AVR: aversive_10-03-12/modules/comm/mf2_server/mf2

00001 /*  
00002  *  Copyright Droids Corporation, Microb Technology, Eirbot (2005)
00003  * 
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
00017  *
00018  *  Revision : $Id: mf2_server.c,v 1.3 2007-05-24 13:08:46 zer0 Exp $
00019  *
00020  */
00021 
00022 /* Olivier MATZ, Droids-corp 2007 */
00023 
00024 #include <stdio.h>
00025 
00026 #include <aversive.h>
00027 #include <aversive/wait.h>
00028 #include <timer.h>
00029 #include <mf2_server.h>
00030 #include <mf2_server_config.h>
00031 
00032 
00033 #define data_Z() do { cbi(DDR(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT); } while(0)
00034 #define data_0() do { sbi(DDR(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT); } while(0)
00035 #define read_data() (bit_is_set(PIN(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT))
00036 #define data_is_Z() (!bit_is_set(DDR(MF2_SERVER_DATA_PORT), MF2_SERVER_DATA_BIT))
00037 
00038 #define clk_Z() do { cbi(DDR(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT); } while(0)
00039 #define clk_0() do { sbi(DDR(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT); } while(0)
00040 #define read_clk() (bit_is_set(PIN(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT))
00041 #define clk_is_Z() (!bit_is_set(DDR(MF2_SERVER_CLK_PORT), MF2_SERVER_CLK_BIT))
00042 
00043 #define MF2_SERVER_STATE_READY 0
00044 #define MF2_SERVER_STATE_SEND  1
00045 #define MF2_SERVER_STATE_RECV  2
00046 
00047 static volatile uint8_t mf2_state=0;
00048 
00049 typedef void (event)(char);
00050 static event * tx_event = NULL;
00051 static event * rx_event = NULL;
00052 static volatile uint8_t mf2_step=0;
00053 static volatile uint8_t mf2_parity_cpt=0;
00054 static volatile char mf2_data_send=0;
00055 static volatile char mf2_data_recv=0;
00056 
00057 
00058 #define WAIT_KBD_CYCLE 600
00059 #define WAIT_KBD_CYCLE4 WAIT_KBD_CYCLE/4
00060 
00061 
00062 void recv(void)
00063 {
00064         uint8_t i;
00065         uint16_t c=0;
00066         uint16_t d=0;
00067         data_Z();
00068         clk_Z();
00069         if (read_data())
00070                 printf("burp\r\n");
00071 /*      wait_4cyc(WAIT_KBD_CYCLE4); */
00072 /*      wait_4cyc(WAIT_KBD_CYCLE4); */
00073 /*      wait_4cyc(WAIT_KBD_CYCLE4); */
00074         clk_0();
00075         wait_4cyc(WAIT_KBD_CYCLE4);
00076         
00077         
00078         for (i=0; i<8 ; i++) {
00079                 if (read_data()) 
00080                         c |= 1 << i;
00081                 clk_Z();
00082                 wait_4cyc(WAIT_KBD_CYCLE4);
00083                 if (read_data()) 
00084                         d |= 1 << i;
00085                 clk_0();
00086                 wait_4cyc(WAIT_KBD_CYCLE4);
00087         }
00088 
00089         // parite
00090         clk_Z();
00091         wait_4cyc(WAIT_KBD_CYCLE4);
00092         clk_0();
00093         wait_4cyc(WAIT_KBD_CYCLE4);
00094 
00095         // ack
00096         clk_Z();
00097         data_0();
00098         wait_4cyc(WAIT_KBD_CYCLE4);
00099         clk_0();
00100         wait_4cyc(WAIT_KBD_CYCLE4);
00101 
00102         // stop
00103         clk_Z();
00104         data_Z();
00105         wait_4cyc(WAIT_KBD_CYCLE4);
00106         clk_0();
00107         wait_4cyc(WAIT_KBD_CYCLE4);
00108         clk_Z();
00109         
00110         printf("%x\r\n", c);
00111         printf("%x\r\n", d);
00112         wait_4cyc(2*WAIT_KBD_CYCLE4);
00113         while(1);
00114 }
00115 
00116 static inline int8_t mf2_server_bus_free(void)
00117 {
00118         return read_clk() && read_data();
00119 }
00120 
00121 
00122 int8_t mf2_server_ready(void)
00123 {
00124         return (mf2_state==MF2_SERVER_STATE_READY && mf2_server_bus_free());
00125 }
00126 
00127 /* a virer XXX */
00128 void disp(char c);
00129 
00130 #if 0
00131 static inline void dump(void)
00132 {
00133         char c=0;
00134         if(read_data()) 
00135                 c|=1;
00136         if(read_clk()) 
00137                 c|=0x10;
00138 
00139         if(data_is_Z()) 
00140                 c|=2;
00141         if(clk_is_Z()) 
00142                 c|=0x20;
00143 
00144         disp((char)(c));
00145 }
00146 #else
00147 #define dump() do {} while(0)
00148 #endif
00149 
00150 void mf2_server_timer_cb(void)
00151 {
00152 /*      static uint16_t i=0; */
00153         static uint16_t t;
00154 
00155         /* if it is just polling */
00156         if (mf2_state == MF2_SERVER_STATE_READY) {
00157                 clk_Z();
00158                 data_Z();
00159 
00160                 /* the central server has something to say */
00161                 if (read_clk() && !read_data()) {
00162                         mf2_state = MF2_SERVER_STATE_RECV;
00163                         mf2_step = 1;
00164                         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_CLK_HALF_PERIOD);
00165                         //                      recv();
00166                         dump();
00167                         return;
00168                 }       
00169                 /* nothing to do if the central server has nothing to say */
00170                 else {
00171                         /* reload timer */
00172                         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_READ_POLL_PERIOD);
00173                         return;
00174                 }
00175         }
00176 
00177         /* an operation is running */
00178 
00179         /* reload timer */
00180         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_CLK_HALF_PERIOD);
00181 
00182         /* XXX we should check if clk is 0 when clk_Z() */
00183         if (mf2_state == MF2_SERVER_STATE_RECV) {
00184                 switch(mf2_step) {
00185                 case 1:
00186                         mf2_data_recv=0;
00187                         dump();
00188                         clk_0();
00189                         break;
00190                 case 2:
00191                         dump();
00192                         clk_Z();
00193                         break;
00194 
00195                 case 3:
00196                 case 5:
00197                 case 7:
00198                 case 9:
00199                 case 11:
00200                 case 13:
00201                 case 15:
00202                 case 17:
00203                         //                      t = timer1_get();
00204                         dump();
00205                         clk_0();
00206                         if(read_data())
00207                                 mf2_data_recv |= (1 << ( (mf2_step-3)/2 ) );
00208                         break;
00209                 case 4:
00210                 case 6:
00211                 case 8:
00212                 case 10:
00213                 case 12:
00214                 case 14:
00215                 case 16:
00216                 case 18:
00217 /*                      printf("%d\n",  timer1_get() - t); */
00218 /*                      while(1); */
00219                         dump();
00220                         clk_Z();
00221                         break;
00222 
00223                 case 19:
00224                         /* parity */
00225                         dump();
00226                         clk_0();
00227                         break;
00228                 case 20:
00229                         dump();
00230                         clk_Z();
00231                         data_0();
00232                         break;
00233                 case 21:
00234                         dump();
00235                         clk_0();
00236                         break;
00237                 case 22:
00238                         dump();
00239                         clk_Z();
00240                         data_Z();
00241                         break;
00242 
00243                 default:
00244                         if (rx_event) {
00245 /*                              c=check_rx_buf(rx_buf); */
00246                                 rx_event((char)(mf2_data_recv));
00247 /*                              rx_event((char)(0xED)); */
00248                         }
00249                         mf2_state = MF2_SERVER_STATE_READY; 
00250                         mf2_step = 0;
00251                         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_READ_POLL_PERIOD);
00252                         return;
00253                 }
00254                 mf2_step++;
00255         }
00256         else {
00257                 switch(mf2_step) {
00258                 case 1:
00259                         data_0();
00260                         break;
00261                 case 2:
00262                         clk_0();
00263                         break;
00264                 case 3:
00265                 case 5:
00266                 case 7:
00267                 case 9:
00268                 case 11:
00269                 case 13:
00270                 case 15:
00271                 case 17:
00272                         if(mf2_data_send & (1<<((mf2_step-3)/2))) {
00273                                 data_Z();
00274                                 mf2_parity_cpt ++;
00275                         }
00276                         else {
00277                                 data_0();
00278                         }
00279                         clk_Z();
00280                         break;
00281                 case 4:
00282                 case 6:
00283                 case 8:
00284                 case 10:
00285                 case 12:
00286                 case 14:
00287                 case 16:
00288                 case 18:
00289                         /* XXX */
00290                         if(!(read_clk())) {
00291 /*                              /\*                     recv(); *\/ */
00292 /*                                                      printf("Ceci est un test\n"); */
00293 /*                                                      printf("%d\n", mf2_step); */
00294 /*                                                      printf("%2.2x\n", mf2_data_send); */
00295 /*                                                      while(1); */
00296                                 mf2_step=0;
00297                                 mf2_state = MF2_SERVER_STATE_RECV;
00298                                 
00299                         }
00300                         clk_0();
00301                         break;
00302 
00303                 case 19:
00304                         if(!(mf2_parity_cpt%2))
00305                                 data_Z();
00306                         else
00307                                 data_0();
00308                         clk_Z();
00309                         break;
00310                 case 20:
00311                         clk_0();
00312                         break;
00313                 case 21:
00314                         clk_Z();
00315                         data_Z();
00316                         break;
00317                 case 22:
00318                         clk_0();
00319                         break;
00320                 case 23:
00321                         clk_Z();
00322                         break;
00323                 case 24:
00324                 case 25:
00325                         break;
00326                 default:
00327                         mf2_state = MF2_SERVER_STATE_READY;
00328                         mf2_step = 0;
00329                         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, timer1_get()+MF2_SERVER_READ_POLL_PERIOD);
00330                         return;
00331                 }
00332                 mf2_step++;
00333         }
00334 }
00335         
00336 
00337 
00338 int8_t mf2_server_send(char c)
00339 {
00340         uint8_t flags;
00341 
00342         IRQ_LOCK(flags);
00343 
00344         if (!mf2_server_ready()) {
00345                 IRQ_UNLOCK(flags);
00346                 //              recv();
00347                 return -1;
00348         }
00349 
00350         mf2_state = MF2_SERVER_STATE_SEND;
00351         mf2_step = 1;
00352         mf2_data_send = c;
00353         mf2_parity_cpt = 0;
00354         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, 
00355                                          timer1_get()+MF2_SERVER_CLK_HALF_PERIOD);
00356         clk_Z();
00357         data_Z();
00358         IRQ_UNLOCK(flags);
00359         return 0;
00360 }
00361 
00362 void mf2_server_init(void)
00363 {
00364         cbi(MF2_SERVER_DATA_PORT, MF2_SERVER_DATA_BIT);
00365         cbi(MF2_SERVER_CLK_PORT, MF2_SERVER_CLK_BIT);
00366 
00367         timer1A_register_OC_intr_at_tics(mf2_server_timer_cb, 
00368                                          timer1_get()+MF2_SERVER_READ_POLL_PERIOD);
00369 
00370         /* XXX choose timer */
00371         clk_Z();
00372         data_Z();
00373 }
00374 
00375 /* This function is used to register another function which will be */
00376 /* executed at each byte transmission. */
00377 void mf2_server_register_tx_event(void (*f)(char))
00378 {
00379         u08 flags;
00380         IRQ_LOCK(flags);
00381         tx_event = f;
00382         IRQ_UNLOCK(flags);
00383 }
00384 
00385 /* This function is used to register another function which will be */
00386 /* executed at each byte reception. */
00387 void mf2_server_register_rx_event(void (*f)(char))
00388 {
00389         u08 flags;
00390         IRQ_LOCK(flags);
00391         rx_event = f;
00392         IRQ_UNLOCK(flags);
00393 }
00394
aversive_10-03-12/modules/comm/mf2_server/mf2_server.c
