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Defines | |
| #define | TIMER0_PRESCALER_DIV_0 0 |
| #define | TIMER0_PRESCALER_DIV_1 1 |
| #define | TIMER0_PRESCALER_DIV_8 2 |
| #define | TIMER0_PRESCALER_DIV_64 3 |
| #define | TIMER0_PRESCALER_DIV_256 4 |
| #define | TIMER0_PRESCALER_DIV_1024 5 |
| #define | TIMER0_PRESCALER_DIV_FALL 6 |
| #define | TIMER0_PRESCALER_DIV_RISE 7 |
| #define | TIMER0_PRESCALER_REG_0 0 |
| #define | TIMER0_PRESCALER_REG_1 1 |
| #define | TIMER0_PRESCALER_REG_2 8 |
| #define | TIMER0_PRESCALER_REG_3 64 |
| #define | TIMER0_PRESCALER_REG_4 256 |
| #define | TIMER0_PRESCALER_REG_5 1024 |
| #define | TIMER0_PRESCALER_REG_6 -1 |
| #define | TIMER0_PRESCALER_REG_7 -2 |
| #define | TIMER1_PRESCALER_DIV_0 0 |
| #define | TIMER1_PRESCALER_DIV_1 1 |
| #define | TIMER1_PRESCALER_DIV_8 2 |
| #define | TIMER1_PRESCALER_DIV_64 3 |
| #define | TIMER1_PRESCALER_DIV_256 4 |
| #define | TIMER1_PRESCALER_DIV_1024 5 |
| #define | TIMER1_PRESCALER_DIV_FALL 6 |
| #define | TIMER1_PRESCALER_DIV_RISE 7 |
| #define | TIMER1_PRESCALER_REG_0 0 |
| #define | TIMER1_PRESCALER_REG_1 1 |
| #define | TIMER1_PRESCALER_REG_2 8 |
| #define | TIMER1_PRESCALER_REG_3 64 |
| #define | TIMER1_PRESCALER_REG_4 256 |
| #define | TIMER1_PRESCALER_REG_5 1024 |
| #define | TIMER1_PRESCALER_REG_6 -1 |
| #define | TIMER1_PRESCALER_REG_7 -2 |
| #define | TIMER2_PRESCALER_DIV_0 0 |
| #define | TIMER2_PRESCALER_DIV_1 1 |
| #define | TIMER2_PRESCALER_DIV_8 2 |
| #define | TIMER2_PRESCALER_DIV_32 3 |
| #define | TIMER2_PRESCALER_DIV_64 4 |
| #define | TIMER2_PRESCALER_DIV_128 5 |
| #define | TIMER2_PRESCALER_DIV_256 6 |
| #define | TIMER2_PRESCALER_DIV_1024 7 |
| #define | TIMER2_PRESCALER_REG_0 0 |
| #define | TIMER2_PRESCALER_REG_1 1 |
| #define | TIMER2_PRESCALER_REG_2 8 |
| #define | TIMER2_PRESCALER_REG_3 32 |
| #define | TIMER2_PRESCALER_REG_4 64 |
| #define | TIMER2_PRESCALER_REG_5 128 |
| #define | TIMER2_PRESCALER_REG_6 256 |
| #define | TIMER2_PRESCALER_REG_7 1024 |
| #define | TIMER0_AVAILABLE |
| #define | TIMER1_AVAILABLE |
| #define | TIMER1A_AVAILABLE |
| #define | TIMER1B_AVAILABLE |
| #define | TIMER2_AVAILABLE |
| #define | SIG_OVERFLOW0_NUM 0 |
| #define | SIG_OVERFLOW1_NUM 1 |
| #define | SIG_OVERFLOW2_NUM 2 |
| #define | SIG_OVERFLOW_TOTAL_NUM 3 |
| #define | SIG_OUTPUT_COMPARE1A_NUM 0 |
| #define | SIG_OUTPUT_COMPARE1B_NUM 1 |
| #define | SIG_OUTPUT_COMPARE2_NUM 2 |
| #define | SIG_OUTPUT_COMPARE_TOTAL_NUM 3 |
| #define | PWM1A_NUM 0 |
| #define | PWM1B_NUM 1 |
| #define | PWM2_NUM 2 |
| #define | PWM_TOTAL_NUM 3 |
| #define | SIG_INPUT_CAPTURE1_NUM 0 |
| #define | SIG_INPUT_CAPTURE_TOTAL_NUM 1 |
| #define | WDP0_REG WDTCR |
| #define | WDP1_REG WDTCR |
| #define | WDP2_REG WDTCR |
| #define | WDE_REG WDTCR |
| #define | WDCE_REG WDTCR |
| #define | ICR1H0_REG ICR1H |
| #define | ICR1H1_REG ICR1H |
| #define | ICR1H2_REG ICR1H |
| #define | ICR1H3_REG ICR1H |
| #define | ICR1H4_REG ICR1H |
| #define | ICR1H5_REG ICR1H |
| #define | ICR1H6_REG ICR1H |
| #define | ICR1H7_REG ICR1H |
| #define | MUX0_REG ADMUX |
| #define | MUX1_REG ADMUX |
| #define | MUX2_REG ADMUX |
| #define | MUX3_REG ADMUX |
| #define | ADLAR_REG ADMUX |
| #define | REFS0_REG ADMUX |
| #define | REFS1_REG ADMUX |
| #define | CS00_REG TCCR0 |
| #define | CS01_REG TCCR0 |
| #define | CS02_REG TCCR0 |
| #define | C_REG SREG |
| #define | Z_REG SREG |
| #define | N_REG SREG |
| #define | V_REG SREG |
| #define | S_REG SREG |
| #define | H_REG SREG |
| #define | T_REG SREG |
| #define | I_REG SREG |
| #define | DDB0_REG DDRB |
| #define | DDB1_REG DDRB |
| #define | DDB2_REG DDRB |
| #define | DDB3_REG DDRB |
| #define | DDB4_REG DDRB |
| #define | DDB5_REG DDRB |
| #define | DDB6_REG DDRB |
| #define | DDB7_REG DDRB |
| #define | IVCE_REG GICR |
| #define | IVSEL_REG GICR |
| #define | INT0_REG GICR |
| #define | INT1_REG GICR |
| #define | SPI2X_REG SPSR |
| #define | WCOL_REG SPSR |
| #define | SPIF_REG SPSR |
| #define | TWD0_REG TWDR |
| #define | TWD1_REG TWDR |
| #define | TWD2_REG TWDR |
| #define | TWD3_REG TWDR |
| #define | TWD4_REG TWDR |
| #define | TWD5_REG TWDR |
| #define | TWD6_REG TWDR |
| #define | TWD7_REG TWDR |
| #define | EEDR0_REG EEDR |
| #define | EEDR1_REG EEDR |
| #define | EEDR2_REG EEDR |
| #define | EEDR3_REG EEDR |
| #define | EEDR4_REG EEDR |
| #define | EEDR5_REG EEDR |
| #define | EEDR6_REG EEDR |
| #define | EEDR7_REG EEDR |
| #define | DDC0_REG DDRC |
| #define | DDC1_REG DDRC |
| #define | DDC2_REG DDRC |
| #define | DDC3_REG DDRC |
| #define | DDC4_REG DDRC |
| #define | DDC5_REG DDRC |
| #define | DDC6_REG DDRC |
| #define | PIND0_REG PIND |
| #define | PIND1_REG PIND |
| #define | PIND2_REG PIND |
| #define | PIND3_REG PIND |
| #define | PIND4_REG PIND |
| #define | PIND5_REG PIND |
| #define | PIND6_REG PIND |
| #define | PIND7_REG PIND |
| #define | WGM10_REG TCCR1A |
| #define | WGM11_REG TCCR1A |
| #define | FOC1B_REG TCCR1A |
| #define | FOC1A_REG TCCR1A |
| #define | COM1B0_REG TCCR1A |
| #define | COM1B1_REG TCCR1A |
| #define | COM1A0_REG TCCR1A |
| #define | COM1A1_REG TCCR1A |
| #define | DDD0_REG DDRD |
| #define | DDD1_REG DDRD |
| #define | DDD2_REG DDRD |
| #define | DDD3_REG DDRD |
| #define | DDD4_REG DDRD |
| #define | DDD5_REG DDRD |
| #define | DDD6_REG DDRD |
| #define | DDD7_REG DDRD |
| #define | CS10_REG TCCR1B |
| #define | CS11_REG TCCR1B |
| #define | CS12_REG TCCR1B |
| #define | WGM12_REG TCCR1B |
| #define | WGM13_REG TCCR1B |
| #define | ICES1_REG TCCR1B |
| #define | ICNC1_REG TCCR1B |
| #define | INTF0_REG GIFR |
| #define | INTF1_REG GIFR |
| #define | TOIE0_REG TIMSK |
| #define | TOIE1_REG TIMSK |
| #define | OCIE1B_REG TIMSK |
| #define | OCIE1A_REG TIMSK |
| #define | TICIE1_REG TIMSK |
| #define | TOIE2_REG TIMSK |
| #define | OCIE2_REG TIMSK |
| #define | ADPS0_REG ADCSRA |
| #define | ADPS1_REG ADCSRA |
| #define | ADPS2_REG ADCSRA |
| #define | ADIE_REG ADCSRA |
| #define | ADIF_REG ADCSRA |
| #define | ADFR_REG ADCSRA |
| #define | ADSC_REG ADCSRA |
| #define | ADEN_REG ADCSRA |
| #define | MPCM_REG UCSRA |
| #define | U2X_REG UCSRA |
| #define | UPE_REG UCSRA |
| #define | DOR_REG UCSRA |
| #define | FE_REG UCSRA |
| #define | UDRE_REG UCSRA |
| #define | TXC_REG UCSRA |
| #define | RXC_REG UCSRA |
| #define | SPDR0_REG SPDR |
| #define | SPDR1_REG SPDR |
| #define | SPDR2_REG SPDR |
| #define | SPDR3_REG SPDR |
| #define | SPDR4_REG SPDR |
| #define | SPDR5_REG SPDR |
| #define | SPDR6_REG SPDR |
| #define | SPDR7_REG SPDR |
| #define | ACME_REG SFIOR |
| #define | PSR2_REG SFIOR |
| #define | PSR10_REG SFIOR |
| #define | PUD_REG SFIOR |
| #define | ADHSM_REG SFIOR |
| #define | ACIS0_REG ACSR |
| #define | ACIS1_REG ACSR |
| #define | ACIC_REG ACSR |
| #define | ACIE_REG ACSR |
| #define | ACI_REG ACSR |
| #define | ACO_REG ACSR |
| #define | ACBG_REG ACSR |
| #define | ACD_REG ACSR |
| #define | SP8_REG SPH |
| #define | SP9_REG SPH |
| #define | SP10_REG SPH |
| #define | OCR1BL0_REG OCR1BL |
| #define | OCR1BL1_REG OCR1BL |
| #define | OCR1BL2_REG OCR1BL |
| #define | OCR1BL3_REG OCR1BL |
| #define | OCR1BL4_REG OCR1BL |
| #define | OCR1BL5_REG OCR1BL |
| #define | OCR1BL6_REG OCR1BL |
| #define | OCR1BL7_REG OCR1BL |
| #define | TXB8_REG UCSRB |
| #define | RXB8_REG UCSRB |
| #define | UCSZ2_REG UCSRB |
| #define | TXEN_REG UCSRB |
| #define | RXEN_REG UCSRB |
| #define | UDRIE_REG UCSRB |
| #define | TXCIE_REG UCSRB |
| #define | RXCIE_REG UCSRB |
| #define | UCPOL_REG UCSRC |
| #define | UCSZ0_REG UCSRC |
| #define | UCSZ1_REG UCSRC |
| #define | USBS_REG UCSRC |
| #define | UPM0_REG UCSRC |
| #define | UPM1_REG UCSRC |
| #define | UMSEL_REG UCSRC |
| #define | URSEL_REG UCSRC |
| #define | SP0_REG SPL |
| #define | SP1_REG SPL |
| #define | SP2_REG SPL |
| #define | SP3_REG SPL |
| #define | SP4_REG SPL |
| #define | SP5_REG SPL |
| #define | SP6_REG SPL |
| #define | SP7_REG SPL |
| #define | OCR1BH0_REG OCR1BH |
| #define | OCR1BH1_REG OCR1BH |
| #define | OCR1BH2_REG OCR1BH |
| #define | OCR1BH3_REG OCR1BH |
| #define | OCR1BH4_REG OCR1BH |
| #define | OCR1BH5_REG OCR1BH |
| #define | OCR1BH6_REG OCR1BH |
| #define | OCR1BH7_REG OCR1BH |
| #define | UDR0_REG UDR |
| #define | UDR1_REG UDR |
| #define | UDR2_REG UDR |
| #define | UDR3_REG UDR |
| #define | UDR4_REG UDR |
| #define | UDR5_REG UDR |
| #define | UDR6_REG UDR |
| #define | UDR7_REG UDR |
| #define | SPMEN_REG SPMCR |
| #define | PGERS_REG SPMCR |
| #define | PGWRT_REG SPMCR |
| #define | BLBSET_REG SPMCR |
| #define | RWWSRE_REG SPMCR |
| #define | RWWSB_REG SPMCR |
| #define | SPMIE_REG SPMCR |
| #define | UBRR8_REG UBRRH |
| #define | UBRR9_REG UBRRH |
| #define | UBRR10_REG UBRRH |
| #define | UBRR11_REG UBRRH |
| #define | TWBR0_REG TWBR |
| #define | TWBR1_REG TWBR |
| #define | TWBR2_REG TWBR |
| #define | TWBR3_REG TWBR |
| #define | TWBR4_REG TWBR |
| #define | TWBR5_REG TWBR |
| #define | TWBR6_REG TWBR |
| #define | TWBR7_REG TWBR |
| #define | ADCL0_REG ADCL |
| #define | ADCL1_REG ADCL |
| #define | ADCL2_REG ADCL |
| #define | ADCL3_REG ADCL |
| #define | ADCL4_REG ADCL |
| #define | ADCL5_REG ADCL |
| #define | ADCL6_REG ADCL |
| #define | ADCL7_REG ADCL |
| #define | UBRR0_REG UBRRL |
| #define | UBRR1_REG UBRRL |
| #define | UBRR2_REG UBRRL |
| #define | UBRR3_REG UBRRL |
| #define | UBRR4_REG UBRRL |
| #define | UBRR5_REG UBRRL |
| #define | UBRR6_REG UBRRL |
| #define | UBRR7_REG UBRRL |
| #define | EERE_REG EECR |
| #define | EEWE_REG EECR |
| #define | EEMWE_REG EECR |
| #define | EERIE_REG EECR |
| #define | CAL0_REG OSCCAL |
| #define | CAL1_REG OSCCAL |
| #define | CAL2_REG OSCCAL |
| #define | CAL3_REG OSCCAL |
| #define | CAL4_REG OSCCAL |
| #define | CAL5_REG OSCCAL |
| #define | CAL6_REG OSCCAL |
| #define | CAL7_REG OSCCAL |
| #define | TCNT1L0_REG TCNT1L |
| #define | TCNT1L1_REG TCNT1L |
| #define | TCNT1L2_REG TCNT1L |
| #define | TCNT1L3_REG TCNT1L |
| #define | TCNT1L4_REG TCNT1L |
| #define | TCNT1L5_REG TCNT1L |
| #define | TCNT1L6_REG TCNT1L |
| #define | TCNT1L7_REG TCNT1L |
| #define | PORTB0_REG PORTB |
| #define | PORTB1_REG PORTB |
| #define | PORTB2_REG PORTB |
| #define | PORTB3_REG PORTB |
| #define | PORTB4_REG PORTB |
| #define | PORTB5_REG PORTB |
| #define | PORTB6_REG PORTB |
| #define | PORTB7_REG PORTB |
| #define | PORTD0_REG PORTD |
| #define | PORTD1_REG PORTD |
| #define | PORTD2_REG PORTD |
| #define | PORTD3_REG PORTD |
| #define | PORTD4_REG PORTD |
| #define | PORTD5_REG PORTD |
| #define | PORTD6_REG PORTD |
| #define | PORTD7_REG PORTD |
| #define | TCNT1H0_REG TCNT1H |
| #define | TCNT1H1_REG TCNT1H |
| #define | TCNT1H2_REG TCNT1H |
| #define | TCNT1H3_REG TCNT1H |
| #define | TCNT1H4_REG TCNT1H |
| #define | TCNT1H5_REG TCNT1H |
| #define | TCNT1H6_REG TCNT1H |
| #define | TCNT1H7_REG TCNT1H |
| #define | PORTC0_REG PORTC |
| #define | PORTC1_REG PORTC |
| #define | PORTC2_REG PORTC |
| #define | PORTC3_REG PORTC |
| #define | PORTC4_REG PORTC |
| #define | PORTC5_REG PORTC |
| #define | PORTC6_REG PORTC |
| #define | ADCH0_REG ADCH |
| #define | ADCH1_REG ADCH |
| #define | ADCH2_REG ADCH |
| #define | ADCH3_REG ADCH |
| #define | ADCH4_REG ADCH |
| #define | ADCH5_REG ADCH |
| #define | ADCH6_REG ADCH |
| #define | ADCH7_REG ADCH |
| #define | TWIE_REG TWCR |
| #define | TWEN_REG TWCR |
| #define | TWWC_REG TWCR |
| #define | TWSTO_REG TWCR |
| #define | TWSTA_REG TWCR |
| #define | TWEA_REG TWCR |
| #define | TWINT_REG TWCR |
| #define | TCNT00_REG TCNT0 |
| #define | TCNT01_REG TCNT0 |
| #define | TCNT02_REG TCNT0 |
| #define | TCNT03_REG TCNT0 |
| #define | TCNT04_REG TCNT0 |
| #define | TCNT05_REG TCNT0 |
| #define | TCNT06_REG TCNT0 |
| #define | TCNT07_REG TCNT0 |
| #define | PORF_REG MCUCSR |
| #define | EXTRF_REG MCUCSR |
| #define | BORF_REG MCUCSR |
| #define | WDRF_REG MCUCSR |
| #define | TWGCE_REG TWAR |
| #define | TWA0_REG TWAR |
| #define | TWA1_REG TWAR |
| #define | TWA2_REG TWAR |
| #define | TWA3_REG TWAR |
| #define | TWA4_REG TWAR |
| #define | TWA5_REG TWAR |
| #define | TWA6_REG TWAR |
| #define | CS20_REG TCCR2 |
| #define | CS21_REG TCCR2 |
| #define | CS22_REG TCCR2 |
| #define | WGM21_REG TCCR2 |
| #define | COM20_REG TCCR2 |
| #define | COM21_REG TCCR2 |
| #define | WGM20_REG TCCR2 |
| #define | FOC2_REG TCCR2 |
| #define | TOV0_REG TIFR |
| #define | TOV1_REG TIFR |
| #define | OCF1B_REG TIFR |
| #define | OCF1A_REG TIFR |
| #define | ICF1_REG TIFR |
| #define | TOV2_REG TIFR |
| #define | OCF2_REG TIFR |
| #define | EEAR8_REG EEARH |
| #define | TCNT2_0_REG TCNT2 |
| #define | TCNT2_1_REG TCNT2 |
| #define | TCNT2_2_REG TCNT2 |
| #define | TCNT2_3_REG TCNT2 |
| #define | TCNT2_4_REG TCNT2 |
| #define | TCNT2_5_REG TCNT2 |
| #define | TCNT2_6_REG TCNT2 |
| #define | TCNT2_7_REG TCNT2 |
| #define | EEAR0_REG EEARL |
| #define | EEAR1_REG EEARL |
| #define | EEAR2_REG EEARL |
| #define | EEAR3_REG EEARL |
| #define | EEAR4_REG EEARL |
| #define | EEAR5_REG EEARL |
| #define | EEAR6_REG EEARL |
| #define | EEAR7_REG EEARL |
| #define | TWPS0_REG TWSR |
| #define | TWPS1_REG TWSR |
| #define | TWS3_REG TWSR |
| #define | TWS4_REG TWSR |
| #define | TWS5_REG TWSR |
| #define | TWS6_REG TWSR |
| #define | TWS7_REG TWSR |
| #define | PINC0_REG PINC |
| #define | PINC1_REG PINC |
| #define | PINC2_REG PINC |
| #define | PINC3_REG PINC |
| #define | PINC4_REG PINC |
| #define | PINC5_REG PINC |
| #define | PINC6_REG PINC |
| #define | PINB0_REG PINB |
| #define | PINB1_REG PINB |
| #define | PINB2_REG PINB |
| #define | PINB3_REG PINB |
| #define | PINB4_REG PINB |
| #define | PINB5_REG PINB |
| #define | PINB6_REG PINB |
| #define | PINB7_REG PINB |
| #define | ISC00_REG MCUCR |
| #define | ISC01_REG MCUCR |
| #define | ISC10_REG MCUCR |
| #define | ISC11_REG MCUCR |
| #define | SM0_REG MCUCR |
| #define | SM1_REG MCUCR |
| #define | SM2_REG MCUCR |
| #define | SE_REG MCUCR |
| #define | OCR1AH0_REG OCR1AH |
| #define | OCR1AH1_REG OCR1AH |
| #define | OCR1AH2_REG OCR1AH |
| #define | OCR1AH3_REG OCR1AH |
| #define | OCR1AH4_REG OCR1AH |
| #define | OCR1AH5_REG OCR1AH |
| #define | OCR1AH6_REG OCR1AH |
| #define | OCR1AH7_REG OCR1AH |
| #define | OCR1AL0_REG OCR1AL |
| #define | OCR1AL1_REG OCR1AL |
| #define | OCR1AL2_REG OCR1AL |
| #define | OCR1AL3_REG OCR1AL |
| #define | OCR1AL4_REG OCR1AL |
| #define | OCR1AL5_REG OCR1AL |
| #define | OCR1AL6_REG OCR1AL |
| #define | OCR1AL7_REG OCR1AL |
| #define | SPR0_REG SPCR |
| #define | SPR1_REG SPCR |
| #define | CPHA_REG SPCR |
| #define | CPOL_REG SPCR |
| #define | MSTR_REG SPCR |
| #define | DORD_REG SPCR |
| #define | SPE_REG SPCR |
| #define | SPIE_REG SPCR |
| #define | TCR2UB_REG ASSR |
| #define | OCR2UB_REG ASSR |
| #define | TCN2UB_REG ASSR |
| #define | AS2_REG ASSR |
| #define | OCR2_0_REG OCR2 |
| #define | OCR2_1_REG OCR2 |
| #define | OCR2_2_REG OCR2 |
| #define | OCR2_3_REG OCR2 |
| #define | OCR2_4_REG OCR2 |
| #define | OCR2_5_REG OCR2 |
| #define | OCR2_6_REG OCR2 |
| #define | OCR2_7_REG OCR2 |
| #define | ICR1L0_REG ICR1L |
| #define | ICR1L1_REG ICR1L |
| #define | ICR1L2_REG ICR1L |
| #define | ICR1L3_REG ICR1L |
| #define | ICR1L4_REG ICR1L |
| #define | ICR1L5_REG ICR1L |
| #define | ICR1L6_REG ICR1L |
| #define | ICR1L7_REG ICR1L |
| #define | ICP_PORT PORTB |
| #define | ICP_BIT 0 |
| #define | OC1A_PORT PORTB |
| #define | OC1A_BIT 1 |
| #define | SS_PORT PORTB |
| #define | SS_BIT 2 |
| #define | OC1B_PORT PORTB |
| #define | OC1B_BIT 2 |
| #define | MOSI_PORT PORTB |
| #define | MOSI_BIT 3 |
| #define | OC2_PORT PORTB |
| #define | OC2_BIT 3 |
| #define | MISO_PORT PORTB |
| #define | MISO_BIT 4 |
| #define | SCK_PORT PORTB |
| #define | SCK_BIT 5 |
| #define | XTAL1_PORT PORTB |
| #define | XTAL1_BIT 6 |
| #define | TOSC1_PORT PORTB |
| #define | TOSC1_BIT 6 |
| #define | XTAL2_PORT PORTB |
| #define | XTAL2_BIT 7 |
| #define | TOSC2_PORT PORTB |
| #define | TOSC2_BIT 7 |
| #define | ADC0_PORT PORTC |
| #define | ADC0_BIT 0 |
| #define | ADC1_PORT PORTC |
| #define | ADC1_BIT 1 |
| #define | ADC2_PORT PORTC |
| #define | ADC2_BIT 2 |
| #define | ADC3_PORT PORTC |
| #define | ADC3_BIT 3 |
| #define | ADC4_PORT PORTC |
| #define | ADC4_BIT 4 |
| #define | SDA_PORT PORTC |
| #define | SDA_BIT 4 |
| #define | ADC5_PORT PORTC |
| #define | ADC5_BIT 5 |
| #define | SCL_PORT PORTC |
| #define | SCL_BIT 5 |
| #define | RESET_PORT PORTC |
| #define | RESET_BIT 6 |
| #define | RXD_PORT PORTD |
| #define | RXD_BIT 0 |
| #define | TXD_PORT PORTD |
| #define | TXD_BIT 1 |
| #define | INT0_PORT PORTD |
| #define | INT0_BIT 2 |
| #define | IN1_PORT PORTD |
| #define | IN1_BIT 3 |
| #define | XCK_PORT PORTD |
| #define | XCK_BIT 4 |
| #define | T0_PORT PORTD |
| #define | T0_BIT 4 |
| #define | T1_PORT PORTD |
| #define | T1_BIT 5 |
| #define | AIN0_PORT PORTD |
| #define | AIN0_BIT 6 |
| #define | AIN1_PORT PORTD |
| #define | AIN1_BIT 7 |
1.5.6