00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE1A_NUM 0
00100 #define SIG_OUTPUT_COMPARE1B_NUM 1
00101 #define SIG_OUTPUT_COMPARE2_NUM 2
00102 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
00103
00104
00105 #define PWM1A_NUM 0
00106 #define PWM1B_NUM 1
00107 #define PWM2_NUM 2
00108 #define PWM_TOTAL_NUM 3
00109
00110
00111 #define SIG_INPUT_CAPTURE1_NUM 0
00112 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00113
00114
00115
00116 #define WDP0_REG WDTCR
00117 #define WDP1_REG WDTCR
00118 #define WDP2_REG WDTCR
00119 #define WDE_REG WDTCR
00120 #define WDCE_REG WDTCR
00121
00122
00123 #define ICR1H0_REG ICR1H
00124 #define ICR1H1_REG ICR1H
00125 #define ICR1H2_REG ICR1H
00126 #define ICR1H3_REG ICR1H
00127 #define ICR1H4_REG ICR1H
00128 #define ICR1H5_REG ICR1H
00129 #define ICR1H6_REG ICR1H
00130 #define ICR1H7_REG ICR1H
00131
00132
00133 #define MUX0_REG ADMUX
00134 #define MUX1_REG ADMUX
00135 #define MUX2_REG ADMUX
00136 #define MUX3_REG ADMUX
00137 #define ADLAR_REG ADMUX
00138 #define REFS0_REG ADMUX
00139 #define REFS1_REG ADMUX
00140
00141
00142 #define CS00_REG TCCR0
00143 #define CS01_REG TCCR0
00144 #define CS02_REG TCCR0
00145
00146
00147 #define C_REG SREG
00148 #define Z_REG SREG
00149 #define N_REG SREG
00150 #define V_REG SREG
00151 #define S_REG SREG
00152 #define H_REG SREG
00153 #define T_REG SREG
00154 #define I_REG SREG
00155
00156
00157 #define DDB0_REG DDRB
00158 #define DDB1_REG DDRB
00159 #define DDB2_REG DDRB
00160 #define DDB3_REG DDRB
00161 #define DDB4_REG DDRB
00162 #define DDB5_REG DDRB
00163 #define DDB6_REG DDRB
00164 #define DDB7_REG DDRB
00165
00166
00167 #define IVCE_REG GICR
00168 #define IVSEL_REG GICR
00169 #define INT0_REG GICR
00170 #define INT1_REG GICR
00171
00172
00173 #define SPI2X_REG SPSR
00174 #define WCOL_REG SPSR
00175 #define SPIF_REG SPSR
00176
00177
00178 #define TWD0_REG TWDR
00179 #define TWD1_REG TWDR
00180 #define TWD2_REG TWDR
00181 #define TWD3_REG TWDR
00182 #define TWD4_REG TWDR
00183 #define TWD5_REG TWDR
00184 #define TWD6_REG TWDR
00185 #define TWD7_REG TWDR
00186
00187
00188 #define EEDR0_REG EEDR
00189 #define EEDR1_REG EEDR
00190 #define EEDR2_REG EEDR
00191 #define EEDR3_REG EEDR
00192 #define EEDR4_REG EEDR
00193 #define EEDR5_REG EEDR
00194 #define EEDR6_REG EEDR
00195 #define EEDR7_REG EEDR
00196
00197
00198 #define DDC0_REG DDRC
00199 #define DDC1_REG DDRC
00200 #define DDC2_REG DDRC
00201 #define DDC3_REG DDRC
00202 #define DDC4_REG DDRC
00203 #define DDC5_REG DDRC
00204 #define DDC6_REG DDRC
00205
00206
00207 #define PIND0_REG PIND
00208 #define PIND1_REG PIND
00209 #define PIND2_REG PIND
00210 #define PIND3_REG PIND
00211 #define PIND4_REG PIND
00212 #define PIND5_REG PIND
00213 #define PIND6_REG PIND
00214 #define PIND7_REG PIND
00215
00216
00217 #define WGM10_REG TCCR1A
00218 #define WGM11_REG TCCR1A
00219 #define FOC1B_REG TCCR1A
00220 #define FOC1A_REG TCCR1A
00221 #define COM1B0_REG TCCR1A
00222 #define COM1B1_REG TCCR1A
00223 #define COM1A0_REG TCCR1A
00224 #define COM1A1_REG TCCR1A
00225
00226
00227 #define DDD0_REG DDRD
00228 #define DDD1_REG DDRD
00229 #define DDD2_REG DDRD
00230 #define DDD3_REG DDRD
00231 #define DDD4_REG DDRD
00232 #define DDD5_REG DDRD
00233 #define DDD6_REG DDRD
00234 #define DDD7_REG DDRD
00235
00236
00237 #define CS10_REG TCCR1B
00238 #define CS11_REG TCCR1B
00239 #define CS12_REG TCCR1B
00240 #define WGM12_REG TCCR1B
00241 #define WGM13_REG TCCR1B
00242 #define ICES1_REG TCCR1B
00243 #define ICNC1_REG TCCR1B
00244
00245
00246 #define INTF0_REG GIFR
00247 #define INTF1_REG GIFR
00248
00249
00250 #define TOIE0_REG TIMSK
00251 #define TOIE1_REG TIMSK
00252 #define OCIE1B_REG TIMSK
00253 #define OCIE1A_REG TIMSK
00254 #define TICIE1_REG TIMSK
00255 #define TOIE2_REG TIMSK
00256 #define OCIE2_REG TIMSK
00257
00258
00259 #define ADPS0_REG ADCSRA
00260 #define ADPS1_REG ADCSRA
00261 #define ADPS2_REG ADCSRA
00262 #define ADIE_REG ADCSRA
00263 #define ADIF_REG ADCSRA
00264 #define ADFR_REG ADCSRA
00265 #define ADSC_REG ADCSRA
00266 #define ADEN_REG ADCSRA
00267
00268
00269 #define MPCM_REG UCSRA
00270 #define U2X_REG UCSRA
00271 #define UPE_REG UCSRA
00272 #define DOR_REG UCSRA
00273 #define FE_REG UCSRA
00274 #define UDRE_REG UCSRA
00275 #define TXC_REG UCSRA
00276 #define RXC_REG UCSRA
00277
00278
00279 #define SPDR0_REG SPDR
00280 #define SPDR1_REG SPDR
00281 #define SPDR2_REG SPDR
00282 #define SPDR3_REG SPDR
00283 #define SPDR4_REG SPDR
00284 #define SPDR5_REG SPDR
00285 #define SPDR6_REG SPDR
00286 #define SPDR7_REG SPDR
00287
00288
00289 #define ACME_REG SFIOR
00290 #define PSR2_REG SFIOR
00291 #define PSR10_REG SFIOR
00292 #define PUD_REG SFIOR
00293 #define ADHSM_REG SFIOR
00294
00295
00296 #define ACIS0_REG ACSR
00297 #define ACIS1_REG ACSR
00298 #define ACIC_REG ACSR
00299 #define ACIE_REG ACSR
00300 #define ACI_REG ACSR
00301 #define ACO_REG ACSR
00302 #define ACBG_REG ACSR
00303 #define ACD_REG ACSR
00304
00305
00306 #define SP8_REG SPH
00307 #define SP9_REG SPH
00308 #define SP10_REG SPH
00309
00310
00311 #define OCR1BL0_REG OCR1BL
00312 #define OCR1BL1_REG OCR1BL
00313 #define OCR1BL2_REG OCR1BL
00314 #define OCR1BL3_REG OCR1BL
00315 #define OCR1BL4_REG OCR1BL
00316 #define OCR1BL5_REG OCR1BL
00317 #define OCR1BL6_REG OCR1BL
00318 #define OCR1BL7_REG OCR1BL
00319
00320
00321 #define TXB8_REG UCSRB
00322 #define RXB8_REG UCSRB
00323 #define UCSZ2_REG UCSRB
00324 #define TXEN_REG UCSRB
00325 #define RXEN_REG UCSRB
00326 #define UDRIE_REG UCSRB
00327 #define TXCIE_REG UCSRB
00328 #define RXCIE_REG UCSRB
00329
00330
00331 #define UCPOL_REG UCSRC
00332 #define UCSZ0_REG UCSRC
00333 #define UCSZ1_REG UCSRC
00334 #define USBS_REG UCSRC
00335 #define UPM0_REG UCSRC
00336 #define UPM1_REG UCSRC
00337 #define UMSEL_REG UCSRC
00338 #define URSEL_REG UCSRC
00339
00340
00341 #define SP0_REG SPL
00342 #define SP1_REG SPL
00343 #define SP2_REG SPL
00344 #define SP3_REG SPL
00345 #define SP4_REG SPL
00346 #define SP5_REG SPL
00347 #define SP6_REG SPL
00348 #define SP7_REG SPL
00349
00350
00351 #define OCR1BH0_REG OCR1BH
00352 #define OCR1BH1_REG OCR1BH
00353 #define OCR1BH2_REG OCR1BH
00354 #define OCR1BH3_REG OCR1BH
00355 #define OCR1BH4_REG OCR1BH
00356 #define OCR1BH5_REG OCR1BH
00357 #define OCR1BH6_REG OCR1BH
00358 #define OCR1BH7_REG OCR1BH
00359
00360
00361 #define UDR0_REG UDR
00362 #define UDR1_REG UDR
00363 #define UDR2_REG UDR
00364 #define UDR3_REG UDR
00365 #define UDR4_REG UDR
00366 #define UDR5_REG UDR
00367 #define UDR6_REG UDR
00368 #define UDR7_REG UDR
00369
00370
00371 #define SPMEN_REG SPMCR
00372 #define PGERS_REG SPMCR
00373 #define PGWRT_REG SPMCR
00374 #define BLBSET_REG SPMCR
00375 #define RWWSRE_REG SPMCR
00376 #define RWWSB_REG SPMCR
00377 #define SPMIE_REG SPMCR
00378
00379
00380 #define UBRR8_REG UBRRH
00381 #define UBRR9_REG UBRRH
00382 #define UBRR10_REG UBRRH
00383 #define UBRR11_REG UBRRH
00384
00385
00386 #define TWBR0_REG TWBR
00387 #define TWBR1_REG TWBR
00388 #define TWBR2_REG TWBR
00389 #define TWBR3_REG TWBR
00390 #define TWBR4_REG TWBR
00391 #define TWBR5_REG TWBR
00392 #define TWBR6_REG TWBR
00393 #define TWBR7_REG TWBR
00394
00395
00396 #define ADCL0_REG ADCL
00397 #define ADCL1_REG ADCL
00398 #define ADCL2_REG ADCL
00399 #define ADCL3_REG ADCL
00400 #define ADCL4_REG ADCL
00401 #define ADCL5_REG ADCL
00402 #define ADCL6_REG ADCL
00403 #define ADCL7_REG ADCL
00404
00405
00406 #define UBRR0_REG UBRRL
00407 #define UBRR1_REG UBRRL
00408 #define UBRR2_REG UBRRL
00409 #define UBRR3_REG UBRRL
00410 #define UBRR4_REG UBRRL
00411 #define UBRR5_REG UBRRL
00412 #define UBRR6_REG UBRRL
00413 #define UBRR7_REG UBRRL
00414
00415
00416 #define EERE_REG EECR
00417 #define EEWE_REG EECR
00418 #define EEMWE_REG EECR
00419 #define EERIE_REG EECR
00420
00421
00422 #define CAL0_REG OSCCAL
00423 #define CAL1_REG OSCCAL
00424 #define CAL2_REG OSCCAL
00425 #define CAL3_REG OSCCAL
00426 #define CAL4_REG OSCCAL
00427 #define CAL5_REG OSCCAL
00428 #define CAL6_REG OSCCAL
00429 #define CAL7_REG OSCCAL
00430
00431
00432 #define TCNT1L0_REG TCNT1L
00433 #define TCNT1L1_REG TCNT1L
00434 #define TCNT1L2_REG TCNT1L
00435 #define TCNT1L3_REG TCNT1L
00436 #define TCNT1L4_REG TCNT1L
00437 #define TCNT1L5_REG TCNT1L
00438 #define TCNT1L6_REG TCNT1L
00439 #define TCNT1L7_REG TCNT1L
00440
00441
00442 #define PORTB0_REG PORTB
00443 #define PORTB1_REG PORTB
00444 #define PORTB2_REG PORTB
00445 #define PORTB3_REG PORTB
00446 #define PORTB4_REG PORTB
00447 #define PORTB5_REG PORTB
00448 #define PORTB6_REG PORTB
00449 #define PORTB7_REG PORTB
00450
00451
00452 #define PORTD0_REG PORTD
00453 #define PORTD1_REG PORTD
00454 #define PORTD2_REG PORTD
00455 #define PORTD3_REG PORTD
00456 #define PORTD4_REG PORTD
00457 #define PORTD5_REG PORTD
00458 #define PORTD6_REG PORTD
00459 #define PORTD7_REG PORTD
00460
00461
00462 #define TCNT1H0_REG TCNT1H
00463 #define TCNT1H1_REG TCNT1H
00464 #define TCNT1H2_REG TCNT1H
00465 #define TCNT1H3_REG TCNT1H
00466 #define TCNT1H4_REG TCNT1H
00467 #define TCNT1H5_REG TCNT1H
00468 #define TCNT1H6_REG TCNT1H
00469 #define TCNT1H7_REG TCNT1H
00470
00471
00472 #define PORTC0_REG PORTC
00473 #define PORTC1_REG PORTC
00474 #define PORTC2_REG PORTC
00475 #define PORTC3_REG PORTC
00476 #define PORTC4_REG PORTC
00477 #define PORTC5_REG PORTC
00478 #define PORTC6_REG PORTC
00479
00480
00481 #define ADCH0_REG ADCH
00482 #define ADCH1_REG ADCH
00483 #define ADCH2_REG ADCH
00484 #define ADCH3_REG ADCH
00485 #define ADCH4_REG ADCH
00486 #define ADCH5_REG ADCH
00487 #define ADCH6_REG ADCH
00488 #define ADCH7_REG ADCH
00489
00490
00491 #define TWIE_REG TWCR
00492 #define TWEN_REG TWCR
00493 #define TWWC_REG TWCR
00494 #define TWSTO_REG TWCR
00495 #define TWSTA_REG TWCR
00496 #define TWEA_REG TWCR
00497 #define TWINT_REG TWCR
00498
00499
00500 #define TCNT00_REG TCNT0
00501 #define TCNT01_REG TCNT0
00502 #define TCNT02_REG TCNT0
00503 #define TCNT03_REG TCNT0
00504 #define TCNT04_REG TCNT0
00505 #define TCNT05_REG TCNT0
00506 #define TCNT06_REG TCNT0
00507 #define TCNT07_REG TCNT0
00508
00509
00510 #define PORF_REG MCUCSR
00511 #define EXTRF_REG MCUCSR
00512 #define BORF_REG MCUCSR
00513 #define WDRF_REG MCUCSR
00514
00515
00516 #define TWGCE_REG TWAR
00517 #define TWA0_REG TWAR
00518 #define TWA1_REG TWAR
00519 #define TWA2_REG TWAR
00520 #define TWA3_REG TWAR
00521 #define TWA4_REG TWAR
00522 #define TWA5_REG TWAR
00523 #define TWA6_REG TWAR
00524
00525
00526 #define CS20_REG TCCR2
00527 #define CS21_REG TCCR2
00528 #define CS22_REG TCCR2
00529 #define WGM21_REG TCCR2
00530 #define COM20_REG TCCR2
00531 #define COM21_REG TCCR2
00532 #define WGM20_REG TCCR2
00533 #define FOC2_REG TCCR2
00534
00535
00536 #define TOV0_REG TIFR
00537 #define TOV1_REG TIFR
00538 #define OCF1B_REG TIFR
00539 #define OCF1A_REG TIFR
00540 #define ICF1_REG TIFR
00541 #define TOV2_REG TIFR
00542 #define OCF2_REG TIFR
00543
00544
00545 #define EEAR8_REG EEARH
00546
00547
00548 #define TCNT2_0_REG TCNT2
00549 #define TCNT2_1_REG TCNT2
00550 #define TCNT2_2_REG TCNT2
00551 #define TCNT2_3_REG TCNT2
00552 #define TCNT2_4_REG TCNT2
00553 #define TCNT2_5_REG TCNT2
00554 #define TCNT2_6_REG TCNT2
00555 #define TCNT2_7_REG TCNT2
00556
00557
00558 #define EEAR0_REG EEARL
00559 #define EEAR1_REG EEARL
00560 #define EEAR2_REG EEARL
00561 #define EEAR3_REG EEARL
00562 #define EEAR4_REG EEARL
00563 #define EEAR5_REG EEARL
00564 #define EEAR6_REG EEARL
00565 #define EEAR7_REG EEARL
00566
00567
00568 #define TWPS0_REG TWSR
00569 #define TWPS1_REG TWSR
00570 #define TWS3_REG TWSR
00571 #define TWS4_REG TWSR
00572 #define TWS5_REG TWSR
00573 #define TWS6_REG TWSR
00574 #define TWS7_REG TWSR
00575
00576
00577 #define PINC0_REG PINC
00578 #define PINC1_REG PINC
00579 #define PINC2_REG PINC
00580 #define PINC3_REG PINC
00581 #define PINC4_REG PINC
00582 #define PINC5_REG PINC
00583 #define PINC6_REG PINC
00584
00585
00586 #define PINB0_REG PINB
00587 #define PINB1_REG PINB
00588 #define PINB2_REG PINB
00589 #define PINB3_REG PINB
00590 #define PINB4_REG PINB
00591 #define PINB5_REG PINB
00592 #define PINB6_REG PINB
00593 #define PINB7_REG PINB
00594
00595
00596 #define ISC00_REG MCUCR
00597 #define ISC01_REG MCUCR
00598 #define ISC10_REG MCUCR
00599 #define ISC11_REG MCUCR
00600 #define SM0_REG MCUCR
00601 #define SM1_REG MCUCR
00602 #define SM2_REG MCUCR
00603 #define SE_REG MCUCR
00604
00605
00606 #define OCR1AH0_REG OCR1AH
00607 #define OCR1AH1_REG OCR1AH
00608 #define OCR1AH2_REG OCR1AH
00609 #define OCR1AH3_REG OCR1AH
00610 #define OCR1AH4_REG OCR1AH
00611 #define OCR1AH5_REG OCR1AH
00612 #define OCR1AH6_REG OCR1AH
00613 #define OCR1AH7_REG OCR1AH
00614
00615
00616 #define OCR1AL0_REG OCR1AL
00617 #define OCR1AL1_REG OCR1AL
00618 #define OCR1AL2_REG OCR1AL
00619 #define OCR1AL3_REG OCR1AL
00620 #define OCR1AL4_REG OCR1AL
00621 #define OCR1AL5_REG OCR1AL
00622 #define OCR1AL6_REG OCR1AL
00623 #define OCR1AL7_REG OCR1AL
00624
00625
00626 #define SPR0_REG SPCR
00627 #define SPR1_REG SPCR
00628 #define CPHA_REG SPCR
00629 #define CPOL_REG SPCR
00630 #define MSTR_REG SPCR
00631 #define DORD_REG SPCR
00632 #define SPE_REG SPCR
00633 #define SPIE_REG SPCR
00634
00635
00636 #define TCR2UB_REG ASSR
00637 #define OCR2UB_REG ASSR
00638 #define TCN2UB_REG ASSR
00639 #define AS2_REG ASSR
00640
00641
00642 #define OCR2_0_REG OCR2
00643 #define OCR2_1_REG OCR2
00644 #define OCR2_2_REG OCR2
00645 #define OCR2_3_REG OCR2
00646 #define OCR2_4_REG OCR2
00647 #define OCR2_5_REG OCR2
00648 #define OCR2_6_REG OCR2
00649 #define OCR2_7_REG OCR2
00650
00651
00652 #define ICR1L0_REG ICR1L
00653 #define ICR1L1_REG ICR1L
00654 #define ICR1L2_REG ICR1L
00655 #define ICR1L3_REG ICR1L
00656 #define ICR1L4_REG ICR1L
00657 #define ICR1L5_REG ICR1L
00658 #define ICR1L6_REG ICR1L
00659 #define ICR1L7_REG ICR1L
00660
00661
00662 #define ICP_PORT PORTB
00663 #define ICP_BIT 0
00664
00665 #define OC1A_PORT PORTB
00666 #define OC1A_BIT 1
00667
00668 #define SS_PORT PORTB
00669 #define SS_BIT 2
00670 #define OC1B_PORT PORTB
00671 #define OC1B_BIT 2
00672
00673 #define MOSI_PORT PORTB
00674 #define MOSI_BIT 3
00675 #define OC2_PORT PORTB
00676 #define OC2_BIT 3
00677
00678 #define MISO_PORT PORTB
00679 #define MISO_BIT 4
00680
00681 #define SCK_PORT PORTB
00682 #define SCK_BIT 5
00683
00684 #define XTAL1_PORT PORTB
00685 #define XTAL1_BIT 6
00686 #define TOSC1_PORT PORTB
00687 #define TOSC1_BIT 6
00688
00689 #define XTAL2_PORT PORTB
00690 #define XTAL2_BIT 7
00691 #define TOSC2_PORT PORTB
00692 #define TOSC2_BIT 7
00693
00694 #define ADC0_PORT PORTC
00695 #define ADC0_BIT 0
00696
00697 #define ADC1_PORT PORTC
00698 #define ADC1_BIT 1
00699
00700 #define ADC2_PORT PORTC
00701 #define ADC2_BIT 2
00702
00703 #define ADC3_PORT PORTC
00704 #define ADC3_BIT 3
00705
00706 #define ADC4_PORT PORTC
00707 #define ADC4_BIT 4
00708 #define SDA_PORT PORTC
00709 #define SDA_BIT 4
00710
00711 #define ADC5_PORT PORTC
00712 #define ADC5_BIT 5
00713 #define SCL_PORT PORTC
00714 #define SCL_BIT 5
00715
00716 #define RESET_PORT PORTC
00717 #define RESET_BIT 6
00718
00719 #define RXD_PORT PORTD
00720 #define RXD_BIT 0
00721
00722 #define TXD_PORT PORTD
00723 #define TXD_BIT 1
00724
00725 #define INT0_PORT PORTD
00726 #define INT0_BIT 2
00727
00728 #define IN1_PORT PORTD
00729 #define IN1_BIT 3
00730
00731 #define XCK_PORT PORTD
00732 #define XCK_BIT 4
00733 #define T0_PORT PORTD
00734 #define T0_BIT 4
00735
00736 #define T1_PORT PORTD
00737 #define T1_BIT 5
00738
00739 #define AIN0_PORT PORTD
00740 #define AIN0_BIT 6
00741
00742 #define AIN1_PORT PORTD
00743 #define AIN1_BIT 7
00744
00745