AVR: aversive_10-03-12/modules/hardware/pwm/timers

00001 /*  
00002  *  Copyright Droids Corporation, Microb Technology, Eirbot (2005)
00003  * 
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
00017  *
00018  *  Revision : $Id: timers_synch.c,v 1.4 2006-11-03 09:05:13 zer0 Exp $
00019  *
00020  */
00021 
00022 
00044 #include <avr/io.h>
00045 #include <pwm.h> // for config
00046 
00047 #include <timers_synch.h>
00048 
00049 
00050 
00051 #if ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) )
00052 
00053 
00054 void pwm_synch(void)
00055 {
00056         uint8_t flags;
00057 
00058 // computations of prescale for sync
00059 #ifdef TIMER0_SYNCH
00060   #undef PWM_SYNCH_PRESCALE
00061   #define PWM_SYNCH_PRESCALE TIMER0_PRESCALE
00062 #endif
00063 #ifdef TIMER1_SYNCH
00064   #undef PWM_SYNCH_PRESCALE
00065   #define PWM_SYNCH_PRESCALE TIMER1_PRESCALE
00066 #endif
00067 #ifdef TIMER2_SYNCH
00068   #undef PWM_SYNCH_PRESCALE
00069   #define PWM_SYNCH_PRESCALE TIMER2_PRESCALE
00070 #endif
00071 #ifdef TIMER3_SYNCH
00072   #undef PWM_SYNCH_PRESCALE
00073   #define PWM_SYNCH_PRESCALE TIMER3_PRESCALE
00074 #endif
00075 
00076 // verify that all the prescales are the same
00077 
00078 #ifdef TIMER0_SYNCH
00079   #if (PWM_SYNCH_PRESCALE  != TIMER0_PRESCALE)
00080     #error TIMER0: not the same prescaler for synchronized PWMs, please verify your pwm_config.h
00081   #endif
00082 #endif
00083 #ifdef TIMER1_SYNCH
00084   #if (PWM_SYNCH_PRESCALE  != TIMER1_PRESCALE)
00085     #error TIMER1: not the same prescaler for synchronized PWMs, please verify your pwm_config.h
00086   #endif
00087 #endif
00088 #ifdef TIMER2_SYNCH
00089   #if (PWM_SYNCH_PRESCALE  != TIMER2_PRESCALE)
00090     #error TIMER2: not the same prescaler for synchronized PWMs, please verify your pwm_config.h
00091   #endif
00092 #endif
00093 #ifdef TIMER3_SYNCH
00094   #if (PWM_SYNCH_PRESCALE  != TIMER3_PRESCALE)
00095     #error TIMER3: not the same prescaler for synchronized PWMs, please verify your pwm_config.h
00096   #endif
00097 #endif
00098 
00099 
00100 
00101 // step between timer activations
00102 
00103 #if (PWM_SYNCH_PRESCALE  == TIMER_8_PRESCALE_1)
00104   #define STEP 1
00105 #else
00106   #define STEP 0
00107 #endif
00108 
00109 
00110   
00111   IRQ_LOCK(flags);
00112   
00113   {
00114   //***************************************************
00115   // register declarations
00116   //***************************************************
00117   
00118 #ifdef TIMER0_SYNCH
00119   register uint8_t tccr0;
00120 #endif
00121 #ifdef TIMER1_SYNCH
00122   register uint8_t tccr1b;
00123 #endif
00124 #ifdef TIMER2_SYNCH
00125   register uint8_t tccr2;
00126 #endif
00127 #ifdef TIMER3_SYNCH
00128   register uint8_t tccr3b;
00129 #endif
00130 
00131   register uint8_t sfior;
00132 
00133   //***************************************************
00134   // save state and stop timers
00135   //***************************************************
00136   
00137 #ifdef TIMER0_SYNCH
00138   tccr0 = TCCR0;
00139   TCCR0 = 0x00;
00140 #endif
00141 #ifdef TIMER1_SYNCH
00142  tccr1b = TCCR1B;
00143  TCCR1B = 0x00;
00144 #endif
00145 #ifdef TIMER2_SYNCH
00146   tccr2 = TCCR2;
00147   TCCR2 = 0x00;
00148 #endif
00149 #ifdef TIMER3_SYNCH
00150   tccr3b = TCCR3B;
00151   TCCR3B = 0x00;
00152 #endif
00153 
00154   //***************************************************
00155   // the timers are now stopped, we set the TCNT's to given values
00156   // set timers to given values
00157   // the timers would then be startes one after another,
00158   // and synchronize themselves while starting with the right offset
00159   //***************************************************
00160 
00161 #ifdef TIMER0_SYNCH
00162   TCNT0 = 0;
00163 #endif
00164 #ifdef TIMER1_SYNCH
00165   TCNT1H = 0;
00166   TCNT1L = 1l * STEP;
00167 #endif
00168 #ifdef TIMER2_SYNCH
00169   TCNT2 = 2l * STEP;
00170 #endif
00171 #ifdef TIMER3_SYNCH
00172   TCNT3H = 0;
00173   TCNT3L = 4l * STEP; // one more, cause TCCR acess takes one instruction more (see TCCR3B acess, down)
00174 #endif
00175 
00176   //***************************************************
00177   // resetting prescalers (some could influence unwanted timers, enshure that there are no problems with that )
00178   // this is done this manner to be absolutely synchronous
00179   //***************************************************
00180 
00181   sfior = SFIOR;
00182 
00183   // mega 128
00184 #if (defined PSR321) && ( (defined TIMER3_SYNCH) || (defined TIMER2_SYNCH)  || (defined TIMER1_SYNCH) )
00185   sfior |= (1<<PSR321);
00186 #endif
00187 #if (defined PSR0) && (defined TIMER0_SYNCH)
00188   sfior |= (1<<PSR0);
00189 #endif
00190   // mega  163, 32 ...
00191 #if (defined PSR10) && ( (defined TIMER1_SYNCH) || (defined TIMER0_SYNCH))
00192   sfior |= (1<<PSR10);
00193 #endif
00194 #if (defined PSR2) && (defined TIMER2_SYNCH)
00195   sfior |= (1<<PSR2);
00196 #endif
00197 
00199   // here begins the time critical  section
00200   // this all is done within less than 8 cycles, to assure function even with a prescaler set to 8
00202   
00203   
00204   SFIOR = sfior;
00205   
00206   
00207   //***************************************************
00208   // running timers
00209   //***************************************************
00210   
00211 #ifdef TIMER0_SYNCH
00212   TCCR0 = tccr0;
00213 #else
00214   nop();
00215 #endif
00216 #ifdef TIMER1_SYNCH
00217   TCCR1B = tccr1b;
00218 #else
00219   nop();
00220 #endif
00221 #ifdef TIMER2_SYNCH
00222   TCCR2 = tccr2;
00223 #else
00224   nop();
00225 #endif
00226 #ifdef TIMER3_SYNCH
00227   TCCR3B = tccr3b; // this instruction takes 2 cycles (on ATMEGA128)
00228 #else
00229   /* nop(); // optimized, not necessary, coz nothing after
00230   nop(); */
00231 #endif
00232 
00234   // here ends the time critical  section
00235   // this all is done within less than 8 cycles, to assure function even with a prescaler set to 8
00237 
00238 
00239 
00240 
00241   }
00242   IRQ_UNLOCK(flags);
00243 
00244 
00245 }
00246 
00247 #endif // ( (defined TIMER0_SYNCH) || (defined TIMER1_SYNCH) || (defined TIMER2_SYNCH) || (defined TIMER3_SYNCH) )
aversive_10-03-12/modules/hardware/pwm/timers_synch.c
