AVR: aversive_10-03-12/modules/hardware/timer/timer

00001 /*  
00002  *  Copyright Droids Corporation, Microb Technology, Eirbot (2006)
00003  * 
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
00017  *
00018  *  Revision : $Id: timer_prescaler.h,v 1.3 2009-03-15 21:51:19 zer0 Exp $
00019  *
00020  */
00021 
00022 #ifndef _TIMER_PRESCALER_H_
00023 #define _TIMER_PRESCALER_H_
00024 
00025 /* return <0 on error, else return reg value */ 
00026 /* This static inline function is very optimized if div is
00027  * a constant */
00028 static inline int16_t __timer0_div_to_reg(uint16_t div)
00029 {
00030         switch(div) {
00031 #if defined TIMER0_PRESCALER_REG_0 && TIMER0_PRESCALER_REG_0 >= 0
00032         case TIMER0_PRESCALER_REG_0:
00033                 return 0;
00034 #endif
00035 
00036 #if defined TIMER0_PRESCALER_REG_1 && TIMER0_PRESCALER_REG_1 >= 0
00037         case TIMER0_PRESCALER_REG_1:
00038                 return 1;
00039 #endif
00040 
00041 #if defined TIMER0_PRESCALER_REG_2 && TIMER0_PRESCALER_REG_2 >= 0
00042         case TIMER0_PRESCALER_REG_2:
00043                 return 2;
00044 #endif
00045 
00046 #if defined TIMER0_PRESCALER_REG_3 && TIMER0_PRESCALER_REG_3 >= 0
00047         case TIMER0_PRESCALER_REG_3:
00048                 return 3;
00049 #endif
00050 
00051 #if defined TIMER0_PRESCALER_REG_4 && TIMER0_PRESCALER_REG_4 >= 0
00052         case TIMER0_PRESCALER_REG_4:
00053                 return 4;
00054 #endif
00055 
00056 #if defined TIMER0_PRESCALER_REG_5 && TIMER0_PRESCALER_REG_5 >= 0
00057         case TIMER0_PRESCALER_REG_5:
00058                 return 5;
00059 #endif
00060 
00061 #if defined TIMER0_PRESCALER_REG_6 && TIMER0_PRESCALER_REG_6 >= 0
00062         case TIMER0_PRESCALER_REG_6:
00063                 return 6;
00064 #endif
00065 
00066 #if defined TIMER0_PRESCALER_REG_7 && TIMER0_PRESCALER_REG_7 >= 0
00067         case TIMER0_PRESCALER_REG_7:
00068                 return 7;
00069 #endif
00070 
00071 #if defined TIMER0_PRESCALER_REG_8 && TIMER0_PRESCALER_REG_8 >= 0
00072         case TIMER0_PRESCALER_REG_8:
00073                 return 8;
00074 #endif
00075 
00076 #if defined TIMER0_PRESCALER_REG_9 && TIMER0_PRESCALER_REG_9 >= 0
00077         case TIMER0_PRESCALER_REG_9:
00078                 return 9;
00079 #endif
00080 
00081 #if defined TIMER0_PRESCALER_REG_10 && TIMER0_PRESCALER_REG_10 >= 0
00082         case TIMER0_PRESCALER_REG_10:
00083                 return 10;
00084 #endif
00085 
00086 #if defined TIMER0_PRESCALER_REG_11 && TIMER0_PRESCALER_REG_11 >= 0
00087         case TIMER0_PRESCALER_REG_11:
00088                 return 11;
00089 #endif
00090 
00091 #if defined TIMER0_PRESCALER_REG_12 && TIMER0_PRESCALER_REG_12 >= 0
00092         case TIMER0_PRESCALER_REG_12:
00093                 return 12;
00094 #endif
00095 
00096 #if defined TIMER0_PRESCALER_REG_13 && TIMER0_PRESCALER_REG_13 >= 0
00097         case TIMER0_PRESCALER_REG_13:
00098                 return 13;
00099 #endif
00100 
00101 #if defined TIMER0_PRESCALER_REG_14 && TIMER0_PRESCALER_REG_14 >= 0
00102         case TIMER0_PRESCALER_REG_14:
00103                 return 14;
00104 #endif
00105 
00106 #if defined TIMER0_PRESCALER_REG_15 && TIMER0_PRESCALER_REG_15 >= 0
00107         case TIMER0_PRESCALER_REG_15:
00108                 return 15;
00109 #endif
00110         default:
00111                 return -1;
00112         }
00113 }
00114 
00115 /* return <0 on error, else return div value */ 
00116 /* This static inline function is very optimized if reg is
00117  * a constant */
00118 static inline int16_t __timer0_reg_to_div(uint8_t reg)
00119 {
00120         switch(reg) {
00121 #if defined TIMER0_PRESCALER_DIV_0
00122         case TIMER0_PRESCALER_DIV_0:
00123                 return 0;
00124 #endif
00125 
00126 #if defined TIMER0_PRESCALER_DIV_1
00127         case TIMER0_PRESCALER_DIV_1:
00128                 return 1;
00129 #endif
00130 
00131 #if defined TIMER0_PRESCALER_DIV_2
00132         case TIMER0_PRESCALER_DIV_2:
00133                 return 2;
00134 #endif
00135 
00136 #if defined TIMER0_PRESCALER_DIV_4
00137         case TIMER0_PRESCALER_DIV_4:
00138                 return 4;
00139 #endif
00140 
00141 #if defined TIMER0_PRESCALER_DIV_8
00142         case TIMER0_PRESCALER_DIV_8:
00143                 return 8;
00144 #endif
00145 
00146 #if defined TIMER0_PRESCALER_DIV_16
00147         case TIMER0_PRESCALER_DIV_16:
00148                 return 16;
00149 #endif
00150 
00151 #if defined TIMER0_PRESCALER_DIV_32
00152         case TIMER0_PRESCALER_DIV_32:
00153                 return 32;
00154 #endif
00155 
00156 #if defined TIMER0_PRESCALER_DIV_64
00157         case TIMER0_PRESCALER_DIV_64:
00158                 return 64;
00159 #endif
00160 
00161 #if defined TIMER0_PRESCALER_DIV_128
00162         case TIMER0_PRESCALER_DIV_128:
00163                 return 128;
00164 #endif
00165 
00166 #if defined TIMER0_PRESCALER_DIV_256
00167         case TIMER0_PRESCALER_DIV_256:
00168                 return 256;
00169 #endif
00170 
00171 #if defined TIMER0_PRESCALER_DIV_512
00172         case TIMER0_PRESCALER_DIV_512:
00173                 return 512;
00174 #endif
00175 
00176 #if defined TIMER0_PRESCALER_DIV_1024
00177         case TIMER0_PRESCALER_DIV_1024:
00178                 return 1024;
00179 #endif
00180 
00181 #if defined TIMER0_PRESCALER_DIV_2048
00182         case TIMER0_PRESCALER_DIV_2048:
00183                 return 2048;
00184 #endif
00185 
00186 #if defined TIMER0_PRESCALER_DIV_4096
00187         case TIMER0_PRESCALER_DIV_4096:
00188                 return 4096;
00189 #endif
00190 
00191 #if defined TIMER0_PRESCALER_DIV_8192
00192         case TIMER0_PRESCALER_DIV_8192:
00193                 return 8192;
00194 #endif
00195 
00196 #if defined TIMER0_PRESCALER_DIV_16384
00197         case TIMER0_PRESCALER_DIV_16384:
00198                 return 16384;
00199 #endif
00200 
00201         default:
00202                 return -1;
00203         }
00204 }
00205 
00206 
00207 /* return <0 on error, else return reg value */ 
00208 /* This static inline function is very optimized if div is
00209  * a constant */
00210 static inline int16_t __timer1_div_to_reg(uint16_t div)
00211 {
00212         switch(div) {
00213 #if defined TIMER1_PRESCALER_REG_0 && TIMER1_PRESCALER_REG_0 >= 0
00214         case TIMER1_PRESCALER_REG_0:
00215                 return 0;
00216 #endif
00217 
00218 #if defined TIMER1_PRESCALER_REG_1 && TIMER1_PRESCALER_REG_1 >= 0
00219         case TIMER1_PRESCALER_REG_1:
00220                 return 1;
00221 #endif
00222 
00223 #if defined TIMER1_PRESCALER_REG_2 && TIMER1_PRESCALER_REG_2 >= 0
00224         case TIMER1_PRESCALER_REG_2:
00225                 return 2;
00226 #endif
00227 
00228 #if defined TIMER1_PRESCALER_REG_3 && TIMER1_PRESCALER_REG_3 >= 0
00229         case TIMER1_PRESCALER_REG_3:
00230                 return 3;
00231 #endif
00232 
00233 #if defined TIMER1_PRESCALER_REG_4 && TIMER1_PRESCALER_REG_4 >= 0
00234         case TIMER1_PRESCALER_REG_4:
00235                 return 4;
00236 #endif
00237 
00238 #if defined TIMER1_PRESCALER_REG_5 && TIMER1_PRESCALER_REG_5 >= 0
00239         case TIMER1_PRESCALER_REG_5:
00240                 return 5;
00241 #endif
00242 
00243 #if defined TIMER1_PRESCALER_REG_6 && TIMER1_PRESCALER_REG_6 >= 0
00244         case TIMER1_PRESCALER_REG_6:
00245                 return 6;
00246 #endif
00247 
00248 #if defined TIMER1_PRESCALER_REG_7 && TIMER1_PRESCALER_REG_7 >= 0
00249         case TIMER1_PRESCALER_REG_7:
00250                 return 7;
00251 #endif
00252 
00253 #if defined TIMER1_PRESCALER_REG_8 && TIMER1_PRESCALER_REG_8 >= 0
00254         case TIMER1_PRESCALER_REG_8:
00255                 return 8;
00256 #endif
00257 
00258 #if defined TIMER1_PRESCALER_REG_9 && TIMER1_PRESCALER_REG_9 >= 0
00259         case TIMER1_PRESCALER_REG_9:
00260                 return 9;
00261 #endif
00262 
00263 #if defined TIMER1_PRESCALER_REG_10 && TIMER1_PRESCALER_REG_10 >= 0
00264         case TIMER1_PRESCALER_REG_10:
00265                 return 10;
00266 #endif
00267 
00268 #if defined TIMER1_PRESCALER_REG_11 && TIMER1_PRESCALER_REG_11 >= 0
00269         case TIMER1_PRESCALER_REG_11:
00270                 return 11;
00271 #endif
00272 
00273 #if defined TIMER1_PRESCALER_REG_12 && TIMER1_PRESCALER_REG_12 >= 0
00274         case TIMER1_PRESCALER_REG_12:
00275                 return 12;
00276 #endif
00277 
00278 #if defined TIMER1_PRESCALER_REG_13 && TIMER1_PRESCALER_REG_13 >= 0
00279         case TIMER1_PRESCALER_REG_13:
00280                 return 13;
00281 #endif
00282 
00283 #if defined TIMER1_PRESCALER_REG_14 && TIMER1_PRESCALER_REG_14 >= 0
00284         case TIMER1_PRESCALER_REG_14:
00285                 return 14;
00286 #endif
00287 
00288 #if defined TIMER1_PRESCALER_REG_15 && TIMER1_PRESCALER_REG_15 >= 0
00289         case TIMER1_PRESCALER_REG_15:
00290                 return 15;
00291 #endif
00292         default:
00293                 return -1;
00294         }
00295 }
00296 
00297 /* return <0 on error, else return div value */ 
00298 /* This static inline function is very optimized if reg is
00299  * a constant */
00300 static inline int16_t __timer1_reg_to_div(uint8_t reg)
00301 {
00302         switch(reg) {
00303 #if defined TIMER1_PRESCALER_DIV_0
00304         case TIMER1_PRESCALER_DIV_0:
00305                 return 0;
00306 #endif
00307 
00308 #if defined TIMER1_PRESCALER_DIV_1
00309         case TIMER1_PRESCALER_DIV_1:
00310                 return 1;
00311 #endif
00312 
00313 #if defined TIMER1_PRESCALER_DIV_2
00314         case TIMER1_PRESCALER_DIV_2:
00315                 return 2;
00316 #endif
00317 
00318 #if defined TIMER1_PRESCALER_DIV_4
00319         case TIMER1_PRESCALER_DIV_4:
00320                 return 4;
00321 #endif
00322 
00323 #if defined TIMER1_PRESCALER_DIV_8
00324         case TIMER1_PRESCALER_DIV_8:
00325                 return 8;
00326 #endif
00327 
00328 #if defined TIMER1_PRESCALER_DIV_16
00329         case TIMER1_PRESCALER_DIV_16:
00330                 return 16;
00331 #endif
00332 
00333 #if defined TIMER1_PRESCALER_DIV_32
00334         case TIMER1_PRESCALER_DIV_32:
00335                 return 32;
00336 #endif
00337 
00338 #if defined TIMER1_PRESCALER_DIV_64
00339         case TIMER1_PRESCALER_DIV_64:
00340                 return 64;
00341 #endif
00342 
00343 #if defined TIMER1_PRESCALER_DIV_128
00344         case TIMER1_PRESCALER_DIV_128:
00345                 return 128;
00346 #endif
00347 
00348 #if defined TIMER1_PRESCALER_DIV_256
00349         case TIMER1_PRESCALER_DIV_256:
00350                 return 256;
00351 #endif
00352 
00353 #if defined TIMER1_PRESCALER_DIV_512
00354         case TIMER1_PRESCALER_DIV_512:
00355                 return 512;
00356 #endif
00357 
00358 #if defined TIMER1_PRESCALER_DIV_1024
00359         case TIMER1_PRESCALER_DIV_1024:
00360                 return 1024;
00361 #endif
00362 
00363 #if defined TIMER1_PRESCALER_DIV_2048
00364         case TIMER1_PRESCALER_DIV_2048:
00365                 return 2048;
00366 #endif
00367 
00368 #if defined TIMER1_PRESCALER_DIV_4096
00369         case TIMER1_PRESCALER_DIV_4096:
00370                 return 4096;
00371 #endif
00372 
00373 #if defined TIMER1_PRESCALER_DIV_8192
00374         case TIMER1_PRESCALER_DIV_8192:
00375                 return 8192;
00376 #endif
00377 
00378 #if defined TIMER1_PRESCALER_DIV_16384
00379         case TIMER1_PRESCALER_DIV_16384:
00380                 return 16384;
00381 #endif
00382 
00383         default:
00384                 return -1;
00385         }
00386 }
00387 
00388 
00389 
00390 /* return <0 on error, else return reg value */ 
00391 /* This static inline function is very optimized if div is
00392  * a constant */
00393 static inline int16_t __timer2_div_to_reg(uint16_t div)
00394 {
00395         switch(div) {
00396 #if defined TIMER2_PRESCALER_REG_0 && TIMER2_PRESCALER_REG_0 >= 0
00397         case TIMER2_PRESCALER_REG_0:
00398                 return 0;
00399 #endif
00400 
00401 #if defined TIMER2_PRESCALER_REG_1 && TIMER2_PRESCALER_REG_1 >= 0
00402         case TIMER2_PRESCALER_REG_1:
00403                 return 1;
00404 #endif
00405 
00406 #if defined TIMER2_PRESCALER_REG_2 && TIMER2_PRESCALER_REG_2 >= 0
00407         case TIMER2_PRESCALER_REG_2:
00408                 return 2;
00409 #endif
00410 
00411 #if defined TIMER2_PRESCALER_REG_3 && TIMER2_PRESCALER_REG_3 >= 0
00412         case TIMER2_PRESCALER_REG_3:
00413                 return 3;
00414 #endif
00415 
00416 #if defined TIMER2_PRESCALER_REG_4 && TIMER2_PRESCALER_REG_4 >= 0
00417         case TIMER2_PRESCALER_REG_4:
00418                 return 4;
00419 #endif
00420 
00421 #if defined TIMER2_PRESCALER_REG_5 && TIMER2_PRESCALER_REG_5 >= 0
00422         case TIMER2_PRESCALER_REG_5:
00423                 return 5;
00424 #endif
00425 
00426 #if defined TIMER2_PRESCALER_REG_6 && TIMER2_PRESCALER_REG_6 >= 0
00427         case TIMER2_PRESCALER_REG_6:
00428                 return 6;
00429 #endif
00430 
00431 #if defined TIMER2_PRESCALER_REG_7 && TIMER2_PRESCALER_REG_7 >= 0
00432         case TIMER2_PRESCALER_REG_7:
00433                 return 7;
00434 #endif
00435 
00436 #if defined TIMER2_PRESCALER_REG_8 && TIMER2_PRESCALER_REG_8 >= 0
00437         case TIMER2_PRESCALER_REG_8:
00438                 return 8;
00439 #endif
00440 
00441 #if defined TIMER2_PRESCALER_REG_9 && TIMER2_PRESCALER_REG_9 >= 0
00442         case TIMER2_PRESCALER_REG_9:
00443                 return 9;
00444 #endif
00445 
00446 #if defined TIMER2_PRESCALER_REG_10 && TIMER2_PRESCALER_REG_10 >= 0
00447         case TIMER2_PRESCALER_REG_10:
00448                 return 10;
00449 #endif
00450 
00451 #if defined TIMER2_PRESCALER_REG_11 && TIMER2_PRESCALER_REG_11 >= 0
00452         case TIMER2_PRESCALER_REG_11:
00453                 return 11;
00454 #endif
00455 
00456 #if defined TIMER2_PRESCALER_REG_12 && TIMER2_PRESCALER_REG_12 >= 0
00457         case TIMER2_PRESCALER_REG_12:
00458                 return 12;
00459 #endif
00460 
00461 #if defined TIMER2_PRESCALER_REG_13 && TIMER2_PRESCALER_REG_13 >= 0
00462         case TIMER2_PRESCALER_REG_13:
00463                 return 13;
00464 #endif
00465 
00466 #if defined TIMER2_PRESCALER_REG_14 && TIMER2_PRESCALER_REG_14 >= 0
00467         case TIMER2_PRESCALER_REG_14:
00468                 return 14;
00469 #endif
00470 
00471 #if defined TIMER2_PRESCALER_REG_15 && TIMER2_PRESCALER_REG_15 >= 0
00472         case TIMER2_PRESCALER_REG_15:
00473                 return 15;
00474 #endif
00475         default:
00476                 return -1;
00477         }
00478 }
00479 
00480 /* return <0 on error, else return div value */ 
00481 /* This static inline function is very optimized if reg is
00482  * a constant */
00483 static inline int16_t __timer2_reg_to_div(uint8_t reg)
00484 {
00485         switch(reg) {
00486 #if defined TIMER2_PRESCALER_DIV_0
00487         case TIMER2_PRESCALER_DIV_0:
00488                 return 0;
00489 #endif
00490 
00491 #if defined TIMER2_PRESCALER_DIV_1
00492         case TIMER2_PRESCALER_DIV_1:
00493                 return 1;
00494 #endif
00495 
00496 #if defined TIMER2_PRESCALER_DIV_2
00497         case TIMER2_PRESCALER_DIV_2:
00498                 return 2;
00499 #endif
00500 
00501 #if defined TIMER2_PRESCALER_DIV_4
00502         case TIMER2_PRESCALER_DIV_4:
00503                 return 4;
00504 #endif
00505 
00506 #if defined TIMER2_PRESCALER_DIV_8
00507         case TIMER2_PRESCALER_DIV_8:
00508                 return 8;
00509 #endif
00510 
00511 #if defined TIMER2_PRESCALER_DIV_16
00512         case TIMER2_PRESCALER_DIV_16:
00513                 return 16;
00514 #endif
00515 
00516 #if defined TIMER2_PRESCALER_DIV_32
00517         case TIMER2_PRESCALER_DIV_32:
00518                 return 32;
00519 #endif
00520 
00521 #if defined TIMER2_PRESCALER_DIV_64
00522         case TIMER2_PRESCALER_DIV_64:
00523                 return 64;
00524 #endif
00525 
00526 #if defined TIMER2_PRESCALER_DIV_128
00527         case TIMER2_PRESCALER_DIV_128:
00528                 return 128;
00529 #endif
00530 
00531 #if defined TIMER2_PRESCALER_DIV_256
00532         case TIMER2_PRESCALER_DIV_256:
00533                 return 256;
00534 #endif
00535 
00536 #if defined TIMER2_PRESCALER_DIV_512
00537         case TIMER2_PRESCALER_DIV_512:
00538                 return 512;
00539 #endif
00540 
00541 #if defined TIMER2_PRESCALER_DIV_1024
00542         case TIMER2_PRESCALER_DIV_1024:
00543                 return 1024;
00544 #endif
00545 
00546 #if defined TIMER2_PRESCALER_DIV_2048
00547         case TIMER2_PRESCALER_DIV_2048:
00548                 return 2048;
00549 #endif
00550 
00551 #if defined TIMER2_PRESCALER_DIV_4096
00552         case TIMER2_PRESCALER_DIV_4096:
00553                 return 4096;
00554 #endif
00555 
00556 #if defined TIMER2_PRESCALER_DIV_8192
00557         case TIMER2_PRESCALER_DIV_8192:
00558                 return 8192;
00559 #endif
00560 
00561 #if defined TIMER2_PRESCALER_DIV_16384
00562         case TIMER2_PRESCALER_DIV_16384:
00563                 return 16384;
00564 #endif
00565 
00566         default:
00567                 return -1;
00568         }
00569 }
00570 
00571 
00572 
00573 /* return <0 on error, else return reg value */ 
00574 /* This static inline function is very optimized if div is
00575  * a constant */
00576 static inline int16_t __timer3_div_to_reg(uint16_t div)
00577 {
00578         switch(div) {
00579 #if defined TIMER3_PRESCALER_REG_0 && TIMER3_PRESCALER_REG_0 >= 0
00580         case TIMER3_PRESCALER_REG_0:
00581                 return 0;
00582 #endif
00583 
00584 #if defined TIMER3_PRESCALER_REG_1 && TIMER3_PRESCALER_REG_1 >= 0
00585         case TIMER3_PRESCALER_REG_1:
00586                 return 1;
00587 #endif
00588 
00589 #if defined TIMER3_PRESCALER_REG_2 && TIMER3_PRESCALER_REG_2 >= 0
00590         case TIMER3_PRESCALER_REG_2:
00591                 return 2;
00592 #endif
00593 
00594 #if defined TIMER3_PRESCALER_REG_3 && TIMER3_PRESCALER_REG_3 >= 0
00595         case TIMER3_PRESCALER_REG_3:
00596                 return 3;
00597 #endif
00598 
00599 #if defined TIMER3_PRESCALER_REG_4 && TIMER3_PRESCALER_REG_4 >= 0
00600         case TIMER3_PRESCALER_REG_4:
00601                 return 4;
00602 #endif
00603 
00604 #if defined TIMER3_PRESCALER_REG_5 && TIMER3_PRESCALER_REG_5 >= 0
00605         case TIMER3_PRESCALER_REG_5:
00606                 return 5;
00607 #endif
00608 
00609 #if defined TIMER3_PRESCALER_REG_6 && TIMER3_PRESCALER_REG_6 >= 0
00610         case TIMER3_PRESCALER_REG_6:
00611                 return 6;
00612 #endif
00613 
00614 #if defined TIMER3_PRESCALER_REG_7 && TIMER3_PRESCALER_REG_7 >= 0
00615         case TIMER3_PRESCALER_REG_7:
00616                 return 7;
00617 #endif
00618 
00619 #if defined TIMER3_PRESCALER_REG_8 && TIMER3_PRESCALER_REG_8 >= 0
00620         case TIMER3_PRESCALER_REG_8:
00621                 return 8;
00622 #endif
00623 
00624 #if defined TIMER3_PRESCALER_REG_9 && TIMER3_PRESCALER_REG_9 >= 0
00625         case TIMER3_PRESCALER_REG_9:
00626                 return 9;
00627 #endif
00628 
00629 #if defined TIMER3_PRESCALER_REG_10 && TIMER3_PRESCALER_REG_10 >= 0
00630         case TIMER3_PRESCALER_REG_10:
00631                 return 10;
00632 #endif
00633 
00634 #if defined TIMER3_PRESCALER_REG_11 && TIMER3_PRESCALER_REG_11 >= 0
00635         case TIMER3_PRESCALER_REG_11:
00636                 return 11;
00637 #endif
00638 
00639 #if defined TIMER3_PRESCALER_REG_12 && TIMER3_PRESCALER_REG_12 >= 0
00640         case TIMER3_PRESCALER_REG_12:
00641                 return 12;
00642 #endif
00643 
00644 #if defined TIMER3_PRESCALER_REG_13 && TIMER3_PRESCALER_REG_13 >= 0
00645         case TIMER3_PRESCALER_REG_13:
00646                 return 13;
00647 #endif
00648 #if defined TIMER3_PRESCALER_REG_14 && TIMER3_PRESCALER_REG_14 >= 0
00649         case TIMER3_PRESCALER_REG_14:
00650                 return 14;
00651 #endif
00652 
00653 #if defined TIMER3_PRESCALER_REG_15 && TIMER3_PRESCALER_REG_15 >= 0
00654         case TIMER3_PRESCALER_REG_15:
00655                 return 15;
00656 #endif
00657         default:
00658                 return -1;
00659         }
00660 }
00661 
00662 /* return <0 on error, else return div value */ 
00663 /* This static inline function is very optimized if reg is
00664  * a constant */
00665 static inline int16_t __timer3_reg_to_div(uint8_t reg)
00666 {
00667         switch(reg) {
00668 #if defined TIMER3_PRESCALER_DIV_0
00669         case TIMER3_PRESCALER_DIV_0:
00670                 return 0;
00671 #endif
00672 
00673 #if defined TIMER3_PRESCALER_DIV_1
00674         case TIMER3_PRESCALER_DIV_1:
00675                 return 1;
00676 #endif
00677 
00678 #if defined TIMER3_PRESCALER_DIV_2
00679         case TIMER3_PRESCALER_DIV_2:
00680                 return 2;
00681 #endif
00682 
00683 #if defined TIMER3_PRESCALER_DIV_4
00684         case TIMER3_PRESCALER_DIV_4:
00685                 return 4;
00686 #endif
00687 
00688 #if defined TIMER3_PRESCALER_DIV_8
00689         case TIMER3_PRESCALER_DIV_8:
00690                 return 8;
00691 #endif
00692 
00693 #if defined TIMER3_PRESCALER_DIV_16
00694         case TIMER3_PRESCALER_DIV_16:
00695                 return 16;
00696 #endif
00697 
00698 #if defined TIMER3_PRESCALER_DIV_32
00699         case TIMER3_PRESCALER_DIV_32:
00700                 return 32;
00701 #endif
00702 
00703 #if defined TIMER3_PRESCALER_DIV_64
00704         case TIMER3_PRESCALER_DIV_64:
00705                 return 64;
00706 #endif
00707 
00708 #if defined TIMER3_PRESCALER_DIV_128
00709         case TIMER3_PRESCALER_DIV_128:
00710                 return 128;
00711 #endif
00712 
00713 #if defined TIMER3_PRESCALER_DIV_256
00714         case TIMER3_PRESCALER_DIV_256:
00715                 return 256;
00716 #endif
00717 
00718 #if defined TIMER3_PRESCALER_DIV_512
00719         case TIMER3_PRESCALER_DIV_512:
00720                 return 512;
00721 #endif
00722 
00723 #if defined TIMER3_PRESCALER_DIV_1024
00724         case TIMER3_PRESCALER_DIV_1024:
00725                 return 1024;
00726 #endif
00727 
00728 #if defined TIMER3_PRESCALER_DIV_2048
00729         case TIMER3_PRESCALER_DIV_2048:
00730                 return 2048;
00731 #endif
00732 
00733 #if defined TIMER3_PRESCALER_DIV_4096
00734         case TIMER3_PRESCALER_DIV_4096:
00735                 return 4096;
00736 #endif
00737 
00738 #if defined TIMER3_PRESCALER_DIV_8192
00739         case TIMER3_PRESCALER_DIV_8192:
00740                 return 8192;
00741 #endif
00742 
00743 #if defined TIMER3_PRESCALER_DIV_16384
00744         case TIMER3_PRESCALER_DIV_16384:
00745                 return 16384;
00746 #endif
00747 
00748         default:
00749                 return -1;
00750         }
00751 }
00752 
00753 /* return <0 on error, else return reg value */ 
00754 /* This static inline function is very optimized if div is
00755  * a constant */
00756 static inline int16_t __timer4_div_to_reg(uint16_t div)
00757 {
00758         switch(div) {
00759 #if defined TIMER4_PRESCALER_REG_0 && TIMER4_PRESCALER_REG_0 >= 0
00760         case TIMER4_PRESCALER_REG_0:
00761                 return 0;
00762 #endif
00763 
00764 #if defined TIMER4_PRESCALER_REG_1 && TIMER4_PRESCALER_REG_1 >= 0
00765         case TIMER4_PRESCALER_REG_1:
00766                 return 1;
00767 #endif
00768 
00769 #if defined TIMER4_PRESCALER_REG_2 && TIMER4_PRESCALER_REG_2 >= 0
00770         case TIMER4_PRESCALER_REG_2:
00771                 return 2;
00772 #endif
00773 
00774 #if defined TIMER4_PRESCALER_REG_3 && TIMER4_PRESCALER_REG_3 >= 0
00775         case TIMER4_PRESCALER_REG_3:
00776                 return 3;
00777 #endif
00778 
00779 #if defined TIMER4_PRESCALER_REG_4 && TIMER4_PRESCALER_REG_4 >= 0
00780         case TIMER4_PRESCALER_REG_4:
00781                 return 4;
00782 #endif
00783 
00784 #if defined TIMER4_PRESCALER_REG_5 && TIMER4_PRESCALER_REG_5 >= 0
00785         case TIMER4_PRESCALER_REG_5:
00786                 return 5;
00787 #endif
00788 
00789 #if defined TIMER4_PRESCALER_REG_6 && TIMER4_PRESCALER_REG_6 >= 0
00790         case TIMER4_PRESCALER_REG_6:
00791                 return 6;
00792 #endif
00793 
00794 #if defined TIMER4_PRESCALER_REG_7 && TIMER4_PRESCALER_REG_7 >= 0
00795         case TIMER4_PRESCALER_REG_7:
00796                 return 7;
00797 #endif
00798 
00799 #if defined TIMER4_PRESCALER_REG_8 && TIMER4_PRESCALER_REG_8 >= 0
00800         case TIMER4_PRESCALER_REG_8:
00801                 return 8;
00802 #endif
00803 
00804 #if defined TIMER4_PRESCALER_REG_9 && TIMER4_PRESCALER_REG_9 >= 0
00805         case TIMER4_PRESCALER_REG_9:
00806                 return 9;
00807 #endif
00808 
00809 #if defined TIMER4_PRESCALER_REG_10 && TIMER4_PRESCALER_REG_10 >= 0
00810         case TIMER4_PRESCALER_REG_10:
00811                 return 10;
00812 #endif
00813 
00814 #if defined TIMER4_PRESCALER_REG_11 && TIMER4_PRESCALER_REG_11 >= 0
00815         case TIMER4_PRESCALER_REG_11:
00816                 return 11;
00817 #endif
00818 
00819 #if defined TIMER4_PRESCALER_REG_12 && TIMER4_PRESCALER_REG_12 >= 0
00820         case TIMER4_PRESCALER_REG_12:
00821                 return 12;
00822 #endif
00823 
00824 #if defined TIMER4_PRESCALER_REG_13 && TIMER4_PRESCALER_REG_13 >= 0
00825         case TIMER4_PRESCALER_REG_13:
00826                 return 13;
00827 #endif
00828 #if defined TIMER4_PRESCALER_REG_14 && TIMER4_PRESCALER_REG_14 >= 0
00829         case TIMER4_PRESCALER_REG_14:
00830                 return 14;
00831 #endif
00832 
00833 #if defined TIMER4_PRESCALER_REG_15 && TIMER4_PRESCALER_REG_15 >= 0
00834         case TIMER4_PRESCALER_REG_15:
00835                 return 15;
00836 #endif
00837         default:
00838                 return -1;
00839         }
00840 }
00841 
00842 /* return <0 on error, else return div value */ 
00843 /* This static inline function is very optimized if reg is
00844  * a constant */
00845 static inline int16_t __timer4_reg_to_div(uint8_t reg)
00846 {
00847         switch(reg) {
00848 #if defined TIMER4_PRESCALER_DIV_0
00849         case TIMER4_PRESCALER_DIV_0:
00850                 return 0;
00851 #endif
00852 
00853 #if defined TIMER4_PRESCALER_DIV_1
00854         case TIMER4_PRESCALER_DIV_1:
00855                 return 1;
00856 #endif
00857 
00858 #if defined TIMER4_PRESCALER_DIV_2
00859         case TIMER4_PRESCALER_DIV_2:
00860                 return 2;
00861 #endif
00862 
00863 #if defined TIMER4_PRESCALER_DIV_4
00864         case TIMER4_PRESCALER_DIV_4:
00865                 return 4;
00866 #endif
00867 
00868 #if defined TIMER4_PRESCALER_DIV_8
00869         case TIMER4_PRESCALER_DIV_8:
00870                 return 8;
00871 #endif
00872 
00873 #if defined TIMER4_PRESCALER_DIV_16
00874         case TIMER4_PRESCALER_DIV_16:
00875                 return 16;
00876 #endif
00877 
00878 #if defined TIMER4_PRESCALER_DIV_32
00879         case TIMER4_PRESCALER_DIV_32:
00880                 return 32;
00881 #endif
00882 
00883 #if defined TIMER4_PRESCALER_DIV_64
00884         case TIMER4_PRESCALER_DIV_64:
00885                 return 64;
00886 #endif
00887 
00888 #if defined TIMER4_PRESCALER_DIV_128
00889         case TIMER4_PRESCALER_DIV_128:
00890                 return 128;
00891 #endif
00892 
00893 #if defined TIMER4_PRESCALER_DIV_256
00894         case TIMER4_PRESCALER_DIV_256:
00895                 return 256;
00896 #endif
00897 
00898 #if defined TIMER4_PRESCALER_DIV_512
00899         case TIMER4_PRESCALER_DIV_512:
00900                 return 512;
00901 #endif
00902 
00903 #if defined TIMER4_PRESCALER_DIV_1024
00904         case TIMER4_PRESCALER_DIV_1024:
00905                 return 1024;
00906 #endif
00907 
00908 #if defined TIMER4_PRESCALER_DIV_2048
00909         case TIMER4_PRESCALER_DIV_2048:
00910                 return 2048;
00911 #endif
00912 
00913 #if defined TIMER4_PRESCALER_DIV_4096
00914         case TIMER4_PRESCALER_DIV_4096:
00915                 return 4096;
00916 #endif
00917 
00918 #if defined TIMER4_PRESCALER_DIV_8192
00919         case TIMER4_PRESCALER_DIV_8192:
00920                 return 8192;
00921 #endif
00922 
00923 #if defined TIMER4_PRESCALER_DIV_16384
00924         case TIMER4_PRESCALER_DIV_16384:
00925                 return 16384;
00926 #endif
00927 
00928         default:
00929                 return -1;
00930         }
00931 }
00932 
00933 /* return <0 on error, else return reg value */ 
00934 /* This static inline function is very optimized if div is
00935  * a constant */
00936 static inline int16_t __timer5_div_to_reg(uint16_t div)
00937 {
00938         switch(div) {
00939 #if defined TIMER5_PRESCALER_REG_0 && TIMER5_PRESCALER_REG_0 >= 0
00940         case TIMER5_PRESCALER_REG_0:
00941                 return 0;
00942 #endif
00943 
00944 #if defined TIMER5_PRESCALER_REG_1 && TIMER5_PRESCALER_REG_1 >= 0
00945         case TIMER5_PRESCALER_REG_1:
00946                 return 1;
00947 #endif
00948 
00949 #if defined TIMER5_PRESCALER_REG_2 && TIMER5_PRESCALER_REG_2 >= 0
00950         case TIMER5_PRESCALER_REG_2:
00951                 return 2;
00952 #endif
00953 
00954 #if defined TIMER5_PRESCALER_REG_3 && TIMER5_PRESCALER_REG_3 >= 0
00955         case TIMER5_PRESCALER_REG_3:
00956                 return 3;
00957 #endif
00958 
00959 #if defined TIMER5_PRESCALER_REG_4 && TIMER5_PRESCALER_REG_4 >= 0
00960         case TIMER5_PRESCALER_REG_4:
00961                 return 4;
00962 #endif
00963 
00964 #if defined TIMER5_PRESCALER_REG_5 && TIMER5_PRESCALER_REG_5 >= 0
00965         case TIMER5_PRESCALER_REG_5:
00966                 return 5;
00967 #endif
00968 
00969 #if defined TIMER5_PRESCALER_REG_6 && TIMER5_PRESCALER_REG_6 >= 0
00970         case TIMER5_PRESCALER_REG_6:
00971                 return 6;
00972 #endif
00973 
00974 #if defined TIMER5_PRESCALER_REG_7 && TIMER5_PRESCALER_REG_7 >= 0
00975         case TIMER5_PRESCALER_REG_7:
00976                 return 7;
00977 #endif
00978 
00979 #if defined TIMER5_PRESCALER_REG_8 && TIMER5_PRESCALER_REG_8 >= 0
00980         case TIMER5_PRESCALER_REG_8:
00981                 return 8;
00982 #endif
00983 
00984 #if defined TIMER5_PRESCALER_REG_9 && TIMER5_PRESCALER_REG_9 >= 0
00985         case TIMER5_PRESCALER_REG_9:
00986                 return 9;
00987 #endif
00988 
00989 #if defined TIMER5_PRESCALER_REG_10 && TIMER5_PRESCALER_REG_10 >= 0
00990         case TIMER5_PRESCALER_REG_10:
00991                 return 10;
00992 #endif
00993 
00994 #if defined TIMER5_PRESCALER_REG_11 && TIMER5_PRESCALER_REG_11 >= 0
00995         case TIMER5_PRESCALER_REG_11:
00996                 return 11;
00997 #endif
00998 
00999 #if defined TIMER5_PRESCALER_REG_12 && TIMER5_PRESCALER_REG_12 >= 0
01000         case TIMER5_PRESCALER_REG_12:
01001                 return 12;
01002 #endif
01003 
01004 #if defined TIMER5_PRESCALER_REG_13 && TIMER5_PRESCALER_REG_13 >= 0
01005         case TIMER5_PRESCALER_REG_13:
01006                 return 13;
01007 #endif
01008 #if defined TIMER5_PRESCALER_REG_14 && TIMER5_PRESCALER_REG_14 >= 0
01009         case TIMER5_PRESCALER_REG_14:
01010                 return 14;
01011 #endif
01012 
01013 #if defined TIMER5_PRESCALER_REG_15 && TIMER5_PRESCALER_REG_15 >= 0
01014         case TIMER5_PRESCALER_REG_15:
01015                 return 15;
01016 #endif
01017         default:
01018                 return -1;
01019         }
01020 }
01021 
01022 /* return <0 on error, else return div value */ 
01023 /* This static inline function is very optimized if reg is
01024  * a constant */
01025 static inline int16_t __timer5_reg_to_div(uint8_t reg)
01026 {
01027         switch(reg) {
01028 #if defined TIMER5_PRESCALER_DIV_0
01029         case TIMER5_PRESCALER_DIV_0:
01030                 return 0;
01031 #endif
01032 
01033 #if defined TIMER5_PRESCALER_DIV_1
01034         case TIMER5_PRESCALER_DIV_1:
01035                 return 1;
01036 #endif
01037 
01038 #if defined TIMER5_PRESCALER_DIV_2
01039         case TIMER5_PRESCALER_DIV_2:
01040                 return 2;
01041 #endif
01042 
01043 #if defined TIMER5_PRESCALER_DIV_4
01044         case TIMER5_PRESCALER_DIV_4:
01045                 return 4;
01046 #endif
01047 
01048 #if defined TIMER5_PRESCALER_DIV_8
01049         case TIMER5_PRESCALER_DIV_8:
01050                 return 8;
01051 #endif
01052 
01053 #if defined TIMER5_PRESCALER_DIV_16
01054         case TIMER5_PRESCALER_DIV_16:
01055                 return 16;
01056 #endif
01057 
01058 #if defined TIMER5_PRESCALER_DIV_32
01059         case TIMER5_PRESCALER_DIV_32:
01060                 return 32;
01061 #endif
01062 
01063 #if defined TIMER5_PRESCALER_DIV_64
01064         case TIMER5_PRESCALER_DIV_64:
01065                 return 64;
01066 #endif
01067 
01068 #if defined TIMER5_PRESCALER_DIV_128
01069         case TIMER5_PRESCALER_DIV_128:
01070                 return 128;
01071 #endif
01072 
01073 #if defined TIMER5_PRESCALER_DIV_256
01074         case TIMER5_PRESCALER_DIV_256:
01075                 return 256;
01076 #endif
01077 
01078 #if defined TIMER5_PRESCALER_DIV_512
01079         case TIMER5_PRESCALER_DIV_512:
01080                 return 512;
01081 #endif
01082 
01083 #if defined TIMER5_PRESCALER_DIV_1024
01084         case TIMER5_PRESCALER_DIV_1024:
01085                 return 1024;
01086 #endif
01087 
01088 #if defined TIMER5_PRESCALER_DIV_2048
01089         case TIMER5_PRESCALER_DIV_2048:
01090                 return 2048;
01091 #endif
01092 
01093 #if defined TIMER5_PRESCALER_DIV_4096
01094         case TIMER5_PRESCALER_DIV_4096:
01095                 return 4096;
01096 #endif
01097 
01098 #if defined TIMER5_PRESCALER_DIV_8192
01099         case TIMER5_PRESCALER_DIV_8192:
01100                 return 8192;
01101 #endif
01102 
01103 #if defined TIMER5_PRESCALER_DIV_16384
01104         case TIMER5_PRESCALER_DIV_16384:
01105                 return 16384;
01106 #endif
01107 
01108         default:
01109                 return -1;
01110         }
01111 }
01112 
01113 #endif
aversive_10-03-12/modules/hardware/timer/timer_prescaler.h
