Data Fields | |
in | CLK std_logic; |
out | sortie unsigned(7 downto 0); |
in | SEL unsigned(1 downto 0); |
out | TX_bus std_logic; |
in | RX_bus std_logic; |
in | TX_avr std_logic; |
out | RX_avr std_logic; |
in | AB0 unsigned(1 downto 0); |
in | AB1 unsigned(1 downto 0); |
:string; | pin_assign |
OF CLK:SIGNAL IS"7"; | pin_assign |
OF sortie:SIGNAL IS"11 12 9 8 6 5 4 3 "; | pin_assign |
OF AB0:SIGNAL IS"27 26"; | pin_assign |
OF AB1:SIGNAL IS"25 29"; | pin_assign |
OF RX_bus:SIGNAL IS"19"; | pin_assign |
OF TX_bus:SIGNAL IS"22"; | pin_assign |
OF RX_avr:SIGNAL IS"14"; | pin_assign |
OF TX_avr:SIGNAL IS"13"; | pin_assign |
OF SEL:SIGNAL IS"1 44"; | pin_assign |
library | IEEE |
package | STD_LOGIC_1164 |
package | numeric_std |
Data Structures | |
class | Behavioral |
Definition at line 10 of file test1.vhd.
: string; carte1::pin_assign [explicit, mutable] |
OF CLK : SIGNAL IS "7"; carte1::pin_assign [explicit, mutable] |
OF sortie : SIGNAL IS "11 12 9 8 6 5 4 3 "; carte1::pin_assign [explicit, mutable] |
OF AB0 : SIGNAL IS "27 26"; carte1::pin_assign [explicit, mutable] |
OF AB1 : SIGNAL IS "25 29"; carte1::pin_assign [explicit, mutable] |
OF RX_bus : SIGNAL IS "19"; carte1::pin_assign [explicit, mutable] |
OF TX_bus : SIGNAL IS "22"; carte1::pin_assign [explicit, mutable] |
OF RX_avr : SIGNAL IS "14"; carte1::pin_assign [explicit, mutable] |
OF TX_avr : SIGNAL IS "13"; carte1::pin_assign [explicit, mutable] |
OF SEL : SIGNAL IS "1 44"; carte1::pin_assign [explicit, mutable] |
library carte1::IEEE [inline] |
package carte1::STD_LOGIC_1164 [inline, explicit, mutable, set] |
package carte1::numeric_std [inline, explicit, mutable, set] |