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Defines | |
| #define | TIMER0_PRESCALER_DIV_0 0 |
| #define | TIMER0_PRESCALER_DIV_1 1 |
| #define | TIMER0_PRESCALER_DIV_8 2 |
| #define | TIMER0_PRESCALER_DIV_64 3 |
| #define | TIMER0_PRESCALER_DIV_256 4 |
| #define | TIMER0_PRESCALER_DIV_1024 5 |
| #define | TIMER0_PRESCALER_DIV_FALL 6 |
| #define | TIMER0_PRESCALER_DIV_RISE 7 |
| #define | TIMER0_PRESCALER_REG_0 0 |
| #define | TIMER0_PRESCALER_REG_1 1 |
| #define | TIMER0_PRESCALER_REG_2 8 |
| #define | TIMER0_PRESCALER_REG_3 64 |
| #define | TIMER0_PRESCALER_REG_4 256 |
| #define | TIMER0_PRESCALER_REG_5 1024 |
| #define | TIMER0_PRESCALER_REG_6 -1 |
| #define | TIMER0_PRESCALER_REG_7 -2 |
| #define | TIMER1_PRESCALER_DIV_0 0 |
| #define | TIMER1_PRESCALER_DIV_1 1 |
| #define | TIMER1_PRESCALER_DIV_8 2 |
| #define | TIMER1_PRESCALER_DIV_64 3 |
| #define | TIMER1_PRESCALER_DIV_256 4 |
| #define | TIMER1_PRESCALER_DIV_1024 5 |
| #define | TIMER1_PRESCALER_DIV_FALL 6 |
| #define | TIMER1_PRESCALER_DIV_RISE 7 |
| #define | TIMER1_PRESCALER_REG_0 0 |
| #define | TIMER1_PRESCALER_REG_1 1 |
| #define | TIMER1_PRESCALER_REG_2 8 |
| #define | TIMER1_PRESCALER_REG_3 64 |
| #define | TIMER1_PRESCALER_REG_4 256 |
| #define | TIMER1_PRESCALER_REG_5 1024 |
| #define | TIMER1_PRESCALER_REG_6 -1 |
| #define | TIMER1_PRESCALER_REG_7 -2 |
| #define | TIMER2_PRESCALER_DIV_0 0 |
| #define | TIMER2_PRESCALER_DIV_1 1 |
| #define | TIMER2_PRESCALER_DIV_8 2 |
| #define | TIMER2_PRESCALER_DIV_32 3 |
| #define | TIMER2_PRESCALER_DIV_64 4 |
| #define | TIMER2_PRESCALER_DIV_128 5 |
| #define | TIMER2_PRESCALER_DIV_256 6 |
| #define | TIMER2_PRESCALER_DIV_1024 7 |
| #define | TIMER2_PRESCALER_REG_0 0 |
| #define | TIMER2_PRESCALER_REG_1 1 |
| #define | TIMER2_PRESCALER_REG_2 8 |
| #define | TIMER2_PRESCALER_REG_3 32 |
| #define | TIMER2_PRESCALER_REG_4 64 |
| #define | TIMER2_PRESCALER_REG_5 128 |
| #define | TIMER2_PRESCALER_REG_6 256 |
| #define | TIMER2_PRESCALER_REG_7 1024 |
| #define | TIMER3_PRESCALER_DIV_0 0 |
| #define | TIMER3_PRESCALER_DIV_1 1 |
| #define | TIMER3_PRESCALER_DIV_8 2 |
| #define | TIMER3_PRESCALER_DIV_64 3 |
| #define | TIMER3_PRESCALER_DIV_256 4 |
| #define | TIMER3_PRESCALER_DIV_1024 5 |
| #define | TIMER3_PRESCALER_DIV_FALL 6 |
| #define | TIMER3_PRESCALER_DIV_RISE 7 |
| #define | TIMER3_PRESCALER_REG_0 0 |
| #define | TIMER3_PRESCALER_REG_1 1 |
| #define | TIMER3_PRESCALER_REG_2 8 |
| #define | TIMER3_PRESCALER_REG_3 64 |
| #define | TIMER3_PRESCALER_REG_4 256 |
| #define | TIMER3_PRESCALER_REG_5 1024 |
| #define | TIMER3_PRESCALER_REG_6 -1 |
| #define | TIMER3_PRESCALER_REG_7 -2 |
| #define | TIMER0_AVAILABLE |
| #define | TIMER0A_AVAILABLE |
| #define | TIMER0B_AVAILABLE |
| #define | TIMER1_AVAILABLE |
| #define | TIMER1A_AVAILABLE |
| #define | TIMER1B_AVAILABLE |
| #define | TIMER1C_AVAILABLE |
| #define | TIMER2_AVAILABLE |
| #define | TIMER2A_AVAILABLE |
| #define | TIMER2B_AVAILABLE |
| #define | TIMER3_AVAILABLE |
| #define | TIMER3A_AVAILABLE |
| #define | TIMER3B_AVAILABLE |
| #define | TIMER3C_AVAILABLE |
| #define | SIG_OVERFLOW0_NUM 0 |
| #define | SIG_OVERFLOW1_NUM 1 |
| #define | SIG_OVERFLOW2_NUM 2 |
| #define | SIG_OVERFLOW3_NUM 3 |
| #define | SIG_OVERFLOW_TOTAL_NUM 4 |
| #define | SIG_OUTPUT_COMPARE0A_NUM 0 |
| #define | SIG_OUTPUT_COMPARE0B_NUM 1 |
| #define | SIG_OUTPUT_COMPARE1A_NUM 2 |
| #define | SIG_OUTPUT_COMPARE1B_NUM 3 |
| #define | SIG_OUTPUT_COMPARE1C_NUM 4 |
| #define | SIG_OUTPUT_COMPARE2A_NUM 5 |
| #define | SIG_OUTPUT_COMPARE2B_NUM 6 |
| #define | SIG_OUTPUT_COMPARE3A_NUM 7 |
| #define | SIG_OUTPUT_COMPARE3B_NUM 8 |
| #define | SIG_OUTPUT_COMPARE3C_NUM 9 |
| #define | SIG_OUTPUT_COMPARE_TOTAL_NUM 10 |
| #define | PWM0A_NUM 0 |
| #define | PWM0B_NUM 1 |
| #define | PWM1A_NUM 2 |
| #define | PWM1B_NUM 3 |
| #define | PWM1C_NUM 4 |
| #define | PWM2A_NUM 5 |
| #define | PWM2B_NUM 6 |
| #define | PWM3A_NUM 7 |
| #define | PWM3B_NUM 8 |
| #define | PWM3C_NUM 9 |
| #define | PWM_TOTAL_NUM 10 |
| #define | SIG_INPUT_CAPTURE1_NUM 0 |
| #define | SIG_INPUT_CAPTURE3_NUM 1 |
| #define | SIG_INPUT_CAPTURE_TOTAL_NUM 2 |
| #define | UEBCHX_0_REG UEBCHX |
| #define | UEBCHX_1_REG UEBCHX |
| #define | UEBCHX_2_REG UEBCHX |
| #define | MUX0_REG ADMUX |
| #define | MUX1_REG ADMUX |
| #define | MUX2_REG ADMUX |
| #define | MUX3_REG ADMUX |
| #define | MUX4_REG ADMUX |
| #define | ADLAR_REG ADMUX |
| #define | REFS0_REG ADMUX |
| #define | REFS1_REG ADMUX |
| #define | SUSPE_REG UDIEN |
| #define | SOFE_REG UDIEN |
| #define | EORSTE_REG UDIEN |
| #define | WAKEUPE_REG UDIEN |
| #define | EORSME_REG UDIEN |
| #define | UPRSME_REG UDIEN |
| #define | WDP0_REG WDTCSR |
| #define | WDP1_REG WDTCSR |
| #define | WDP2_REG WDTCSR |
| #define | WDE_REG WDTCSR |
| #define | WDCE_REG WDTCSR |
| #define | WDP3_REG WDTCSR |
| #define | WDIE_REG WDTCSR |
| #define | WDIF_REG WDTCSR |
| #define | EEDR0_REG EEDR |
| #define | EEDR1_REG EEDR |
| #define | EEDR2_REG EEDR |
| #define | EEDR3_REG EEDR |
| #define | EEDR4_REG EEDR |
| #define | EEDR5_REG EEDR |
| #define | EEDR6_REG EEDR |
| #define | EEDR7_REG EEDR |
| #define | OCR0B_0_REG OCR0B |
| #define | OCR0B_1_REG OCR0B |
| #define | OCR0B_2_REG OCR0B |
| #define | OCR0B_3_REG OCR0B |
| #define | OCR0B_4_REG OCR0B |
| #define | OCR0B_5_REG OCR0B |
| #define | OCR0B_6_REG OCR0B |
| #define | OCR0B_7_REG OCR0B |
| #define | SUSPI_REG UDINT |
| #define | SOFI_REG UDINT |
| #define | EORSTI_REG UDINT |
| #define | WAKEUPI_REG UDINT |
| #define | EORSMI_REG UDINT |
| #define | UPRSMI_REG UDINT |
| #define | EPRST0_REG UERST |
| #define | EPRST1_REG UERST |
| #define | EPRST2_REG UERST |
| #define | EPRST3_REG UERST |
| #define | EPRST4_REG UERST |
| #define | EPRST5_REG UERST |
| #define | EPRST6_REG UERST |
| #define | ALLOC_REG UECFG1X |
| #define | EPBK0_REG UECFG1X |
| #define | EPBK1_REG UECFG1X |
| #define | EPSIZE0_REG UECFG1X |
| #define | EPSIZE1_REG UECFG1X |
| #define | EPSIZE2_REG UECFG1X |
| #define | OCR2B_0_REG OCR2B |
| #define | OCR2B_1_REG OCR2B |
| #define | OCR2B_2_REG OCR2B |
| #define | OCR2B_3_REG OCR2B |
| #define | OCR2B_4_REG OCR2B |
| #define | OCR2B_5_REG OCR2B |
| #define | OCR2B_6_REG OCR2B |
| #define | OCR2B_7_REG OCR2B |
| #define | OCR2A_0_REG OCR2A |
| #define | OCR2A_1_REG OCR2A |
| #define | OCR2A_2_REG OCR2A |
| #define | OCR2A_3_REG OCR2A |
| #define | OCR2A_4_REG OCR2A |
| #define | OCR2A_5_REG OCR2A |
| #define | OCR2A_6_REG OCR2A |
| #define | OCR2A_7_REG OCR2A |
| #define | SPDR0_REG SPDR |
| #define | SPDR1_REG SPDR |
| #define | SPDR2_REG SPDR |
| #define | SPDR3_REG SPDR |
| #define | SPDR4_REG SPDR |
| #define | SPDR5_REG SPDR |
| #define | SPDR6_REG SPDR |
| #define | SPDR7_REG SPDR |
| #define | SPI2X_REG SPSR |
| #define | WCOL_REG SPSR |
| #define | SPIF_REG SPSR |
| #define | ICR1H0_REG ICR1H |
| #define | ICR1H1_REG ICR1H |
| #define | ICR1H2_REG ICR1H |
| #define | ICR1H3_REG ICR1H |
| #define | ICR1H4_REG ICR1H |
| #define | ICR1H5_REG ICR1H |
| #define | ICR1H6_REG ICR1H |
| #define | ICR1H7_REG ICR1H |
| #define | ICR1L0_REG ICR1L |
| #define | ICR1L1_REG ICR1L |
| #define | ICR1L2_REG ICR1L |
| #define | ICR1L3_REG ICR1L |
| #define | ICR1L4_REG ICR1L |
| #define | ICR1L5_REG ICR1L |
| #define | ICR1L6_REG ICR1L |
| #define | ICR1L7_REG ICR1L |
| #define | EPINT0_REG UEINT |
| #define | EPINT1_REG UEINT |
| #define | EPINT2_REG UEINT |
| #define | EPINT3_REG UEINT |
| #define | EPINT4_REG UEINT |
| #define | EPINT5_REG UEINT |
| #define | EPINT6_REG UEINT |
| #define | TCNT1L0_REG TCNT1L |
| #define | TCNT1L1_REG TCNT1L |
| #define | TCNT1L2_REG TCNT1L |
| #define | TCNT1L3_REG TCNT1L |
| #define | TCNT1L4_REG TCNT1L |
| #define | TCNT1L5_REG TCNT1L |
| #define | TCNT1L6_REG TCNT1L |
| #define | TCNT1L7_REG TCNT1L |
| #define | PORTD0_REG PORTD |
| #define | PORTD1_REG PORTD |
| #define | PORTD2_REG PORTD |
| #define | PORTD3_REG PORTD |
| #define | PORTD4_REG PORTD |
| #define | PORTD5_REG PORTD |
| #define | PORTD6_REG PORTD |
| #define | PORTD7_REG PORTD |
| #define | PORTE0_REG PORTE |
| #define | PORTE1_REG PORTE |
| #define | PORTE2_REG PORTE |
| #define | PORTE3_REG PORTE |
| #define | PORTE4_REG PORTE |
| #define | PORTE5_REG PORTE |
| #define | PORTE6_REG PORTE |
| #define | PORTE7_REG PORTE |
| #define | TCNT1H0_REG TCNT1H |
| #define | TCNT1H1_REG TCNT1H |
| #define | TCNT1H2_REG TCNT1H |
| #define | TCNT1H3_REG TCNT1H |
| #define | TCNT1H4_REG TCNT1H |
| #define | TCNT1H5_REG TCNT1H |
| #define | TCNT1H6_REG TCNT1H |
| #define | TCNT1H7_REG TCNT1H |
| #define | PORTC0_REG PORTC |
| #define | PORTC1_REG PORTC |
| #define | PORTC2_REG PORTC |
| #define | PORTC3_REG PORTC |
| #define | PORTC4_REG PORTC |
| #define | PORTC5_REG PORTC |
| #define | PORTC6_REG PORTC |
| #define | PORTC7_REG PORTC |
| #define | PORTA0_REG PORTA |
| #define | PORTA1_REG PORTA |
| #define | PORTA2_REG PORTA |
| #define | PORTA3_REG PORTA |
| #define | PORTA4_REG PORTA |
| #define | PORTA5_REG PORTA |
| #define | PORTA6_REG PORTA |
| #define | PORTA7_REG PORTA |
| #define | INT0_REG EIMSK |
| #define | INT1_REG EIMSK |
| #define | INT2_REG EIMSK |
| #define | INT3_REG EIMSK |
| #define | INT4_REG EIMSK |
| #define | INT5_REG EIMSK |
| #define | INT6_REG EIMSK |
| #define | INT7_REG EIMSK |
| #define | UDR1_0_REG UDR1 |
| #define | UDR1_1_REG UDR1 |
| #define | UDR1_2_REG UDR1 |
| #define | UDR1_3_REG UDR1 |
| #define | UDR1_4_REG UDR1 |
| #define | UDR1_5_REG UDR1 |
| #define | UDR1_6_REG UDR1 |
| #define | UDR1_7_REG UDR1 |
| #define | ISC40_REG EICRB |
| #define | ISC41_REG EICRB |
| #define | ISC50_REG EICRB |
| #define | ISC51_REG EICRB |
| #define | ISC60_REG EICRB |
| #define | ISC61_REG EICRB |
| #define | ISC70_REG EICRB |
| #define | ISC71_REG EICRB |
| #define | UEDATX_0_REG UEDATX |
| #define | UEDATX_1_REG UEDATX |
| #define | UEDATX_2_REG UEDATX |
| #define | UEDATX_3_REG UEDATX |
| #define | UEDATX_4_REG UEDATX |
| #define | UEDATX_5_REG UEDATX |
| #define | UEDATX_6_REG UEDATX |
| #define | UEDATX_7_REG UEDATX |
| #define | ISC00_REG EICRA |
| #define | ISC01_REG EICRA |
| #define | ISC10_REG EICRA |
| #define | ISC11_REG EICRA |
| #define | ISC20_REG EICRA |
| #define | ISC21_REG EICRA |
| #define | ISC30_REG EICRA |
| #define | ISC31_REG EICRA |
| #define | EPDIR_REG UECFG0X |
| #define | EPTYPE0_REG UECFG0X |
| #define | EPTYPE1_REG UECFG0X |
| #define | ADC0D_REG DIDR0 |
| #define | ADC1D_REG DIDR0 |
| #define | ADC2D_REG DIDR0 |
| #define | ADC3D_REG DIDR0 |
| #define | ADC4D_REG DIDR0 |
| #define | ADC5D_REG DIDR0 |
| #define | ADC6D_REG DIDR0 |
| #define | ADC7D_REG DIDR0 |
| #define | AIN0D_REG DIDR1 |
| #define | AIN1D_REG DIDR1 |
| #define | DDF0_REG DDRF |
| #define | DDF1_REG DDRF |
| #define | DDF2_REG DDRF |
| #define | DDF3_REG DDRF |
| #define | DDF4_REG DDRF |
| #define | DDF5_REG DDRF |
| #define | DDF6_REG DDRF |
| #define | DDF7_REG DDRF |
| #define | TCR2BUB_REG ASSR |
| #define | TCR2AUB_REG ASSR |
| #define | OCR2BUB_REG ASSR |
| #define | OCR2AUB_REG ASSR |
| #define | TCN2UB_REG ASSR |
| #define | AS2_REG ASSR |
| #define | EXCLK_REG ASSR |
| #define | CLKPS0_REG CLKPR |
| #define | CLKPS1_REG CLKPR |
| #define | CLKPS2_REG CLKPR |
| #define | CLKPS3_REG CLKPR |
| #define | CLKPCE_REG CLKPR |
| #define | C_REG SREG |
| #define | Z_REG SREG |
| #define | N_REG SREG |
| #define | V_REG SREG |
| #define | S_REG SREG |
| #define | H_REG SREG |
| #define | T_REG SREG |
| #define | I_REG SREG |
| #define | UENUM_0_REG UENUM |
| #define | UENUM_1_REG UENUM |
| #define | UENUM_2_REG UENUM |
| #define | UBRR_0_REG UBRR1L |
| #define | UBRR_1_REG UBRR1L |
| #define | UBRR_2_REG UBRR1L |
| #define | UBRR_3_REG UBRR1L |
| #define | UBRR_4_REG UBRR1L |
| #define | UBRR_5_REG UBRR1L |
| #define | UBRR_6_REG UBRR1L |
| #define | UBRR_7_REG UBRR1L |
| #define | DDC0_REG DDRC |
| #define | DDC1_REG DDRC |
| #define | DDC2_REG DDRC |
| #define | DDC3_REG DDRC |
| #define | DDC4_REG DDRC |
| #define | DDC5_REG DDRC |
| #define | DDC6_REG DDRC |
| #define | DDC7_REG DDRC |
| #define | OCR3AL0_REG OCR3AL |
| #define | OCR3AL1_REG OCR3AL |
| #define | OCR3AL2_REG OCR3AL |
| #define | OCR3AL3_REG OCR3AL |
| #define | OCR3AL4_REG OCR3AL |
| #define | OCR3AL5_REG OCR3AL |
| #define | OCR3AL6_REG OCR3AL |
| #define | OCR3AL7_REG OCR3AL |
| #define | DDA0_REG DDRA |
| #define | DDA1_REG DDRA |
| #define | DDA2_REG DDRA |
| #define | DDA3_REG DDRA |
| #define | DDA4_REG DDRA |
| #define | DDA5_REG DDRA |
| #define | DDA6_REG DDRA |
| #define | DDA7_REG DDRA |
| #define | WGM10_REG TCCR1A |
| #define | WGM11_REG TCCR1A |
| #define | COM1C0_REG TCCR1A |
| #define | COM1C1_REG TCCR1A |
| #define | COM1B0_REG TCCR1A |
| #define | COM1B1_REG TCCR1A |
| #define | COM1A0_REG TCCR1A |
| #define | COM1A1_REG TCCR1A |
| #define | OCR3AH0_REG OCR3AH |
| #define | OCR3AH1_REG OCR3AH |
| #define | OCR3AH2_REG OCR3AH |
| #define | OCR3AH3_REG OCR3AH |
| #define | OCR3AH4_REG OCR3AH |
| #define | OCR3AH5_REG OCR3AH |
| #define | OCR3AH6_REG OCR3AH |
| #define | OCR3AH7_REG OCR3AH |
| #define | CS10_REG TCCR1B |
| #define | CS11_REG TCCR1B |
| #define | CS12_REG TCCR1B |
| #define | WGM12_REG TCCR1B |
| #define | WGM13_REG TCCR1B |
| #define | ICES1_REG TCCR1B |
| #define | ICNC1_REG TCCR1B |
| #define | CAL0_REG OSCCAL |
| #define | CAL1_REG OSCCAL |
| #define | CAL2_REG OSCCAL |
| #define | CAL3_REG OSCCAL |
| #define | CAL4_REG OSCCAL |
| #define | CAL5_REG OSCCAL |
| #define | CAL6_REG OSCCAL |
| #define | CAL7_REG OSCCAL |
| #define | DDD0_REG DDRD |
| #define | DDD1_REG DDRD |
| #define | DDD2_REG DDRD |
| #define | DDD3_REG DDRD |
| #define | DDD4_REG DDRD |
| #define | DDD5_REG DDRD |
| #define | DDD6_REG DDRD |
| #define | DDD7_REG DDRD |
| #define | GPIOR10_REG GPIOR1 |
| #define | GPIOR11_REG GPIOR1 |
| #define | GPIOR12_REG GPIOR1 |
| #define | GPIOR13_REG GPIOR1 |
| #define | GPIOR14_REG GPIOR1 |
| #define | GPIOR15_REG GPIOR1 |
| #define | GPIOR16_REG GPIOR1 |
| #define | GPIOR17_REG GPIOR1 |
| #define | GPIOR00_REG GPIOR0 |
| #define | GPIOR01_REG GPIOR0 |
| #define | GPIOR02_REG GPIOR0 |
| #define | GPIOR03_REG GPIOR0 |
| #define | GPIOR04_REG GPIOR0 |
| #define | GPIOR05_REG GPIOR0 |
| #define | GPIOR06_REG GPIOR0 |
| #define | GPIOR07_REG GPIOR0 |
| #define | GPIOR20_REG GPIOR2 |
| #define | GPIOR21_REG GPIOR2 |
| #define | GPIOR22_REG GPIOR2 |
| #define | GPIOR23_REG GPIOR2 |
| #define | GPIOR24_REG GPIOR2 |
| #define | GPIOR25_REG GPIOR2 |
| #define | GPIOR26_REG GPIOR2 |
| #define | GPIOR27_REG GPIOR2 |
| #define | DETACH_REG UDCON |
| #define | RMWKUP_REG UDCON |
| #define | LSM_REG UDCON |
| #define | PCIE0_REG PCICR |
| #define | VBUSTI_REG USBINT |
| #define | IDTI_REG USBINT |
| #define | TCNT2_0_REG TCNT2 |
| #define | TCNT2_1_REG TCNT2 |
| #define | TCNT2_2_REG TCNT2 |
| #define | TCNT2_3_REG TCNT2 |
| #define | TCNT2_4_REG TCNT2 |
| #define | TCNT2_5_REG TCNT2 |
| #define | TCNT2_6_REG TCNT2 |
| #define | TCNT2_7_REG TCNT2 |
| #define | TCNT0_0_REG TCNT0 |
| #define | TCNT0_1_REG TCNT0 |
| #define | TCNT0_2_REG TCNT0 |
| #define | TCNT0_3_REG TCNT0 |
| #define | TCNT0_4_REG TCNT0 |
| #define | TCNT0_5_REG TCNT0 |
| #define | TCNT0_6_REG TCNT0 |
| #define | TCNT0_7_REG TCNT0 |
| #define | TWGCE_REG TWAR |
| #define | TWA0_REG TWAR |
| #define | TWA1_REG TWAR |
| #define | TWA2_REG TWAR |
| #define | TWA3_REG TWAR |
| #define | TWA4_REG TWAR |
| #define | TWA5_REG TWAR |
| #define | TWA6_REG TWAR |
| #define | UVREGE_REG UHWCON |
| #define | UVCONE_REG UHWCON |
| #define | UIDE_REG UHWCON |
| #define | UIMOD_REG UHWCON |
| #define | CS00_REG TCCR0B |
| #define | CS01_REG TCCR0B |
| #define | CS02_REG TCCR0B |
| #define | WGM02_REG TCCR0B |
| #define | FOC0B_REG TCCR0B |
| #define | FOC0A_REG TCCR0B |
| #define | FNCERR_REG UDMFN |
| #define | WGM00_REG TCCR0A |
| #define | WGM01_REG TCCR0A |
| #define | COM0B0_REG TCCR0A |
| #define | COM0B1_REG TCCR0A |
| #define | COM0A0_REG TCCR0A |
| #define | COM0A1_REG TCCR0A |
| #define | TOV2_REG TIFR2 |
| #define | OCF2A_REG TIFR2 |
| #define | OCF2B_REG TIFR2 |
| #define | TOV3_REG TIFR3 |
| #define | OCF3A_REG TIFR3 |
| #define | OCF3B_REG TIFR3 |
| #define | OCF3C_REG TIFR3 |
| #define | ICF3_REG TIFR3 |
| #define | SPR0_REG SPCR |
| #define | SPR1_REG SPCR |
| #define | CPHA_REG SPCR |
| #define | CPOL_REG SPCR |
| #define | MSTR_REG SPCR |
| #define | DORD_REG SPCR |
| #define | SPE_REG SPCR |
| #define | SPIE_REG SPCR |
| #define | TOV1_REG TIFR1 |
| #define | OCF1A_REG TIFR1 |
| #define | OCF1B_REG TIFR1 |
| #define | OCF1C_REG TIFR1 |
| #define | ICF1_REG TIFR1 |
| #define | EEAR8_REG EEARH |
| #define | EEAR9_REG EEARH |
| #define | EEAR10_REG EEARH |
| #define | EEAR11_REG EEARH |
| #define | UEBCLX_0_REG UEBCLX |
| #define | UEBCLX_1_REG UEBCLX |
| #define | UEBCLX_2_REG UEBCLX |
| #define | UEBCLX_3_REG UEBCLX |
| #define | UEBCLX_4_REG UEBCLX |
| #define | UEBCLX_5_REG UEBCLX |
| #define | UEBCLX_6_REG UEBCLX |
| #define | UEBCLX_7_REG UEBCLX |
| #define | OCR3CH0_REG OCR3CH |
| #define | OCR3CH1_REG OCR3CH |
| #define | OCR3CH2_REG OCR3CH |
| #define | OCR3CH3_REG OCR3CH |
| #define | OCR3CH4_REG OCR3CH |
| #define | OCR3CH5_REG OCR3CH |
| #define | OCR3CH6_REG OCR3CH |
| #define | OCR3CH7_REG OCR3CH |
| #define | CURRBK0_REG UESTA1X |
| #define | CURRBK1_REG UESTA1X |
| #define | CTRLDIR_REG UESTA1X |
| #define | OCR3CL0_REG OCR3CL |
| #define | OCR3CL1_REG OCR3CL |
| #define | OCR3CL2_REG OCR3CL |
| #define | OCR3CL3_REG OCR3CL |
| #define | OCR3CL4_REG OCR3CL |
| #define | OCR3CL5_REG OCR3CL |
| #define | OCR3CL6_REG OCR3CL |
| #define | OCR3CL7_REG OCR3CL |
| #define | PSRSYNC_REG GTCCR |
| #define | TSM_REG GTCCR |
| #define | PSRASY_REG GTCCR |
| #define | TWBR0_REG TWBR |
| #define | TWBR1_REG TWBR |
| #define | TWBR2_REG TWBR |
| #define | TWBR3_REG TWBR |
| #define | TWBR4_REG TWBR |
| #define | TWBR5_REG TWBR |
| #define | TWBR6_REG TWBR |
| #define | TWBR7_REG TWBR |
| #define | SP8_REG SPH |
| #define | SP9_REG SPH |
| #define | SP10_REG SPH |
| #define | SP11_REG SPH |
| #define | SP12_REG SPH |
| #define | SP13_REG SPH |
| #define | SP14_REG SPH |
| #define | SP15_REG SPH |
| #define | FOC3C_REG TCCR3C |
| #define | FOC3B_REG TCCR3C |
| #define | FOC3A_REG TCCR3C |
| #define | CS30_REG TCCR3B |
| #define | CS31_REG TCCR3B |
| #define | CS32_REG TCCR3B |
| #define | WGM32_REG TCCR3B |
| #define | WGM33_REG TCCR3B |
| #define | ICES3_REG TCCR3B |
| #define | ICNC3_REG TCCR3B |
| #define | WGM30_REG TCCR3A |
| #define | WGM31_REG TCCR3A |
| #define | COM3C0_REG TCCR3A |
| #define | COM3C1_REG TCCR3A |
| #define | COM3B0_REG TCCR3A |
| #define | COM3B1_REG TCCR3A |
| #define | COM3A0_REG TCCR3A |
| #define | COM3A1_REG TCCR3A |
| #define | TXINI_REG UEINTX |
| #define | STALLEDI_REG UEINTX |
| #define | RXOUTI_REG UEINTX |
| #define | RXSTPI_REG UEINTX |
| #define | NAKOUTI_REG UEINTX |
| #define | RWAL_REG UEINTX |
| #define | NAKINI_REG UEINTX |
| #define | FIFOCON_REG UEINTX |
| #define | OCR1BL0_REG OCR1BL |
| #define | OCR1BL1_REG OCR1BL |
| #define | OCR1BL2_REG OCR1BL |
| #define | OCR1BL3_REG OCR1BL |
| #define | OCR1BL4_REG OCR1BL |
| #define | OCR1BL5_REG OCR1BL |
| #define | OCR1BL6_REG OCR1BL |
| #define | OCR1BL7_REG OCR1BL |
| #define | TCNT3H0_REG TCNT3H |
| #define | TCNT3H1_REG TCNT3H |
| #define | TCNT3H2_REG TCNT3H |
| #define | TCNT3H3_REG TCNT3H |
| #define | TCNT3H4_REG TCNT3H |
| #define | TCNT3H5_REG TCNT3H |
| #define | TCNT3H6_REG TCNT3H |
| #define | TCNT3H7_REG TCNT3H |
| #define | OCR1BH0_REG OCR1BH |
| #define | OCR1BH1_REG OCR1BH |
| #define | OCR1BH2_REG OCR1BH |
| #define | OCR1BH3_REG OCR1BH |
| #define | OCR1BH4_REG OCR1BH |
| #define | OCR1BH5_REG OCR1BH |
| #define | OCR1BH6_REG OCR1BH |
| #define | OCR1BH7_REG OCR1BH |
| #define | TCNT3L0_REG TCNT3L |
| #define | TCNT3L1_REG TCNT3L |
| #define | TCNT3L2_REG TCNT3L |
| #define | TCNT3L3_REG TCNT3L |
| #define | TCNT3L4_REG TCNT3L |
| #define | TCNT3L5_REG TCNT3L |
| #define | TCNT3L6_REG TCNT3L |
| #define | TCNT3L7_REG TCNT3L |
| #define | SP0_REG SPL |
| #define | SP1_REG SPL |
| #define | SP2_REG SPL |
| #define | SP3_REG SPL |
| #define | SP4_REG SPL |
| #define | SP5_REG SPL |
| #define | SP6_REG SPL |
| #define | SP7_REG SPL |
| #define | VBUSTE_REG USBCON |
| #define | IDTE_REG USBCON |
| #define | OTGPADE_REG USBCON |
| #define | FRZCLK_REG USBCON |
| #define | HOST_REG USBCON |
| #define | USBE_REG USBCON |
| #define | JTRF_REG MCUSR |
| #define | PORF_REG MCUSR |
| #define | EXTRF_REG MCUSR |
| #define | BORF_REG MCUSR |
| #define | WDRF_REG MCUSR |
| #define | EERE_REG EECR |
| #define | EEPE_REG EECR |
| #define | EEMPE_REG EECR |
| #define | EERIE_REG EECR |
| #define | EEPM0_REG EECR |
| #define | EEPM1_REG EECR |
| #define | SE_REG SMCR |
| #define | SM0_REG SMCR |
| #define | SM1_REG SMCR |
| #define | SM2_REG SMCR |
| #define | TWIE_REG TWCR |
| #define | TWEN_REG TWCR |
| #define | TWWC_REG TWCR |
| #define | TWSTO_REG TWCR |
| #define | TWSTA_REG TWCR |
| #define | TWEA_REG TWCR |
| #define | TWINT_REG TWCR |
| #define | PCIF0_REG PCIFR |
| #define | WGM20_REG TCCR2A |
| #define | WGM21_REG TCCR2A |
| #define | COM2B0_REG TCCR2A |
| #define | COM2B1_REG TCCR2A |
| #define | COM2A0_REG TCCR2A |
| #define | COM2A1_REG TCCR2A |
| #define | CS20_REG TCCR2B |
| #define | CS21_REG TCCR2B |
| #define | CS22_REG TCCR2B |
| #define | WGM22_REG TCCR2B |
| #define | FOC2B_REG TCCR2B |
| #define | FOC2A_REG TCCR2B |
| #define | EPEN_REG UECONX |
| #define | RSTDT_REG UECONX |
| #define | STALLRQC_REG UECONX |
| #define | STALLRQ_REG UECONX |
| #define | TWPS0_REG TWSR |
| #define | TWPS1_REG TWSR |
| #define | TWS3_REG TWSR |
| #define | TWS4_REG TWSR |
| #define | TWS5_REG TWSR |
| #define | TWS6_REG TWSR |
| #define | TWS7_REG TWSR |
| #define | EEAR0_REG EEARL |
| #define | EEAR1_REG EEARL |
| #define | EEAR2_REG EEARL |
| #define | EEAR3_REG EEARL |
| #define | EEAR4_REG EEARL |
| #define | EEAR5_REG EEARL |
| #define | EEAR6_REG EEARL |
| #define | EEAR7_REG EEARL |
| #define | JTD_REG MCUCR |
| #define | IVCE_REG MCUCR |
| #define | IVSEL_REG MCUCR |
| #define | PUD_REG MCUCR |
| #define | OCR1CL0_REG OCR1CL |
| #define | OCR1CL1_REG OCR1CL |
| #define | OCR1CL2_REG OCR1CL |
| #define | OCR1CL3_REG OCR1CL |
| #define | OCR1CL4_REG OCR1CL |
| #define | OCR1CL5_REG OCR1CL |
| #define | OCR1CL6_REG OCR1CL |
| #define | OCR1CL7_REG OCR1CL |
| #define | OCR1CH0_REG OCR1CH |
| #define | OCR1CH1_REG OCR1CH |
| #define | OCR1CH2_REG OCR1CH |
| #define | OCR1CH3_REG OCR1CH |
| #define | OCR1CH4_REG OCR1CH |
| #define | OCR1CH5_REG OCR1CH |
| #define | OCR1CH6_REG OCR1CH |
| #define | OCR1CH7_REG OCR1CH |
| #define | OCDR0_REG OCDR |
| #define | OCDR1_REG OCDR |
| #define | OCDR2_REG OCDR |
| #define | OCDR3_REG OCDR |
| #define | OCDR4_REG OCDR |
| #define | OCDR5_REG OCDR |
| #define | OCDR6_REG OCDR |
| #define | OCDR7_REG OCDR |
| #define | PINA0_REG PINA |
| #define | PINA1_REG PINA |
| #define | PINA2_REG PINA |
| #define | PINA3_REG PINA |
| #define | PINA4_REG PINA |
| #define | PINA5_REG PINA |
| #define | PINA6_REG PINA |
| #define | PINA7_REG PINA |
| #define | VBUS_REG USBSTA |
| #define | ID_REG USBSTA |
| #define | SPEED_REG USBSTA |
| #define | TXINE_REG UEIENX |
| #define | STALLEDE_REG UEIENX |
| #define | RXOUTE_REG UEIENX |
| #define | RXSTPE_REG UEIENX |
| #define | NAKOUTE_REG UEIENX |
| #define | NAKINE_REG UEIENX |
| #define | FLERRE_REG UEIENX |
| #define | TXB81_REG UCSR1B |
| #define | RXB81_REG UCSR1B |
| #define | UCSZ12_REG UCSR1B |
| #define | TXEN1_REG UCSR1B |
| #define | RXEN1_REG UCSR1B |
| #define | UDRIE1_REG UCSR1B |
| #define | TXCIE1_REG UCSR1B |
| #define | RXCIE1_REG UCSR1B |
| #define | UCPOL1_REG UCSR1C |
| #define | UCSZ10_REG UCSR1C |
| #define | UCSZ11_REG UCSR1C |
| #define | USBS1_REG UCSR1C |
| #define | UPM10_REG UCSR1C |
| #define | UPM11_REG UCSR1C |
| #define | UMSEL10_REG UCSR1C |
| #define | UMSEL11_REG UCSR1C |
| #define | MPCM1_REG UCSR1A |
| #define | U2X1_REG UCSR1A |
| #define | UPE1_REG UCSR1A |
| #define | DOR1_REG UCSR1A |
| #define | FE1_REG UCSR1A |
| #define | UDRE1_REG UCSR1A |
| #define | TXC1_REG UCSR1A |
| #define | RXC1_REG UCSR1A |
| #define | DDB0_REG DDRB |
| #define | DDB1_REG DDRB |
| #define | DDB2_REG DDRB |
| #define | DDB3_REG DDRB |
| #define | DDB4_REG DDRB |
| #define | DDB5_REG DDRB |
| #define | DDB6_REG DDRB |
| #define | DDB7_REG DDRB |
| #define | UDFNUML_0_REG UDFNUML |
| #define | UDFNUML_1_REG UDFNUML |
| #define | UDFNUML_2_REG UDFNUML |
| #define | UDFNUML_3_REG UDFNUML |
| #define | UDFNUML_4_REG UDFNUML |
| #define | UDFNUML_5_REG UDFNUML |
| #define | UDFNUML_6_REG UDFNUML |
| #define | UDFNUML_7_REG UDFNUML |
| #define | TWD0_REG TWDR |
| #define | TWD1_REG TWDR |
| #define | TWD2_REG TWDR |
| #define | TWD3_REG TWDR |
| #define | TWD4_REG TWDR |
| #define | TWD5_REG TWDR |
| #define | TWD6_REG TWDR |
| #define | TWD7_REG TWDR |
| #define | UDFNUMH_0_REG UDFNUMH |
| #define | UDFNUMH_1_REG UDFNUMH |
| #define | UDFNUMH_2_REG UDFNUMH |
| #define | TWAM0_REG TWAMR |
| #define | TWAM1_REG TWAMR |
| #define | TWAM2_REG TWAMR |
| #define | TWAM3_REG TWAMR |
| #define | TWAM4_REG TWAMR |
| #define | TWAM5_REG TWAMR |
| #define | TWAM6_REG TWAMR |
| #define | ADPS0_REG ADCSRA |
| #define | ADPS1_REG ADCSRA |
| #define | ADPS2_REG ADCSRA |
| #define | ADIE_REG ADCSRA |
| #define | ADIF_REG ADCSRA |
| #define | ADATE_REG ADCSRA |
| #define | ADSC_REG ADCSRA |
| #define | ADEN_REG ADCSRA |
| #define | ADTS0_REG ADCSRB |
| #define | ADTS1_REG ADCSRB |
| #define | ADTS2_REG ADCSRB |
| #define | ADHSM_REG ADCSRB |
| #define | ACME_REG ADCSRB |
| #define | PRADC_REG PRR0 |
| #define | PRSPI_REG PRR0 |
| #define | PRTIM1_REG PRR0 |
| #define | PRTIM0_REG PRR0 |
| #define | PRTIM2_REG PRR0 |
| #define | PRTWI_REG PRR0 |
| #define | UBRR_8_REG UBRR1H |
| #define | UBRR_9_REG UBRR1H |
| #define | UBRR_10_REG UBRR1H |
| #define | UBRR_11_REG UBRR1H |
| #define | OCROA_0_REG OCR0A |
| #define | OCROA_1_REG OCR0A |
| #define | OCROA_2_REG OCR0A |
| #define | OCROA_3_REG OCR0A |
| #define | OCROA_4_REG OCR0A |
| #define | OCROA_5_REG OCR0A |
| #define | OCROA_6_REG OCR0A |
| #define | OCROA_7_REG OCR0A |
| #define | ACIS0_REG ACSR |
| #define | ACIS1_REG ACSR |
| #define | ACIC_REG ACSR |
| #define | ACIE_REG ACSR |
| #define | ACI_REG ACSR |
| #define | ACO_REG ACSR |
| #define | ACBG_REG ACSR |
| #define | ACD_REG ACSR |
| #define | PORTF0_REG PORTF |
| #define | PORTF1_REG PORTF |
| #define | PORTF2_REG PORTF |
| #define | PORTF3_REG PORTF |
| #define | PORTF4_REG PORTF |
| #define | PORTF5_REG PORTF |
| #define | PORTF6_REG PORTF |
| #define | PORTF7_REG PORTF |
| #define | FOC1C_REG TCCR1C |
| #define | FOC1B_REG TCCR1C |
| #define | FOC1A_REG TCCR1C |
| #define | ICR3H0_REG ICR3H |
| #define | ICR3H1_REG ICR3H |
| #define | ICR3H2_REG ICR3H |
| #define | ICR3H3_REG ICR3H |
| #define | ICR3H4_REG ICR3H |
| #define | ICR3H5_REG ICR3H |
| #define | ICR3H6_REG ICR3H |
| #define | ICR3H7_REG ICR3H |
| #define | DDE0_REG DDRE |
| #define | DDE1_REG DDRE |
| #define | DDE2_REG DDRE |
| #define | DDE3_REG DDRE |
| #define | DDE4_REG DDRE |
| #define | DDE5_REG DDRE |
| #define | DDE6_REG DDRE |
| #define | DDE7_REG DDRE |
| #define | UADD0_REG UDADDR |
| #define | UADD1_REG UDADDR |
| #define | UADD2_REG UDADDR |
| #define | UADD3_REG UDADDR |
| #define | UADD4_REG UDADDR |
| #define | UADD5_REG UDADDR |
| #define | UADD6_REG UDADDR |
| #define | ADDEN_REG UDADDR |
| #define | ICR3L0_REG ICR3L |
| #define | ICR3L1_REG ICR3L |
| #define | ICR3L2_REG ICR3L |
| #define | ICR3L3_REG ICR3L |
| #define | ICR3L4_REG ICR3L |
| #define | ICR3L5_REG ICR3L |
| #define | ICR3L6_REG ICR3L |
| #define | ICR3L7_REG ICR3L |
| #define | SPMEN_REG SPMCSR |
| #define | PGERS_REG SPMCSR |
| #define | PGWRT_REG SPMCSR |
| #define | BLBSET_REG SPMCSR |
| #define | RWWSRE_REG SPMCSR |
| #define | SIGRD_REG SPMCSR |
| #define | RWWSB_REG SPMCSR |
| #define | SPMIE_REG SPMCSR |
| #define | NBUSYBK0_REG UESTA0X |
| #define | NBUSYBK1_REG UESTA0X |
| #define | DTSEQ0_REG UESTA0X |
| #define | DTSEQ1_REG UESTA0X |
| #define | UNDERFI_REG UESTA0X |
| #define | OVERFI_REG UESTA0X |
| #define | CFGOK_REG UESTA0X |
| #define | PORTB0_REG PORTB |
| #define | PORTB1_REG PORTB |
| #define | PORTB2_REG PORTB |
| #define | PORTB3_REG PORTB |
| #define | PORTB4_REG PORTB |
| #define | PORTB5_REG PORTB |
| #define | PORTB6_REG PORTB |
| #define | PORTB7_REG PORTB |
| #define | ADCL0_REG ADCL |
| #define | ADCL1_REG ADCL |
| #define | ADCL2_REG ADCL |
| #define | ADCL3_REG ADCL |
| #define | ADCL4_REG ADCL |
| #define | ADCL5_REG ADCL |
| #define | ADCL6_REG ADCL |
| #define | ADCL7_REG ADCL |
| #define | ADCH0_REG ADCH |
| #define | ADCH1_REG ADCH |
| #define | ADCH2_REG ADCH |
| #define | ADCH3_REG ADCH |
| #define | ADCH4_REG ADCH |
| #define | ADCH5_REG ADCH |
| #define | ADCH6_REG ADCH |
| #define | ADCH7_REG ADCH |
| #define | OCR3BL0_REG OCR3BL |
| #define | OCR3BL1_REG OCR3BL |
| #define | OCR3BL2_REG OCR3BL |
| #define | OCR3BL3_REG OCR3BL |
| #define | OCR3BL4_REG OCR3BL |
| #define | OCR3BL5_REG OCR3BL |
| #define | OCR3BL6_REG OCR3BL |
| #define | OCR3BL7_REG OCR3BL |
| #define | OCR3BH0_REG OCR3BH |
| #define | OCR3BH1_REG OCR3BH |
| #define | OCR3BH2_REG OCR3BH |
| #define | OCR3BH3_REG OCR3BH |
| #define | OCR3BH4_REG OCR3BH |
| #define | OCR3BH5_REG OCR3BH |
| #define | OCR3BH6_REG OCR3BH |
| #define | OCR3BH7_REG OCR3BH |
| #define | TOIE2_REG TIMSK2 |
| #define | OCIE2A_REG TIMSK2 |
| #define | OCIE2B_REG TIMSK2 |
| #define | TOIE3_REG TIMSK3 |
| #define | OCIE3A_REG TIMSK3 |
| #define | OCIE3B_REG TIMSK3 |
| #define | OCIE3C_REG TIMSK3 |
| #define | ICIE3_REG TIMSK3 |
| #define | TOIE0_REG TIMSK0 |
| #define | OCIE0A_REG TIMSK0 |
| #define | OCIE0B_REG TIMSK0 |
| #define | TOIE1_REG TIMSK1 |
| #define | OCIE1A_REG TIMSK1 |
| #define | OCIE1B_REG TIMSK1 |
| #define | OCIE1C_REG TIMSK1 |
| #define | ICIE1_REG TIMSK1 |
| #define | PLOCK_REG PLLCSR |
| #define | PLLE_REG PLLCSR |
| #define | PLLP0_REG PLLCSR |
| #define | PLLP1_REG PLLCSR |
| #define | PLLP2_REG PLLCSR |
| #define | PCINT0_REG PCMSK0 |
| #define | PCINT1_REG PCMSK0 |
| #define | PCINT2_REG PCMSK0 |
| #define | PCINT3_REG PCMSK0 |
| #define | PCINT4_REG PCMSK0 |
| #define | PCINT5_REG PCMSK0 |
| #define | PCINT6_REG PCMSK0 |
| #define | PCINT7_REG PCMSK0 |
| #define | XMM0_REG XMCRB |
| #define | XMM1_REG XMCRB |
| #define | XMM2_REG XMCRB |
| #define | XMBK_REG XMCRB |
| #define | SRW00_REG XMCRA |
| #define | SRW01_REG XMCRA |
| #define | SRW10_REG XMCRA |
| #define | SRW11_REG XMCRA |
| #define | SRL0_REG XMCRA |
| #define | SRL1_REG XMCRA |
| #define | SRL2_REG XMCRA |
| #define | SRE_REG XMCRA |
| #define | PINC0_REG PINC |
| #define | PINC1_REG PINC |
| #define | PINC2_REG PINC |
| #define | PINC3_REG PINC |
| #define | PINC4_REG PINC |
| #define | PINC5_REG PINC |
| #define | PINC6_REG PINC |
| #define | PINC7_REG PINC |
| #define | PINB0_REG PINB |
| #define | PINB1_REG PINB |
| #define | PINB2_REG PINB |
| #define | PINB3_REG PINB |
| #define | PINB4_REG PINB |
| #define | PINB5_REG PINB |
| #define | PINB6_REG PINB |
| #define | PINB7_REG PINB |
| #define | INTF0_REG EIFR |
| #define | INTF1_REG EIFR |
| #define | INTF2_REG EIFR |
| #define | INTF3_REG EIFR |
| #define | INTF4_REG EIFR |
| #define | INTF5_REG EIFR |
| #define | INTF6_REG EIFR |
| #define | INTF7_REG EIFR |
| #define | PINF0_REG PINF |
| #define | PINF1_REG PINF |
| #define | PINF2_REG PINF |
| #define | PINF3_REG PINF |
| #define | PINF4_REG PINF |
| #define | PINF5_REG PINF |
| #define | PINF6_REG PINF |
| #define | PINF7_REG PINF |
| #define | PINE0_REG PINE |
| #define | PINE1_REG PINE |
| #define | PINE2_REG PINE |
| #define | PINE3_REG PINE |
| #define | PINE4_REG PINE |
| #define | PINE5_REG PINE |
| #define | PINE6_REG PINE |
| #define | PINE7_REG PINE |
| #define | PIND0_REG PIND |
| #define | PIND1_REG PIND |
| #define | PIND2_REG PIND |
| #define | PIND3_REG PIND |
| #define | PIND4_REG PIND |
| #define | PIND5_REG PIND |
| #define | PIND6_REG PIND |
| #define | PIND7_REG PIND |
| #define | OCR1AH0_REG OCR1AH |
| #define | OCR1AH1_REG OCR1AH |
| #define | OCR1AH2_REG OCR1AH |
| #define | OCR1AH3_REG OCR1AH |
| #define | OCR1AH4_REG OCR1AH |
| #define | OCR1AH5_REG OCR1AH |
| #define | OCR1AH6_REG OCR1AH |
| #define | OCR1AH7_REG OCR1AH |
| #define | OCR1AL0_REG OCR1AL |
| #define | OCR1AL1_REG OCR1AL |
| #define | OCR1AL2_REG OCR1AL |
| #define | OCR1AL3_REG OCR1AL |
| #define | OCR1AL4_REG OCR1AL |
| #define | OCR1AL5_REG OCR1AL |
| #define | OCR1AL6_REG OCR1AL |
| #define | OCR1AL7_REG OCR1AL |
| #define | TOV0_REG TIFR0 |
| #define | OCF0A_REG TIFR0 |
| #define | OCF0B_REG TIFR0 |
| #define | PRUSART1_REG PRR1 |
| #define | PRTIM3_REG PRR1 |
| #define | PRUSB_REG PRR1 |
| #define ACBG_REG ACSR |
Definition at line 1100 of file ATmega32U6.h.
| #define ACD_REG ACSR |
Definition at line 1101 of file ATmega32U6.h.
| #define ACI_REG ACSR |
Definition at line 1098 of file ATmega32U6.h.
| #define ACIC_REG ACSR |
Definition at line 1096 of file ATmega32U6.h.
| #define ACIE_REG ACSR |
Definition at line 1097 of file ATmega32U6.h.
| #define ACIS0_REG ACSR |
Definition at line 1094 of file ATmega32U6.h.
| #define ACIS1_REG ACSR |
Definition at line 1095 of file ATmega32U6.h.
| #define ACME_REG ADCSRB |
Definition at line 1067 of file ATmega32U6.h.
| #define ACO_REG ACSR |
Definition at line 1099 of file ATmega32U6.h.
| #define ADATE_REG ADCSRA |
Definition at line 1058 of file ATmega32U6.h.
| #define ADC0D_REG DIDR0 |
Definition at line 417 of file ATmega32U6.h.
| #define ADC1D_REG DIDR0 |
Definition at line 418 of file ATmega32U6.h.
| #define ADC2D_REG DIDR0 |
Definition at line 419 of file ATmega32U6.h.
| #define ADC3D_REG DIDR0 |
Definition at line 420 of file ATmega32U6.h.
| #define ADC4D_REG DIDR0 |
Definition at line 421 of file ATmega32U6.h.
| #define ADC5D_REG DIDR0 |
Definition at line 422 of file ATmega32U6.h.
| #define ADC6D_REG DIDR0 |
Definition at line 423 of file ATmega32U6.h.
| #define ADC7D_REG DIDR0 |
Definition at line 424 of file ATmega32U6.h.
| #define ADCH0_REG ADCH |
Definition at line 1198 of file ATmega32U6.h.
| #define ADCH1_REG ADCH |
Definition at line 1199 of file ATmega32U6.h.
| #define ADCH2_REG ADCH |
Definition at line 1200 of file ATmega32U6.h.
| #define ADCH3_REG ADCH |
Definition at line 1201 of file ATmega32U6.h.
| #define ADCH4_REG ADCH |
Definition at line 1202 of file ATmega32U6.h.
| #define ADCH5_REG ADCH |
Definition at line 1203 of file ATmega32U6.h.
| #define ADCH6_REG ADCH |
Definition at line 1204 of file ATmega32U6.h.
| #define ADCH7_REG ADCH |
Definition at line 1205 of file ATmega32U6.h.
| #define ADCL0_REG ADCL |
Definition at line 1188 of file ATmega32U6.h.
| #define ADCL1_REG ADCL |
Definition at line 1189 of file ATmega32U6.h.
| #define ADCL2_REG ADCL |
Definition at line 1190 of file ATmega32U6.h.
| #define ADCL3_REG ADCL |
Definition at line 1191 of file ATmega32U6.h.
| #define ADCL4_REG ADCL |
Definition at line 1192 of file ATmega32U6.h.
| #define ADCL5_REG ADCL |
Definition at line 1193 of file ATmega32U6.h.
| #define ADCL6_REG ADCL |
Definition at line 1194 of file ATmega32U6.h.
| #define ADCL7_REG ADCL |
Definition at line 1195 of file ATmega32U6.h.
| #define ADDEN_REG UDADDR |
Definition at line 1146 of file ATmega32U6.h.
| #define ADEN_REG ADCSRA |
Definition at line 1060 of file ATmega32U6.h.
| #define ADHSM_REG ADCSRB |
Definition at line 1066 of file ATmega32U6.h.
| #define ADIE_REG ADCSRA |
Definition at line 1056 of file ATmega32U6.h.
| #define ADIF_REG ADCSRA |
Definition at line 1057 of file ATmega32U6.h.
| #define ADLAR_REG ADMUX |
Definition at line 170 of file ATmega32U6.h.
| #define ADPS0_REG ADCSRA |
Definition at line 1053 of file ATmega32U6.h.
| #define ADPS1_REG ADCSRA |
Definition at line 1054 of file ATmega32U6.h.
| #define ADPS2_REG ADCSRA |
Definition at line 1055 of file ATmega32U6.h.
| #define ADSC_REG ADCSRA |
Definition at line 1059 of file ATmega32U6.h.
| #define ADTS0_REG ADCSRB |
Definition at line 1063 of file ATmega32U6.h.
| #define ADTS1_REG ADCSRB |
Definition at line 1064 of file ATmega32U6.h.
| #define ADTS2_REG ADCSRB |
Definition at line 1065 of file ATmega32U6.h.
| #define AIN0D_REG DIDR1 |
Definition at line 427 of file ATmega32U6.h.
| #define AIN1D_REG DIDR1 |
Definition at line 428 of file ATmega32U6.h.
| #define ALLOC_REG UECFG1X |
Definition at line 230 of file ATmega32U6.h.
| #define AS2_REG ASSR |
Definition at line 446 of file ATmega32U6.h.
| #define BLBSET_REG SPMCSR |
Definition at line 1162 of file ATmega32U6.h.
| #define BORF_REG MCUSR |
Definition at line 848 of file ATmega32U6.h.
| #define C_REG SREG |
Definition at line 457 of file ATmega32U6.h.
| #define CAL0_REG OSCCAL |
Definition at line 541 of file ATmega32U6.h.
| #define CAL1_REG OSCCAL |
Definition at line 542 of file ATmega32U6.h.
| #define CAL2_REG OSCCAL |
Definition at line 543 of file ATmega32U6.h.
| #define CAL3_REG OSCCAL |
Definition at line 544 of file ATmega32U6.h.
| #define CAL4_REG OSCCAL |
Definition at line 545 of file ATmega32U6.h.
| #define CAL5_REG OSCCAL |
Definition at line 546 of file ATmega32U6.h.
| #define CAL6_REG OSCCAL |
Definition at line 547 of file ATmega32U6.h.
| #define CAL7_REG OSCCAL |
Definition at line 548 of file ATmega32U6.h.
| #define CFGOK_REG UESTA0X |
Definition at line 1175 of file ATmega32U6.h.
| #define CLKPCE_REG CLKPR |
Definition at line 454 of file ATmega32U6.h.
| #define CLKPS0_REG CLKPR |
Definition at line 450 of file ATmega32U6.h.
| #define CLKPS1_REG CLKPR |
Definition at line 451 of file ATmega32U6.h.
| #define CLKPS2_REG CLKPR |
Definition at line 452 of file ATmega32U6.h.
| #define CLKPS3_REG CLKPR |
Definition at line 453 of file ATmega32U6.h.
| #define COM0A0_REG TCCR0A |
Definition at line 654 of file ATmega32U6.h.
| #define COM0A1_REG TCCR0A |
Definition at line 655 of file ATmega32U6.h.
| #define COM0B0_REG TCCR0A |
Definition at line 652 of file ATmega32U6.h.
| #define COM0B1_REG TCCR0A |
Definition at line 653 of file ATmega32U6.h.
| #define COM1A0_REG TCCR1A |
Definition at line 518 of file ATmega32U6.h.
| #define COM1A1_REG TCCR1A |
Definition at line 519 of file ATmega32U6.h.
| #define COM1B0_REG TCCR1A |
Definition at line 516 of file ATmega32U6.h.
| #define COM1B1_REG TCCR1A |
Definition at line 517 of file ATmega32U6.h.
| #define COM1C0_REG TCCR1A |
Definition at line 514 of file ATmega32U6.h.
| #define COM1C1_REG TCCR1A |
Definition at line 515 of file ATmega32U6.h.
| #define COM2A0_REG TCCR2A |
Definition at line 882 of file ATmega32U6.h.
| #define COM2A1_REG TCCR2A |
Definition at line 883 of file ATmega32U6.h.
| #define COM2B0_REG TCCR2A |
Definition at line 880 of file ATmega32U6.h.
| #define COM2B1_REG TCCR2A |
Definition at line 881 of file ATmega32U6.h.
| #define COM3A0_REG TCCR3A |
Definition at line 773 of file ATmega32U6.h.
| #define COM3A1_REG TCCR3A |
Definition at line 774 of file ATmega32U6.h.
| #define COM3B0_REG TCCR3A |
Definition at line 771 of file ATmega32U6.h.
| #define COM3B1_REG TCCR3A |
Definition at line 772 of file ATmega32U6.h.
| #define COM3C0_REG TCCR3A |
Definition at line 769 of file ATmega32U6.h.
| #define COM3C1_REG TCCR3A |
Definition at line 770 of file ATmega32U6.h.
| #define CPHA_REG SPCR |
Definition at line 672 of file ATmega32U6.h.
| #define CPOL_REG SPCR |
Definition at line 673 of file ATmega32U6.h.
| #define CS00_REG TCCR0B |
Definition at line 639 of file ATmega32U6.h.
| #define CS01_REG TCCR0B |
Definition at line 640 of file ATmega32U6.h.
| #define CS02_REG TCCR0B |
Definition at line 641 of file ATmega32U6.h.
| #define CS10_REG TCCR1B |
Definition at line 532 of file ATmega32U6.h.
| #define CS11_REG TCCR1B |
Definition at line 533 of file ATmega32U6.h.
| #define CS12_REG TCCR1B |
Definition at line 534 of file ATmega32U6.h.
| #define CS20_REG TCCR2B |
Definition at line 886 of file ATmega32U6.h.
| #define CS21_REG TCCR2B |
Definition at line 887 of file ATmega32U6.h.
| #define CS22_REG TCCR2B |
Definition at line 888 of file ATmega32U6.h.
| #define CS30_REG TCCR3B |
Definition at line 758 of file ATmega32U6.h.
| #define CS31_REG TCCR3B |
Definition at line 759 of file ATmega32U6.h.
| #define CS32_REG TCCR3B |
Definition at line 760 of file ATmega32U6.h.
| #define CTRLDIR_REG UESTA1X |
Definition at line 715 of file ATmega32U6.h.
| #define CURRBK0_REG UESTA1X |
Definition at line 713 of file ATmega32U6.h.
| #define CURRBK1_REG UESTA1X |
Definition at line 714 of file ATmega32U6.h.
| #define DDA0_REG DDRA |
Definition at line 502 of file ATmega32U6.h.
| #define DDA1_REG DDRA |
Definition at line 503 of file ATmega32U6.h.
| #define DDA2_REG DDRA |
Definition at line 504 of file ATmega32U6.h.
| #define DDA3_REG DDRA |
Definition at line 505 of file ATmega32U6.h.
| #define DDA4_REG DDRA |
Definition at line 506 of file ATmega32U6.h.
| #define DDA5_REG DDRA |
Definition at line 507 of file ATmega32U6.h.
| #define DDA6_REG DDRA |
Definition at line 508 of file ATmega32U6.h.
| #define DDA7_REG DDRA |
Definition at line 509 of file ATmega32U6.h.
| #define DDB0_REG DDRB |
Definition at line 1009 of file ATmega32U6.h.
| #define DDB1_REG DDRB |
Definition at line 1010 of file ATmega32U6.h.
| #define DDB2_REG DDRB |
Definition at line 1011 of file ATmega32U6.h.
| #define DDB3_REG DDRB |
Definition at line 1012 of file ATmega32U6.h.
| #define DDB4_REG DDRB |
Definition at line 1013 of file ATmega32U6.h.
| #define DDB5_REG DDRB |
Definition at line 1014 of file ATmega32U6.h.
| #define DDB6_REG DDRB |
Definition at line 1015 of file ATmega32U6.h.
| #define DDB7_REG DDRB |
Definition at line 1016 of file ATmega32U6.h.
| #define DDC0_REG DDRC |
Definition at line 482 of file ATmega32U6.h.
| #define DDC1_REG DDRC |
Definition at line 483 of file ATmega32U6.h.
| #define DDC2_REG DDRC |
Definition at line 484 of file ATmega32U6.h.
| #define DDC3_REG DDRC |
Definition at line 485 of file ATmega32U6.h.
| #define DDC4_REG DDRC |
Definition at line 486 of file ATmega32U6.h.
| #define DDC5_REG DDRC |
Definition at line 487 of file ATmega32U6.h.
| #define DDC6_REG DDRC |
Definition at line 488 of file ATmega32U6.h.
| #define DDC7_REG DDRC |
Definition at line 489 of file ATmega32U6.h.
| #define DDD0_REG DDRD |
Definition at line 551 of file ATmega32U6.h.
| #define DDD1_REG DDRD |
Definition at line 552 of file ATmega32U6.h.
| #define DDD2_REG DDRD |
Definition at line 553 of file ATmega32U6.h.
| #define DDD3_REG DDRD |
Definition at line 554 of file ATmega32U6.h.
| #define DDD4_REG DDRD |
Definition at line 555 of file ATmega32U6.h.
| #define DDD5_REG DDRD |
Definition at line 556 of file ATmega32U6.h.
| #define DDD6_REG DDRD |
Definition at line 557 of file ATmega32U6.h.
| #define DDD7_REG DDRD |
Definition at line 558 of file ATmega32U6.h.
| #define DDE0_REG DDRE |
Definition at line 1129 of file ATmega32U6.h.
| #define DDE1_REG DDRE |
Definition at line 1130 of file ATmega32U6.h.
| #define DDE2_REG DDRE |
Definition at line 1131 of file ATmega32U6.h.
| #define DDE3_REG DDRE |
Definition at line 1132 of file ATmega32U6.h.
| #define DDE4_REG DDRE |
Definition at line 1133 of file ATmega32U6.h.
| #define DDE5_REG DDRE |
Definition at line 1134 of file ATmega32U6.h.
| #define DDE6_REG DDRE |
Definition at line 1135 of file ATmega32U6.h.
| #define DDE7_REG DDRE |
Definition at line 1136 of file ATmega32U6.h.
| #define DDF0_REG DDRF |
Definition at line 431 of file ATmega32U6.h.
| #define DDF1_REG DDRF |
Definition at line 432 of file ATmega32U6.h.
| #define DDF2_REG DDRF |
Definition at line 433 of file ATmega32U6.h.
| #define DDF3_REG DDRF |
Definition at line 434 of file ATmega32U6.h.
| #define DDF4_REG DDRF |
Definition at line 435 of file ATmega32U6.h.
| #define DDF5_REG DDRF |
Definition at line 436 of file ATmega32U6.h.
| #define DDF6_REG DDRF |
Definition at line 437 of file ATmega32U6.h.
| #define DDF7_REG DDRF |
Definition at line 438 of file ATmega32U6.h.
| #define DETACH_REG UDCON |
Definition at line 591 of file ATmega32U6.h.
| #define DOR1_REG UCSR1A |
Definition at line 1002 of file ATmega32U6.h.
| #define DORD_REG SPCR |
Definition at line 675 of file ATmega32U6.h.
| #define DTSEQ0_REG UESTA0X |
Definition at line 1171 of file ATmega32U6.h.
| #define DTSEQ1_REG UESTA0X |
Definition at line 1172 of file ATmega32U6.h.
| #define EEAR0_REG EEARL |
Definition at line 909 of file ATmega32U6.h.
| #define EEAR10_REG EEARH |
Definition at line 689 of file ATmega32U6.h.
| #define EEAR11_REG EEARH |
Definition at line 690 of file ATmega32U6.h.
| #define EEAR1_REG EEARL |
Definition at line 910 of file ATmega32U6.h.
| #define EEAR2_REG EEARL |
Definition at line 911 of file ATmega32U6.h.
| #define EEAR3_REG EEARL |
Definition at line 912 of file ATmega32U6.h.
| #define EEAR4_REG EEARL |
Definition at line 913 of file ATmega32U6.h.
| #define EEAR5_REG EEARL |
Definition at line 914 of file ATmega32U6.h.
| #define EEAR6_REG EEARL |
Definition at line 915 of file ATmega32U6.h.
| #define EEAR7_REG EEARL |
Definition at line 916 of file ATmega32U6.h.
| #define EEAR8_REG EEARH |
Definition at line 687 of file ATmega32U6.h.
| #define EEAR9_REG EEARH |
Definition at line 688 of file ATmega32U6.h.
| #define EEDR0_REG EEDR |
Definition at line 193 of file ATmega32U6.h.
| #define EEDR1_REG EEDR |
Definition at line 194 of file ATmega32U6.h.
| #define EEDR2_REG EEDR |
Definition at line 195 of file ATmega32U6.h.
| #define EEDR3_REG EEDR |
Definition at line 196 of file ATmega32U6.h.
| #define EEDR4_REG EEDR |
Definition at line 197 of file ATmega32U6.h.
| #define EEDR5_REG EEDR |
Definition at line 198 of file ATmega32U6.h.
| #define EEDR6_REG EEDR |
Definition at line 199 of file ATmega32U6.h.
| #define EEDR7_REG EEDR |
Definition at line 200 of file ATmega32U6.h.
| #define EEMPE_REG EECR |
Definition at line 854 of file ATmega32U6.h.
| #define EEPE_REG EECR |
Definition at line 853 of file ATmega32U6.h.
| #define EEPM0_REG EECR |
Definition at line 856 of file ATmega32U6.h.
| #define EEPM1_REG EECR |
Definition at line 857 of file ATmega32U6.h.
| #define EERE_REG EECR |
Definition at line 852 of file ATmega32U6.h.
| #define EERIE_REG EECR |
Definition at line 855 of file ATmega32U6.h.
| #define EORSME_REG UDIEN |
Definition at line 179 of file ATmega32U6.h.
| #define EORSMI_REG UDINT |
Definition at line 217 of file ATmega32U6.h.
| #define EORSTE_REG UDIEN |
Definition at line 177 of file ATmega32U6.h.
| #define EORSTI_REG UDINT |
Definition at line 215 of file ATmega32U6.h.
| #define EPBK0_REG UECFG1X |
Definition at line 231 of file ATmega32U6.h.
| #define EPBK1_REG UECFG1X |
Definition at line 232 of file ATmega32U6.h.
| #define EPDIR_REG UECFG0X |
Definition at line 412 of file ATmega32U6.h.
| #define EPEN_REG UECONX |
Definition at line 894 of file ATmega32U6.h.
| #define EPINT0_REG UEINT |
Definition at line 293 of file ATmega32U6.h.
| #define EPINT1_REG UEINT |
Definition at line 294 of file ATmega32U6.h.
| #define EPINT2_REG UEINT |
Definition at line 295 of file ATmega32U6.h.
| #define EPINT3_REG UEINT |
Definition at line 296 of file ATmega32U6.h.
| #define EPINT4_REG UEINT |
Definition at line 297 of file ATmega32U6.h.
| #define EPINT5_REG UEINT |
Definition at line 298 of file ATmega32U6.h.
| #define EPINT6_REG UEINT |
Definition at line 299 of file ATmega32U6.h.
| #define EPRST0_REG UERST |
Definition at line 221 of file ATmega32U6.h.
| #define EPRST1_REG UERST |
Definition at line 222 of file ATmega32U6.h.
| #define EPRST2_REG UERST |
Definition at line 223 of file ATmega32U6.h.
| #define EPRST3_REG UERST |
Definition at line 224 of file ATmega32U6.h.
| #define EPRST4_REG UERST |
Definition at line 225 of file ATmega32U6.h.
| #define EPRST5_REG UERST |
Definition at line 226 of file ATmega32U6.h.
| #define EPRST6_REG UERST |
Definition at line 227 of file ATmega32U6.h.
| #define EPSIZE0_REG UECFG1X |
Definition at line 233 of file ATmega32U6.h.
| #define EPSIZE1_REG UECFG1X |
Definition at line 234 of file ATmega32U6.h.
| #define EPSIZE2_REG UECFG1X |
Definition at line 235 of file ATmega32U6.h.
| #define EPTYPE0_REG UECFG0X |
Definition at line 413 of file ATmega32U6.h.
| #define EPTYPE1_REG UECFG0X |
Definition at line 414 of file ATmega32U6.h.
| #define EXCLK_REG ASSR |
Definition at line 447 of file ATmega32U6.h.
| #define EXTRF_REG MCUSR |
Definition at line 847 of file ATmega32U6.h.
| #define FE1_REG UCSR1A |
Definition at line 1003 of file ATmega32U6.h.
| #define FIFOCON_REG UEINTX |
Definition at line 784 of file ATmega32U6.h.
| #define FLERRE_REG UEIENX |
Definition at line 976 of file ATmega32U6.h.
| #define FNCERR_REG UDMFN |
Definition at line 647 of file ATmega32U6.h.
| #define FOC0A_REG TCCR0B |
Definition at line 644 of file ATmega32U6.h.
| #define FOC0B_REG TCCR0B |
Definition at line 643 of file ATmega32U6.h.
| #define FOC1A_REG TCCR1C |
Definition at line 1116 of file ATmega32U6.h.
| #define FOC1B_REG TCCR1C |
Definition at line 1115 of file ATmega32U6.h.
| #define FOC1C_REG TCCR1C |
Definition at line 1114 of file ATmega32U6.h.
| #define FOC2A_REG TCCR2B |
Definition at line 891 of file ATmega32U6.h.
| #define FOC2B_REG TCCR2B |
Definition at line 890 of file ATmega32U6.h.
| #define FOC3A_REG TCCR3C |
Definition at line 755 of file ATmega32U6.h.
| #define FOC3B_REG TCCR3C |
Definition at line 754 of file ATmega32U6.h.
| #define FOC3C_REG TCCR3C |
Definition at line 753 of file ATmega32U6.h.
| #define FRZCLK_REG USBCON |
Definition at line 840 of file ATmega32U6.h.
| #define GPIOR00_REG GPIOR0 |
Definition at line 571 of file ATmega32U6.h.
| #define GPIOR01_REG GPIOR0 |
Definition at line 572 of file ATmega32U6.h.
| #define GPIOR02_REG GPIOR0 |
Definition at line 573 of file ATmega32U6.h.
| #define GPIOR03_REG GPIOR0 |
Definition at line 574 of file ATmega32U6.h.
| #define GPIOR04_REG GPIOR0 |
Definition at line 575 of file ATmega32U6.h.
| #define GPIOR05_REG GPIOR0 |
Definition at line 576 of file ATmega32U6.h.
| #define GPIOR06_REG GPIOR0 |
Definition at line 577 of file ATmega32U6.h.
| #define GPIOR07_REG GPIOR0 |
Definition at line 578 of file ATmega32U6.h.
| #define GPIOR10_REG GPIOR1 |
Definition at line 561 of file ATmega32U6.h.
| #define GPIOR11_REG GPIOR1 |
Definition at line 562 of file ATmega32U6.h.
| #define GPIOR12_REG GPIOR1 |
Definition at line 563 of file ATmega32U6.h.
| #define GPIOR13_REG GPIOR1 |
Definition at line 564 of file ATmega32U6.h.
| #define GPIOR14_REG GPIOR1 |
Definition at line 565 of file ATmega32U6.h.
| #define GPIOR15_REG GPIOR1 |
Definition at line 566 of file ATmega32U6.h.
| #define GPIOR16_REG GPIOR1 |
Definition at line 567 of file ATmega32U6.h.
| #define GPIOR17_REG GPIOR1 |
Definition at line 568 of file ATmega32U6.h.
| #define GPIOR20_REG GPIOR2 |
Definition at line 581 of file ATmega32U6.h.
| #define GPIOR21_REG GPIOR2 |
Definition at line 582 of file ATmega32U6.h.
| #define GPIOR22_REG GPIOR2 |
Definition at line 583 of file ATmega32U6.h.
| #define GPIOR23_REG GPIOR2 |
Definition at line 584 of file ATmega32U6.h.
| #define GPIOR24_REG GPIOR2 |
Definition at line 585 of file ATmega32U6.h.
| #define GPIOR25_REG GPIOR2 |
Definition at line 586 of file ATmega32U6.h.
| #define GPIOR26_REG GPIOR2 |
Definition at line 587 of file ATmega32U6.h.
| #define GPIOR27_REG GPIOR2 |
Definition at line 588 of file ATmega32U6.h.
| #define H_REG SREG |
Definition at line 462 of file ATmega32U6.h.
| #define HOST_REG USBCON |
Definition at line 841 of file ATmega32U6.h.
| #define I_REG SREG |
Definition at line 464 of file ATmega32U6.h.
| #define ICES1_REG TCCR1B |
Definition at line 537 of file ATmega32U6.h.
| #define ICES3_REG TCCR3B |
Definition at line 763 of file ATmega32U6.h.
| #define ICF1_REG TIFR1 |
Definition at line 684 of file ATmega32U6.h.
| #define ICF3_REG TIFR3 |
Definition at line 667 of file ATmega32U6.h.
| #define ICIE1_REG TIMSK1 |
Definition at line 1249 of file ATmega32U6.h.
| #define ICIE3_REG TIMSK3 |
Definition at line 1237 of file ATmega32U6.h.
| #define ICNC1_REG TCCR1B |
Definition at line 538 of file ATmega32U6.h.
| #define ICNC3_REG TCCR3B |
Definition at line 764 of file ATmega32U6.h.
| #define ICR1H0_REG ICR1H |
Definition at line 273 of file ATmega32U6.h.
| #define ICR1H1_REG ICR1H |
Definition at line 274 of file ATmega32U6.h.
| #define ICR1H2_REG ICR1H |
Definition at line 275 of file ATmega32U6.h.
| #define ICR1H3_REG ICR1H |
Definition at line 276 of file ATmega32U6.h.
| #define ICR1H4_REG ICR1H |
Definition at line 277 of file ATmega32U6.h.
| #define ICR1H5_REG ICR1H |
Definition at line 278 of file ATmega32U6.h.
| #define ICR1H6_REG ICR1H |
Definition at line 279 of file ATmega32U6.h.
| #define ICR1H7_REG ICR1H |
Definition at line 280 of file ATmega32U6.h.
| #define ICR1L0_REG ICR1L |
Definition at line 283 of file ATmega32U6.h.
| #define ICR1L1_REG ICR1L |
Definition at line 284 of file ATmega32U6.h.
| #define ICR1L2_REG ICR1L |
Definition at line 285 of file ATmega32U6.h.
| #define ICR1L3_REG ICR1L |
Definition at line 286 of file ATmega32U6.h.
| #define ICR1L4_REG ICR1L |
Definition at line 287 of file ATmega32U6.h.
| #define ICR1L5_REG ICR1L |
Definition at line 288 of file ATmega32U6.h.
| #define ICR1L6_REG ICR1L |
Definition at line 289 of file ATmega32U6.h.
| #define ICR1L7_REG ICR1L |
Definition at line 290 of file ATmega32U6.h.
| #define ICR3H0_REG ICR3H |
Definition at line 1119 of file ATmega32U6.h.
| #define ICR3H1_REG ICR3H |
Definition at line 1120 of file ATmega32U6.h.
| #define ICR3H2_REG ICR3H |
Definition at line 1121 of file ATmega32U6.h.
| #define ICR3H3_REG ICR3H |
Definition at line 1122 of file ATmega32U6.h.
| #define ICR3H4_REG ICR3H |
Definition at line 1123 of file ATmega32U6.h.
| #define ICR3H5_REG ICR3H |
Definition at line 1124 of file ATmega32U6.h.
| #define ICR3H6_REG ICR3H |
Definition at line 1125 of file ATmega32U6.h.
| #define ICR3H7_REG ICR3H |
Definition at line 1126 of file ATmega32U6.h.
| #define ICR3L0_REG ICR3L |
Definition at line 1149 of file ATmega32U6.h.
| #define ICR3L1_REG ICR3L |
Definition at line 1150 of file ATmega32U6.h.
| #define ICR3L2_REG ICR3L |
Definition at line 1151 of file ATmega32U6.h.
| #define ICR3L3_REG ICR3L |
Definition at line 1152 of file ATmega32U6.h.
| #define ICR3L4_REG ICR3L |
Definition at line 1153 of file ATmega32U6.h.
| #define ICR3L5_REG ICR3L |
Definition at line 1154 of file ATmega32U6.h.
| #define ICR3L6_REG ICR3L |
Definition at line 1155 of file ATmega32U6.h.
| #define ICR3L7_REG ICR3L |
Definition at line 1156 of file ATmega32U6.h.
| #define ID_REG USBSTA |
Definition at line 966 of file ATmega32U6.h.
| #define IDTE_REG USBCON |
Definition at line 838 of file ATmega32U6.h.
| #define IDTI_REG USBINT |
Definition at line 600 of file ATmega32U6.h.
| #define INT0_REG EIMSK |
Definition at line 362 of file ATmega32U6.h.
| #define INT1_REG EIMSK |
Definition at line 363 of file ATmega32U6.h.
| #define INT2_REG EIMSK |
Definition at line 364 of file ATmega32U6.h.
| #define INT3_REG EIMSK |
Definition at line 365 of file ATmega32U6.h.
| #define INT4_REG EIMSK |
Definition at line 366 of file ATmega32U6.h.
| #define INT5_REG EIMSK |
Definition at line 367 of file ATmega32U6.h.
| #define INT6_REG EIMSK |
Definition at line 368 of file ATmega32U6.h.
| #define INT7_REG EIMSK |
Definition at line 369 of file ATmega32U6.h.
| #define INTF0_REG EIFR |
Definition at line 1305 of file ATmega32U6.h.
| #define INTF1_REG EIFR |
Definition at line 1306 of file ATmega32U6.h.
| #define INTF2_REG EIFR |
Definition at line 1307 of file ATmega32U6.h.
| #define INTF3_REG EIFR |
Definition at line 1308 of file ATmega32U6.h.
| #define INTF4_REG EIFR |
Definition at line 1309 of file ATmega32U6.h.
| #define INTF5_REG EIFR |
Definition at line 1310 of file ATmega32U6.h.
| #define INTF6_REG EIFR |
Definition at line 1311 of file ATmega32U6.h.
| #define INTF7_REG EIFR |
Definition at line 1312 of file ATmega32U6.h.
| #define ISC00_REG EICRA |
Definition at line 402 of file ATmega32U6.h.
| #define ISC01_REG EICRA |
Definition at line 403 of file ATmega32U6.h.
| #define ISC10_REG EICRA |
Definition at line 404 of file ATmega32U6.h.
| #define ISC11_REG EICRA |
Definition at line 405 of file ATmega32U6.h.
| #define ISC20_REG EICRA |
Definition at line 406 of file ATmega32U6.h.
| #define ISC21_REG EICRA |
Definition at line 407 of file ATmega32U6.h.
| #define ISC30_REG EICRA |
Definition at line 408 of file ATmega32U6.h.
| #define ISC31_REG EICRA |
Definition at line 409 of file ATmega32U6.h.
| #define ISC40_REG EICRB |
Definition at line 382 of file ATmega32U6.h.
| #define ISC41_REG EICRB |
Definition at line 383 of file ATmega32U6.h.
| #define ISC50_REG EICRB |
Definition at line 384 of file ATmega32U6.h.
| #define ISC51_REG EICRB |
Definition at line 385 of file ATmega32U6.h.
| #define ISC60_REG EICRB |
Definition at line 386 of file ATmega32U6.h.
| #define ISC61_REG EICRB |
Definition at line 387 of file ATmega32U6.h.
| #define ISC70_REG EICRB |
Definition at line 388 of file ATmega32U6.h.
| #define ISC71_REG EICRB |
Definition at line 389 of file ATmega32U6.h.
| #define IVCE_REG MCUCR |
Definition at line 920 of file ATmega32U6.h.
| #define IVSEL_REG MCUCR |
Definition at line 921 of file ATmega32U6.h.
| #define JTD_REG MCUCR |
Definition at line 919 of file ATmega32U6.h.
| #define JTRF_REG MCUSR |
Definition at line 845 of file ATmega32U6.h.
| #define LSM_REG UDCON |
Definition at line 593 of file ATmega32U6.h.
| #define MPCM1_REG UCSR1A |
Definition at line 999 of file ATmega32U6.h.
| #define MSTR_REG SPCR |
Definition at line 674 of file ATmega32U6.h.
| #define MUX0_REG ADMUX |
Definition at line 165 of file ATmega32U6.h.
| #define MUX1_REG ADMUX |
Definition at line 166 of file ATmega32U6.h.
| #define MUX2_REG ADMUX |
Definition at line 167 of file ATmega32U6.h.
| #define MUX3_REG ADMUX |
Definition at line 168 of file ATmega32U6.h.
| #define MUX4_REG ADMUX |
Definition at line 169 of file ATmega32U6.h.
| #define N_REG SREG |
Definition at line 459 of file ATmega32U6.h.
| #define NAKINE_REG UEIENX |
Definition at line 975 of file ATmega32U6.h.
| #define NAKINI_REG UEINTX |
Definition at line 783 of file ATmega32U6.h.
| #define NAKOUTE_REG UEIENX |
Definition at line 974 of file ATmega32U6.h.
| #define NAKOUTI_REG UEINTX |
Definition at line 781 of file ATmega32U6.h.
| #define NBUSYBK0_REG UESTA0X |
Definition at line 1169 of file ATmega32U6.h.
| #define NBUSYBK1_REG UESTA0X |
Definition at line 1170 of file ATmega32U6.h.
| #define OCDR0_REG OCDR |
Definition at line 945 of file ATmega32U6.h.
| #define OCDR1_REG OCDR |
Definition at line 946 of file ATmega32U6.h.
| #define OCDR2_REG OCDR |
Definition at line 947 of file ATmega32U6.h.
| #define OCDR3_REG OCDR |
Definition at line 948 of file ATmega32U6.h.
| #define OCDR4_REG OCDR |
Definition at line 949 of file ATmega32U6.h.
| #define OCDR5_REG OCDR |
Definition at line 950 of file ATmega32U6.h.
| #define OCDR6_REG OCDR |
Definition at line 951 of file ATmega32U6.h.
| #define OCDR7_REG OCDR |
Definition at line 952 of file ATmega32U6.h.
| #define OCF0A_REG TIFR0 |
Definition at line 1366 of file ATmega32U6.h.
| #define OCF0B_REG TIFR0 |
Definition at line 1367 of file ATmega32U6.h.
| #define OCF1A_REG TIFR1 |
Definition at line 681 of file ATmega32U6.h.
| #define OCF1B_REG TIFR1 |
Definition at line 682 of file ATmega32U6.h.
| #define OCF1C_REG TIFR1 |
Definition at line 683 of file ATmega32U6.h.
| #define OCF2A_REG TIFR2 |
Definition at line 659 of file ATmega32U6.h.
| #define OCF2B_REG TIFR2 |
Definition at line 660 of file ATmega32U6.h.
| #define OCF3A_REG TIFR3 |
Definition at line 664 of file ATmega32U6.h.
| #define OCF3B_REG TIFR3 |
Definition at line 665 of file ATmega32U6.h.
| #define OCF3C_REG TIFR3 |
Definition at line 666 of file ATmega32U6.h.
| #define OCIE0A_REG TIMSK0 |
Definition at line 1241 of file ATmega32U6.h.
| #define OCIE0B_REG TIMSK0 |
Definition at line 1242 of file ATmega32U6.h.
| #define OCIE1A_REG TIMSK1 |
Definition at line 1246 of file ATmega32U6.h.
| #define OCIE1B_REG TIMSK1 |
Definition at line 1247 of file ATmega32U6.h.
| #define OCIE1C_REG TIMSK1 |
Definition at line 1248 of file ATmega32U6.h.
| #define OCIE2A_REG TIMSK2 |
Definition at line 1229 of file ATmega32U6.h.
| #define OCIE2B_REG TIMSK2 |
Definition at line 1230 of file ATmega32U6.h.
| #define OCIE3A_REG TIMSK3 |
Definition at line 1234 of file ATmega32U6.h.
| #define OCIE3B_REG TIMSK3 |
Definition at line 1235 of file ATmega32U6.h.
| #define OCIE3C_REG TIMSK3 |
Definition at line 1236 of file ATmega32U6.h.
| #define OCR0B_0_REG OCR0B |
Definition at line 203 of file ATmega32U6.h.
| #define OCR0B_1_REG OCR0B |
Definition at line 204 of file ATmega32U6.h.
| #define OCR0B_2_REG OCR0B |
Definition at line 205 of file ATmega32U6.h.
| #define OCR0B_3_REG OCR0B |
Definition at line 206 of file ATmega32U6.h.
| #define OCR0B_4_REG OCR0B |
Definition at line 207 of file ATmega32U6.h.
| #define OCR0B_5_REG OCR0B |
Definition at line 208 of file ATmega32U6.h.
| #define OCR0B_6_REG OCR0B |
Definition at line 209 of file ATmega32U6.h.
| #define OCR0B_7_REG OCR0B |
Definition at line 210 of file ATmega32U6.h.
| #define OCR1AH0_REG OCR1AH |
Definition at line 1345 of file ATmega32U6.h.
| #define OCR1AH1_REG OCR1AH |
Definition at line 1346 of file ATmega32U6.h.
| #define OCR1AH2_REG OCR1AH |
Definition at line 1347 of file ATmega32U6.h.
| #define OCR1AH3_REG OCR1AH |
Definition at line 1348 of file ATmega32U6.h.
| #define OCR1AH4_REG OCR1AH |
Definition at line 1349 of file ATmega32U6.h.
| #define OCR1AH5_REG OCR1AH |
Definition at line 1350 of file ATmega32U6.h.
| #define OCR1AH6_REG OCR1AH |
Definition at line 1351 of file ATmega32U6.h.
| #define OCR1AH7_REG OCR1AH |
Definition at line 1352 of file ATmega32U6.h.
| #define OCR1AL0_REG OCR1AL |
Definition at line 1355 of file ATmega32U6.h.
| #define OCR1AL1_REG OCR1AL |
Definition at line 1356 of file ATmega32U6.h.
| #define OCR1AL2_REG OCR1AL |
Definition at line 1357 of file ATmega32U6.h.
| #define OCR1AL3_REG OCR1AL |
Definition at line 1358 of file ATmega32U6.h.
| #define OCR1AL4_REG OCR1AL |
Definition at line 1359 of file ATmega32U6.h.
| #define OCR1AL5_REG OCR1AL |
Definition at line 1360 of file ATmega32U6.h.
| #define OCR1AL6_REG OCR1AL |
Definition at line 1361 of file ATmega32U6.h.
| #define OCR1AL7_REG OCR1AL |
Definition at line 1362 of file ATmega32U6.h.
| #define OCR1BH0_REG OCR1BH |
Definition at line 807 of file ATmega32U6.h.
| #define OCR1BH1_REG OCR1BH |
Definition at line 808 of file ATmega32U6.h.
| #define OCR1BH2_REG OCR1BH |
Definition at line 809 of file ATmega32U6.h.
| #define OCR1BH3_REG OCR1BH |
Definition at line 810 of file ATmega32U6.h.
| #define OCR1BH4_REG OCR1BH |
Definition at line 811 of file ATmega32U6.h.
| #define OCR1BH5_REG OCR1BH |
Definition at line 812 of file ATmega32U6.h.
| #define OCR1BH6_REG OCR1BH |
Definition at line 813 of file ATmega32U6.h.
| #define OCR1BH7_REG OCR1BH |
Definition at line 814 of file ATmega32U6.h.
| #define OCR1BL0_REG OCR1BL |
Definition at line 787 of file ATmega32U6.h.
| #define OCR1BL1_REG OCR1BL |
Definition at line 788 of file ATmega32U6.h.
| #define OCR1BL2_REG OCR1BL |
Definition at line 789 of file ATmega32U6.h.
| #define OCR1BL3_REG OCR1BL |
Definition at line 790 of file ATmega32U6.h.
| #define OCR1BL4_REG OCR1BL |
Definition at line 791 of file ATmega32U6.h.
| #define OCR1BL5_REG OCR1BL |
Definition at line 792 of file ATmega32U6.h.
| #define OCR1BL6_REG OCR1BL |
Definition at line 793 of file ATmega32U6.h.
| #define OCR1BL7_REG OCR1BL |
Definition at line 794 of file ATmega32U6.h.
| #define OCR1CH0_REG OCR1CH |
Definition at line 935 of file ATmega32U6.h.
| #define OCR1CH1_REG OCR1CH |
Definition at line 936 of file ATmega32U6.h.
| #define OCR1CH2_REG OCR1CH |
Definition at line 937 of file ATmega32U6.h.
| #define OCR1CH3_REG OCR1CH |
Definition at line 938 of file ATmega32U6.h.
| #define OCR1CH4_REG OCR1CH |
Definition at line 939 of file ATmega32U6.h.
| #define OCR1CH5_REG OCR1CH |
Definition at line 940 of file ATmega32U6.h.
| #define OCR1CH6_REG OCR1CH |
Definition at line 941 of file ATmega32U6.h.
| #define OCR1CH7_REG OCR1CH |
Definition at line 942 of file ATmega32U6.h.
| #define OCR1CL0_REG OCR1CL |
Definition at line 925 of file ATmega32U6.h.
| #define OCR1CL1_REG OCR1CL |
Definition at line 926 of file ATmega32U6.h.
| #define OCR1CL2_REG OCR1CL |
Definition at line 927 of file ATmega32U6.h.
| #define OCR1CL3_REG OCR1CL |
Definition at line 928 of file ATmega32U6.h.
| #define OCR1CL4_REG OCR1CL |
Definition at line 929 of file ATmega32U6.h.
| #define OCR1CL5_REG OCR1CL |
Definition at line 930 of file ATmega32U6.h.
| #define OCR1CL6_REG OCR1CL |
Definition at line 931 of file ATmega32U6.h.
| #define OCR1CL7_REG OCR1CL |
Definition at line 932 of file ATmega32U6.h.
| #define OCR2A_0_REG OCR2A |
Definition at line 248 of file ATmega32U6.h.
| #define OCR2A_1_REG OCR2A |
Definition at line 249 of file ATmega32U6.h.
| #define OCR2A_2_REG OCR2A |
Definition at line 250 of file ATmega32U6.h.
| #define OCR2A_3_REG OCR2A |
Definition at line 251 of file ATmega32U6.h.
| #define OCR2A_4_REG OCR2A |
Definition at line 252 of file ATmega32U6.h.
| #define OCR2A_5_REG OCR2A |
Definition at line 253 of file ATmega32U6.h.
| #define OCR2A_6_REG OCR2A |
Definition at line 254 of file ATmega32U6.h.
| #define OCR2A_7_REG OCR2A |
Definition at line 255 of file ATmega32U6.h.
| #define OCR2AUB_REG ASSR |
Definition at line 444 of file ATmega32U6.h.
| #define OCR2B_0_REG OCR2B |
Definition at line 238 of file ATmega32U6.h.
| #define OCR2B_1_REG OCR2B |
Definition at line 239 of file ATmega32U6.h.
| #define OCR2B_2_REG OCR2B |
Definition at line 240 of file ATmega32U6.h.
| #define OCR2B_3_REG OCR2B |
Definition at line 241 of file ATmega32U6.h.
| #define OCR2B_4_REG OCR2B |
Definition at line 242 of file ATmega32U6.h.
| #define OCR2B_5_REG OCR2B |
Definition at line 243 of file ATmega32U6.h.
| #define OCR2B_6_REG OCR2B |
Definition at line 244 of file ATmega32U6.h.
| #define OCR2B_7_REG OCR2B |
Definition at line 245 of file ATmega32U6.h.
| #define OCR2BUB_REG ASSR |
Definition at line 443 of file ATmega32U6.h.
| #define OCR3AH0_REG OCR3AH |
Definition at line 522 of file ATmega32U6.h.
| #define OCR3AH1_REG OCR3AH |
Definition at line 523 of file ATmega32U6.h.
| #define OCR3AH2_REG OCR3AH |
Definition at line 524 of file ATmega32U6.h.
| #define OCR3AH3_REG OCR3AH |
Definition at line 525 of file ATmega32U6.h.
| #define OCR3AH4_REG OCR3AH |
Definition at line 526 of file ATmega32U6.h.
| #define OCR3AH5_REG OCR3AH |
Definition at line 527 of file ATmega32U6.h.
| #define OCR3AH6_REG OCR3AH |
Definition at line 528 of file ATmega32U6.h.
| #define OCR3AH7_REG OCR3AH |
Definition at line 529 of file ATmega32U6.h.
| #define OCR3AL0_REG OCR3AL |
Definition at line 492 of file ATmega32U6.h.
| #define OCR3AL1_REG OCR3AL |
Definition at line 493 of file ATmega32U6.h.
| #define OCR3AL2_REG OCR3AL |
Definition at line 494 of file ATmega32U6.h.
| #define OCR3AL3_REG OCR3AL |
Definition at line 495 of file ATmega32U6.h.
| #define OCR3AL4_REG OCR3AL |
Definition at line 496 of file ATmega32U6.h.
| #define OCR3AL5_REG OCR3AL |
Definition at line 497 of file ATmega32U6.h.
| #define OCR3AL6_REG OCR3AL |
Definition at line 498 of file ATmega32U6.h.
| #define OCR3AL7_REG OCR3AL |
Definition at line 499 of file ATmega32U6.h.
| #define OCR3BH0_REG OCR3BH |
Definition at line 1218 of file ATmega32U6.h.
| #define OCR3BH1_REG OCR3BH |
Definition at line 1219 of file ATmega32U6.h.
| #define OCR3BH2_REG OCR3BH |
Definition at line 1220 of file ATmega32U6.h.
| #define OCR3BH3_REG OCR3BH |
Definition at line 1221 of file ATmega32U6.h.
| #define OCR3BH4_REG OCR3BH |
Definition at line 1222 of file ATmega32U6.h.
| #define OCR3BH5_REG OCR3BH |
Definition at line 1223 of file ATmega32U6.h.
| #define OCR3BH6_REG OCR3BH |
Definition at line 1224 of file ATmega32U6.h.
| #define OCR3BH7_REG OCR3BH |
Definition at line 1225 of file ATmega32U6.h.
| #define OCR3BL0_REG OCR3BL |
Definition at line 1208 of file ATmega32U6.h.
| #define OCR3BL1_REG OCR3BL |
Definition at line 1209 of file ATmega32U6.h.
| #define OCR3BL2_REG OCR3BL |
Definition at line 1210 of file ATmega32U6.h.
| #define OCR3BL3_REG OCR3BL |
Definition at line 1211 of file ATmega32U6.h.
| #define OCR3BL4_REG OCR3BL |
Definition at line 1212 of file ATmega32U6.h.
| #define OCR3BL5_REG OCR3BL |
Definition at line 1213 of file ATmega32U6.h.
| #define OCR3BL6_REG OCR3BL |
Definition at line 1214 of file ATmega32U6.h.
| #define OCR3BL7_REG OCR3BL |
Definition at line 1215 of file ATmega32U6.h.
| #define OCR3CH0_REG OCR3CH |
Definition at line 703 of file ATmega32U6.h.
| #define OCR3CH1_REG OCR3CH |
Definition at line 704 of file ATmega32U6.h.
| #define OCR3CH2_REG OCR3CH |
Definition at line 705 of file ATmega32U6.h.
| #define OCR3CH3_REG OCR3CH |
Definition at line 706 of file ATmega32U6.h.
| #define OCR3CH4_REG OCR3CH |
Definition at line 707 of file ATmega32U6.h.
| #define OCR3CH5_REG OCR3CH |
Definition at line 708 of file ATmega32U6.h.
| #define OCR3CH6_REG OCR3CH |
Definition at line 709 of file ATmega32U6.h.
| #define OCR3CH7_REG OCR3CH |
Definition at line 710 of file ATmega32U6.h.
| #define OCR3CL0_REG OCR3CL |
Definition at line 718 of file ATmega32U6.h.
| #define OCR3CL1_REG OCR3CL |
Definition at line 719 of file ATmega32U6.h.
| #define OCR3CL2_REG OCR3CL |
Definition at line 720 of file ATmega32U6.h.
| #define OCR3CL3_REG OCR3CL |
Definition at line 721 of file ATmega32U6.h.
| #define OCR3CL4_REG OCR3CL |
Definition at line 722 of file ATmega32U6.h.
| #define OCR3CL5_REG OCR3CL |
Definition at line 723 of file ATmega32U6.h.
| #define OCR3CL6_REG OCR3CL |
Definition at line 724 of file ATmega32U6.h.
| #define OCR3CL7_REG OCR3CL |
Definition at line 725 of file ATmega32U6.h.
| #define OCROA_0_REG OCR0A |
Definition at line 1084 of file ATmega32U6.h.
| #define OCROA_1_REG OCR0A |
Definition at line 1085 of file ATmega32U6.h.
| #define OCROA_2_REG OCR0A |
Definition at line 1086 of file ATmega32U6.h.
| #define OCROA_3_REG OCR0A |
Definition at line 1087 of file ATmega32U6.h.
| #define OCROA_4_REG OCR0A |
Definition at line 1088 of file ATmega32U6.h.
| #define OCROA_5_REG OCR0A |
Definition at line 1089 of file ATmega32U6.h.
| #define OCROA_6_REG OCR0A |
Definition at line 1090 of file ATmega32U6.h.
| #define OCROA_7_REG OCR0A |
Definition at line 1091 of file ATmega32U6.h.
| #define OTGPADE_REG USBCON |
Definition at line 839 of file ATmega32U6.h.
| #define OVERFI_REG UESTA0X |
Definition at line 1174 of file ATmega32U6.h.
| #define PCIE0_REG PCICR |
Definition at line 596 of file ATmega32U6.h.
| #define PCIF0_REG PCIFR |
Definition at line 875 of file ATmega32U6.h.
| #define PCINT0_REG PCMSK0 |
Definition at line 1259 of file ATmega32U6.h.
| #define PCINT1_REG PCMSK0 |
Definition at line 1260 of file ATmega32U6.h.
| #define PCINT2_REG PCMSK0 |
Definition at line 1261 of file ATmega32U6.h.
| #define PCINT3_REG PCMSK0 |
Definition at line 1262 of file ATmega32U6.h.
| #define PCINT4_REG PCMSK0 |
Definition at line 1263 of file ATmega32U6.h.
| #define PCINT5_REG PCMSK0 |
Definition at line 1264 of file ATmega32U6.h.
| #define PCINT6_REG PCMSK0 |
Definition at line 1265 of file ATmega32U6.h.
| #define PCINT7_REG PCMSK0 |
Definition at line 1266 of file ATmega32U6.h.
| #define PGERS_REG SPMCSR |
Definition at line 1160 of file ATmega32U6.h.
| #define PGWRT_REG SPMCSR |
Definition at line 1161 of file ATmega32U6.h.
| #define PINA0_REG PINA |
Definition at line 955 of file ATmega32U6.h.
| #define PINA1_REG PINA |
Definition at line 956 of file ATmega32U6.h.
| #define PINA2_REG PINA |
Definition at line 957 of file ATmega32U6.h.
| #define PINA3_REG PINA |
Definition at line 958 of file ATmega32U6.h.
| #define PINA4_REG PINA |
Definition at line 959 of file ATmega32U6.h.
| #define PINA5_REG PINA |
Definition at line 960 of file ATmega32U6.h.
| #define PINA6_REG PINA |
Definition at line 961 of file ATmega32U6.h.
| #define PINA7_REG PINA |
Definition at line 962 of file ATmega32U6.h.
| #define PINB0_REG PINB |
Definition at line 1295 of file ATmega32U6.h.
| #define PINB1_REG PINB |
Definition at line 1296 of file ATmega32U6.h.
| #define PINB2_REG PINB |
Definition at line 1297 of file ATmega32U6.h.
| #define PINB3_REG PINB |
Definition at line 1298 of file ATmega32U6.h.
| #define PINB4_REG PINB |
Definition at line 1299 of file ATmega32U6.h.
| #define PINB5_REG PINB |
Definition at line 1300 of file ATmega32U6.h.
| #define PINB6_REG PINB |
Definition at line 1301 of file ATmega32U6.h.
| #define PINB7_REG PINB |
Definition at line 1302 of file ATmega32U6.h.
| #define PINC0_REG PINC |
Definition at line 1285 of file ATmega32U6.h.
| #define PINC1_REG PINC |
Definition at line 1286 of file ATmega32U6.h.
| #define PINC2_REG PINC |
Definition at line 1287 of file ATmega32U6.h.
| #define PINC3_REG PINC |
Definition at line 1288 of file ATmega32U6.h.
| #define PINC4_REG PINC |
Definition at line 1289 of file ATmega32U6.h.
| #define PINC5_REG PINC |
Definition at line 1290 of file ATmega32U6.h.
| #define PINC6_REG PINC |
Definition at line 1291 of file ATmega32U6.h.
| #define PINC7_REG PINC |
Definition at line 1292 of file ATmega32U6.h.
| #define PIND0_REG PIND |
Definition at line 1335 of file ATmega32U6.h.
| #define PIND1_REG PIND |
Definition at line 1336 of file ATmega32U6.h.
| #define PIND2_REG PIND |
Definition at line 1337 of file ATmega32U6.h.
| #define PIND3_REG PIND |
Definition at line 1338 of file ATmega32U6.h.
| #define PIND4_REG PIND |
Definition at line 1339 of file ATmega32U6.h.
| #define PIND5_REG PIND |
Definition at line 1340 of file ATmega32U6.h.
| #define PIND6_REG PIND |
Definition at line 1341 of file ATmega32U6.h.
| #define PIND7_REG PIND |
Definition at line 1342 of file ATmega32U6.h.
| #define PINE0_REG PINE |
Definition at line 1325 of file ATmega32U6.h.
| #define PINE1_REG PINE |
Definition at line 1326 of file ATmega32U6.h.
| #define PINE2_REG PINE |
Definition at line 1327 of file ATmega32U6.h.
| #define PINE3_REG PINE |
Definition at line 1328 of file ATmega32U6.h.
| #define PINE4_REG PINE |
Definition at line 1329 of file ATmega32U6.h.
| #define PINE5_REG PINE |
Definition at line 1330 of file ATmega32U6.h.
| #define PINE6_REG PINE |
Definition at line 1331 of file ATmega32U6.h.
| #define PINE7_REG PINE |
Definition at line 1332 of file ATmega32U6.h.
| #define PINF0_REG PINF |
Definition at line 1315 of file ATmega32U6.h.
| #define PINF1_REG PINF |
Definition at line 1316 of file ATmega32U6.h.
| #define PINF2_REG PINF |
Definition at line 1317 of file ATmega32U6.h.
| #define PINF3_REG PINF |
Definition at line 1318 of file ATmega32U6.h.
| #define PINF4_REG PINF |
Definition at line 1319 of file ATmega32U6.h.
| #define PINF5_REG PINF |
Definition at line 1320 of file ATmega32U6.h.
| #define PINF6_REG PINF |
Definition at line 1321 of file ATmega32U6.h.
| #define PINF7_REG PINF |
Definition at line 1322 of file ATmega32U6.h.
| #define PLLE_REG PLLCSR |
Definition at line 1253 of file ATmega32U6.h.
| #define PLLP0_REG PLLCSR |
Definition at line 1254 of file ATmega32U6.h.
| #define PLLP1_REG PLLCSR |
Definition at line 1255 of file ATmega32U6.h.
| #define PLLP2_REG PLLCSR |
Definition at line 1256 of file ATmega32U6.h.
| #define PLOCK_REG PLLCSR |
Definition at line 1252 of file ATmega32U6.h.
| #define PORF_REG MCUSR |
Definition at line 846 of file ATmega32U6.h.
| #define PORTA0_REG PORTA |
Definition at line 352 of file ATmega32U6.h.
| #define PORTA1_REG PORTA |
Definition at line 353 of file ATmega32U6.h.
| #define PORTA2_REG PORTA |
Definition at line 354 of file ATmega32U6.h.
| #define PORTA3_REG PORTA |
Definition at line 355 of file ATmega32U6.h.
| #define PORTA4_REG PORTA |
Definition at line 356 of file ATmega32U6.h.
| #define PORTA5_REG PORTA |
Definition at line 357 of file ATmega32U6.h.
| #define PORTA6_REG PORTA |
Definition at line 358 of file ATmega32U6.h.
| #define PORTA7_REG PORTA |
Definition at line 359 of file ATmega32U6.h.
| #define PORTB0_REG PORTB |
Definition at line 1178 of file ATmega32U6.h.
| #define PORTB1_REG PORTB |
Definition at line 1179 of file ATmega32U6.h.
| #define PORTB2_REG PORTB |
Definition at line 1180 of file ATmega32U6.h.
| #define PORTB3_REG PORTB |
Definition at line 1181 of file ATmega32U6.h.
| #define PORTB4_REG PORTB |
Definition at line 1182 of file ATmega32U6.h.
| #define PORTB5_REG PORTB |
Definition at line 1183 of file ATmega32U6.h.
| #define PORTB6_REG PORTB |
Definition at line 1184 of file ATmega32U6.h.
| #define PORTB7_REG PORTB |
Definition at line 1185 of file ATmega32U6.h.
| #define PORTC0_REG PORTC |
Definition at line 342 of file ATmega32U6.h.
| #define PORTC1_REG PORTC |
Definition at line 343 of file ATmega32U6.h.
| #define PORTC2_REG PORTC |
Definition at line 344 of file ATmega32U6.h.
| #define PORTC3_REG PORTC |
Definition at line 345 of file ATmega32U6.h.
| #define PORTC4_REG PORTC |
Definition at line 346 of file ATmega32U6.h.
| #define PORTC5_REG PORTC |
Definition at line 347 of file ATmega32U6.h.
| #define PORTC6_REG PORTC |
Definition at line 348 of file ATmega32U6.h.
| #define PORTC7_REG PORTC |
Definition at line 349 of file ATmega32U6.h.
| #define PORTD0_REG PORTD |
Definition at line 312 of file ATmega32U6.h.
| #define PORTD1_REG PORTD |
Definition at line 313 of file ATmega32U6.h.
| #define PORTD2_REG PORTD |
Definition at line 314 of file ATmega32U6.h.
| #define PORTD3_REG PORTD |
Definition at line 315 of file ATmega32U6.h.
| #define PORTD4_REG PORTD |
Definition at line 316 of file ATmega32U6.h.
| #define PORTD5_REG PORTD |
Definition at line 317 of file ATmega32U6.h.
| #define PORTD6_REG PORTD |
Definition at line 318 of file ATmega32U6.h.
| #define PORTD7_REG PORTD |
Definition at line 319 of file ATmega32U6.h.
| #define PORTE0_REG PORTE |
Definition at line 322 of file ATmega32U6.h.
| #define PORTE1_REG PORTE |
Definition at line 323 of file ATmega32U6.h.
| #define PORTE2_REG PORTE |
Definition at line 324 of file ATmega32U6.h.
| #define PORTE3_REG PORTE |
Definition at line 325 of file ATmega32U6.h.
| #define PORTE4_REG PORTE |
Definition at line 326 of file ATmega32U6.h.
| #define PORTE5_REG PORTE |
Definition at line 327 of file ATmega32U6.h.
| #define PORTE6_REG PORTE |
Definition at line 328 of file ATmega32U6.h.
| #define PORTE7_REG PORTE |
Definition at line 329 of file ATmega32U6.h.
| #define PORTF0_REG PORTF |
Definition at line 1104 of file ATmega32U6.h.
| #define PORTF1_REG PORTF |
Definition at line 1105 of file ATmega32U6.h.
| #define PORTF2_REG PORTF |
Definition at line 1106 of file ATmega32U6.h.
| #define PORTF3_REG PORTF |
Definition at line 1107 of file ATmega32U6.h.
| #define PORTF4_REG PORTF |
Definition at line 1108 of file ATmega32U6.h.
| #define PORTF5_REG PORTF |
Definition at line 1109 of file ATmega32U6.h.
| #define PORTF6_REG PORTF |
Definition at line 1110 of file ATmega32U6.h.
| #define PORTF7_REG PORTF |
Definition at line 1111 of file ATmega32U6.h.
| #define PRADC_REG PRR0 |
Definition at line 1070 of file ATmega32U6.h.
| #define PRSPI_REG PRR0 |
Definition at line 1071 of file ATmega32U6.h.
| #define PRTIM0_REG PRR0 |
Definition at line 1073 of file ATmega32U6.h.
| #define PRTIM1_REG PRR0 |
Definition at line 1072 of file ATmega32U6.h.
| #define PRTIM2_REG PRR0 |
Definition at line 1074 of file ATmega32U6.h.
| #define PRTIM3_REG PRR1 |
Definition at line 1371 of file ATmega32U6.h.
| #define PRTWI_REG PRR0 |
Definition at line 1075 of file ATmega32U6.h.
| #define PRUSART1_REG PRR1 |
Definition at line 1370 of file ATmega32U6.h.
| #define PRUSB_REG PRR1 |
Definition at line 1372 of file ATmega32U6.h.
| #define PSRASY_REG GTCCR |
Definition at line 730 of file ATmega32U6.h.
| #define PSRSYNC_REG GTCCR |
Definition at line 728 of file ATmega32U6.h.
| #define PUD_REG MCUCR |
Definition at line 922 of file ATmega32U6.h.
| #define PWM0A_NUM 0 |
Definition at line 141 of file ATmega32U6.h.
| #define PWM0B_NUM 1 |
Definition at line 142 of file ATmega32U6.h.
| #define PWM1A_NUM 2 |
Definition at line 143 of file ATmega32U6.h.
| #define PWM1B_NUM 3 |
Definition at line 144 of file ATmega32U6.h.
| #define PWM1C_NUM 4 |
Definition at line 145 of file ATmega32U6.h.
| #define PWM2A_NUM 5 |
Definition at line 146 of file ATmega32U6.h.
| #define PWM2B_NUM 6 |
Definition at line 147 of file ATmega32U6.h.
| #define PWM3A_NUM 7 |
Definition at line 148 of file ATmega32U6.h.
| #define PWM3B_NUM 8 |
Definition at line 149 of file ATmega32U6.h.
| #define PWM3C_NUM 9 |
Definition at line 150 of file ATmega32U6.h.
| #define PWM_TOTAL_NUM 10 |
Definition at line 151 of file ATmega32U6.h.
| #define REFS0_REG ADMUX |
Definition at line 171 of file ATmega32U6.h.
| #define REFS1_REG ADMUX |
Definition at line 172 of file ATmega32U6.h.
| #define RMWKUP_REG UDCON |
Definition at line 592 of file ATmega32U6.h.
| #define RSTDT_REG UECONX |
Definition at line 895 of file ATmega32U6.h.
| #define RWAL_REG UEINTX |
Definition at line 782 of file ATmega32U6.h.
| #define RWWSB_REG SPMCSR |
Definition at line 1165 of file ATmega32U6.h.
| #define RWWSRE_REG SPMCSR |
Definition at line 1163 of file ATmega32U6.h.
| #define RXB81_REG UCSR1B |
Definition at line 980 of file ATmega32U6.h.
| #define RXC1_REG UCSR1A |
Definition at line 1006 of file ATmega32U6.h.
| #define RXCIE1_REG UCSR1B |
Definition at line 986 of file ATmega32U6.h.
| #define RXEN1_REG UCSR1B |
Definition at line 983 of file ATmega32U6.h.
| #define RXOUTE_REG UEIENX |
Definition at line 972 of file ATmega32U6.h.
| #define RXOUTI_REG UEINTX |
Definition at line 779 of file ATmega32U6.h.
| #define RXSTPE_REG UEIENX |
Definition at line 973 of file ATmega32U6.h.
| #define RXSTPI_REG UEINTX |
Definition at line 780 of file ATmega32U6.h.
| #define S_REG SREG |
Definition at line 461 of file ATmega32U6.h.
| #define SE_REG SMCR |
Definition at line 860 of file ATmega32U6.h.
| #define SIG_INPUT_CAPTURE1_NUM 0 |
Definition at line 154 of file ATmega32U6.h.
| #define SIG_INPUT_CAPTURE3_NUM 1 |
Definition at line 155 of file ATmega32U6.h.
| #define SIG_INPUT_CAPTURE_TOTAL_NUM 2 |
Definition at line 156 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE0A_NUM 0 |
Definition at line 128 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE0B_NUM 1 |
Definition at line 129 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE1A_NUM 2 |
Definition at line 130 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE1B_NUM 3 |
Definition at line 131 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE1C_NUM 4 |
Definition at line 132 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE2A_NUM 5 |
Definition at line 133 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE2B_NUM 6 |
Definition at line 134 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE3A_NUM 7 |
Definition at line 135 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE3B_NUM 8 |
Definition at line 136 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE3C_NUM 9 |
Definition at line 137 of file ATmega32U6.h.
| #define SIG_OUTPUT_COMPARE_TOTAL_NUM 10 |
Definition at line 138 of file ATmega32U6.h.
| #define SIG_OVERFLOW0_NUM 0 |
Definition at line 121 of file ATmega32U6.h.
| #define SIG_OVERFLOW1_NUM 1 |
Definition at line 122 of file ATmega32U6.h.
| #define SIG_OVERFLOW2_NUM 2 |
Definition at line 123 of file ATmega32U6.h.
| #define SIG_OVERFLOW3_NUM 3 |
Definition at line 124 of file ATmega32U6.h.
| #define SIG_OVERFLOW_TOTAL_NUM 4 |
Definition at line 125 of file ATmega32U6.h.
| #define SIGRD_REG SPMCSR |
Definition at line 1164 of file ATmega32U6.h.
| #define SM0_REG SMCR |
Definition at line 861 of file ATmega32U6.h.
| #define SM1_REG SMCR |
Definition at line 862 of file ATmega32U6.h.
| #define SM2_REG SMCR |
Definition at line 863 of file ATmega32U6.h.
| #define SOFE_REG UDIEN |
Definition at line 176 of file ATmega32U6.h.
| #define SOFI_REG UDINT |
Definition at line 214 of file ATmega32U6.h.
| #define SP0_REG SPL |
Definition at line 827 of file ATmega32U6.h.
| #define SP10_REG SPH |
Definition at line 745 of file ATmega32U6.h.
| #define SP11_REG SPH |
Definition at line 746 of file ATmega32U6.h.
| #define SP12_REG SPH |
Definition at line 747 of file ATmega32U6.h.
| #define SP13_REG SPH |
Definition at line 748 of file ATmega32U6.h.
| #define SP14_REG SPH |
Definition at line 749 of file ATmega32U6.h.
| #define SP15_REG SPH |
Definition at line 750 of file ATmega32U6.h.
| #define SP1_REG SPL |
Definition at line 828 of file ATmega32U6.h.
| #define SP2_REG SPL |
Definition at line 829 of file ATmega32U6.h.
| #define SP3_REG SPL |
Definition at line 830 of file ATmega32U6.h.
| #define SP4_REG SPL |
Definition at line 831 of file ATmega32U6.h.
| #define SP5_REG SPL |
Definition at line 832 of file ATmega32U6.h.
| #define SP6_REG SPL |
Definition at line 833 of file ATmega32U6.h.
| #define SP7_REG SPL |
Definition at line 834 of file ATmega32U6.h.
| #define SP8_REG SPH |
Definition at line 743 of file ATmega32U6.h.
| #define SP9_REG SPH |
Definition at line 744 of file ATmega32U6.h.
| #define SPDR0_REG SPDR |
Definition at line 258 of file ATmega32U6.h.
| #define SPDR1_REG SPDR |
Definition at line 259 of file ATmega32U6.h.
| #define SPDR2_REG SPDR |
Definition at line 260 of file ATmega32U6.h.
| #define SPDR3_REG SPDR |
Definition at line 261 of file ATmega32U6.h.
| #define SPDR4_REG SPDR |
Definition at line 262 of file ATmega32U6.h.
| #define SPDR5_REG SPDR |
Definition at line 263 of file ATmega32U6.h.
| #define SPDR6_REG SPDR |
Definition at line 264 of file ATmega32U6.h.
| #define SPDR7_REG SPDR |
Definition at line 265 of file ATmega32U6.h.
| #define SPE_REG SPCR |
Definition at line 676 of file ATmega32U6.h.
| #define SPEED_REG USBSTA |
Definition at line 967 of file ATmega32U6.h.
| #define SPI2X_REG SPSR |
Definition at line 268 of file ATmega32U6.h.
| #define SPIE_REG SPCR |
Definition at line 677 of file ATmega32U6.h.
| #define SPIF_REG SPSR |
Definition at line 270 of file ATmega32U6.h.
| #define SPMEN_REG SPMCSR |
Definition at line 1159 of file ATmega32U6.h.
| #define SPMIE_REG SPMCSR |
Definition at line 1166 of file ATmega32U6.h.
| #define SPR0_REG SPCR |
Definition at line 670 of file ATmega32U6.h.
| #define SPR1_REG SPCR |
Definition at line 671 of file ATmega32U6.h.
| #define SRE_REG XMCRA |
Definition at line 1282 of file ATmega32U6.h.
| #define SRL0_REG XMCRA |
Definition at line 1279 of file ATmega32U6.h.
| #define SRL1_REG XMCRA |
Definition at line 1280 of file ATmega32U6.h.
| #define SRL2_REG XMCRA |
Definition at line 1281 of file ATmega32U6.h.
| #define SRW00_REG XMCRA |
Definition at line 1275 of file ATmega32U6.h.
| #define SRW01_REG XMCRA |
Definition at line 1276 of file ATmega32U6.h.
| #define SRW10_REG XMCRA |
Definition at line 1277 of file ATmega32U6.h.
| #define SRW11_REG XMCRA |
Definition at line 1278 of file ATmega32U6.h.
| #define STALLEDE_REG UEIENX |
Definition at line 971 of file ATmega32U6.h.
| #define STALLEDI_REG UEINTX |
Definition at line 778 of file ATmega32U6.h.
| #define STALLRQ_REG UECONX |
Definition at line 897 of file ATmega32U6.h.
| #define STALLRQC_REG UECONX |
Definition at line 896 of file ATmega32U6.h.
| #define SUSPE_REG UDIEN |
Definition at line 175 of file ATmega32U6.h.
| #define SUSPI_REG UDINT |
Definition at line 213 of file ATmega32U6.h.
| #define T_REG SREG |
Definition at line 463 of file ATmega32U6.h.
| #define TCN2UB_REG ASSR |
Definition at line 445 of file ATmega32U6.h.
| #define TCNT0_0_REG TCNT0 |
Definition at line 613 of file ATmega32U6.h.
| #define TCNT0_1_REG TCNT0 |
Definition at line 614 of file ATmega32U6.h.
| #define TCNT0_2_REG TCNT0 |
Definition at line 615 of file ATmega32U6.h.
| #define TCNT0_3_REG TCNT0 |
Definition at line 616 of file ATmega32U6.h.
| #define TCNT0_4_REG TCNT0 |
Definition at line 617 of file ATmega32U6.h.
| #define TCNT0_5_REG TCNT0 |
Definition at line 618 of file ATmega32U6.h.
| #define TCNT0_6_REG TCNT0 |
Definition at line 619 of file ATmega32U6.h.
| #define TCNT0_7_REG TCNT0 |
Definition at line 620 of file ATmega32U6.h.
| #define TCNT1H0_REG TCNT1H |
Definition at line 332 of file ATmega32U6.h.
| #define TCNT1H1_REG TCNT1H |
Definition at line 333 of file ATmega32U6.h.
| #define TCNT1H2_REG TCNT1H |
Definition at line 334 of file ATmega32U6.h.
| #define TCNT1H3_REG TCNT1H |
Definition at line 335 of file ATmega32U6.h.
| #define TCNT1H4_REG TCNT1H |
Definition at line 336 of file ATmega32U6.h.
| #define TCNT1H5_REG TCNT1H |
Definition at line 337 of file ATmega32U6.h.
| #define TCNT1H6_REG TCNT1H |
Definition at line 338 of file ATmega32U6.h.
| #define TCNT1H7_REG TCNT1H |
Definition at line 339 of file ATmega32U6.h.
| #define TCNT1L0_REG TCNT1L |
Definition at line 302 of file ATmega32U6.h.
| #define TCNT1L1_REG TCNT1L |
Definition at line 303 of file ATmega32U6.h.
| #define TCNT1L2_REG TCNT1L |
Definition at line 304 of file ATmega32U6.h.
| #define TCNT1L3_REG TCNT1L |
Definition at line 305 of file ATmega32U6.h.
| #define TCNT1L4_REG TCNT1L |
Definition at line 306 of file ATmega32U6.h.
| #define TCNT1L5_REG TCNT1L |
Definition at line 307 of file ATmega32U6.h.
| #define TCNT1L6_REG TCNT1L |
Definition at line 308 of file ATmega32U6.h.
| #define TCNT1L7_REG TCNT1L |
Definition at line 309 of file ATmega32U6.h.
| #define TCNT2_0_REG TCNT2 |
Definition at line 603 of file ATmega32U6.h.
| #define TCNT2_1_REG TCNT2 |
Definition at line 604 of file ATmega32U6.h.
| #define TCNT2_2_REG TCNT2 |
Definition at line 605 of file ATmega32U6.h.
| #define TCNT2_3_REG TCNT2 |
Definition at line 606 of file ATmega32U6.h.
| #define TCNT2_4_REG TCNT2 |
Definition at line 607 of file ATmega32U6.h.
| #define TCNT2_5_REG TCNT2 |
Definition at line 608 of file ATmega32U6.h.
| #define TCNT2_6_REG TCNT2 |
Definition at line 609 of file ATmega32U6.h.
| #define TCNT2_7_REG TCNT2 |
Definition at line 610 of file ATmega32U6.h.
| #define TCNT3H0_REG TCNT3H |
Definition at line 797 of file ATmega32U6.h.
| #define TCNT3H1_REG TCNT3H |
Definition at line 798 of file ATmega32U6.h.
| #define TCNT3H2_REG TCNT3H |
Definition at line 799 of file ATmega32U6.h.
| #define TCNT3H3_REG TCNT3H |
Definition at line 800 of file ATmega32U6.h.
| #define TCNT3H4_REG TCNT3H |
Definition at line 801 of file ATmega32U6.h.
| #define TCNT3H5_REG TCNT3H |
Definition at line 802 of file ATmega32U6.h.
| #define TCNT3H6_REG TCNT3H |
Definition at line 803 of file ATmega32U6.h.
| #define TCNT3H7_REG TCNT3H |
Definition at line 804 of file ATmega32U6.h.
| #define TCNT3L0_REG TCNT3L |
Definition at line 817 of file ATmega32U6.h.
| #define TCNT3L1_REG TCNT3L |
Definition at line 818 of file ATmega32U6.h.
| #define TCNT3L2_REG TCNT3L |
Definition at line 819 of file ATmega32U6.h.
| #define TCNT3L3_REG TCNT3L |
Definition at line 820 of file ATmega32U6.h.
| #define TCNT3L4_REG TCNT3L |
Definition at line 821 of file ATmega32U6.h.
| #define TCNT3L5_REG TCNT3L |
Definition at line 822 of file ATmega32U6.h.
| #define TCNT3L6_REG TCNT3L |
Definition at line 823 of file ATmega32U6.h.
| #define TCNT3L7_REG TCNT3L |
Definition at line 824 of file ATmega32U6.h.
| #define TCR2AUB_REG ASSR |
Definition at line 442 of file ATmega32U6.h.
| #define TCR2BUB_REG ASSR |
Definition at line 441 of file ATmega32U6.h.
| #define TIMER0_AVAILABLE |
Definition at line 105 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_0 0 |
Definition at line 28 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_1 1 |
Definition at line 29 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_1024 5 |
Definition at line 33 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_256 4 |
Definition at line 32 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_64 3 |
Definition at line 31 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_8 2 |
Definition at line 30 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_FALL 6 |
Definition at line 34 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_DIV_RISE 7 |
Definition at line 35 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_0 0 |
Definition at line 37 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_1 1 |
Definition at line 38 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_2 8 |
Definition at line 39 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_3 64 |
Definition at line 40 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_4 256 |
Definition at line 41 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_5 1024 |
Definition at line 42 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_6 -1 |
Definition at line 43 of file ATmega32U6.h.
| #define TIMER0_PRESCALER_REG_7 -2 |
Definition at line 44 of file ATmega32U6.h.
| #define TIMER0A_AVAILABLE |
Definition at line 106 of file ATmega32U6.h.
| #define TIMER0B_AVAILABLE |
Definition at line 107 of file ATmega32U6.h.
| #define TIMER1_AVAILABLE |
Definition at line 108 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_0 0 |
Definition at line 47 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_1 1 |
Definition at line 48 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_1024 5 |
Definition at line 52 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_256 4 |
Definition at line 51 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_64 3 |
Definition at line 50 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_8 2 |
Definition at line 49 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_FALL 6 |
Definition at line 53 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_DIV_RISE 7 |
Definition at line 54 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_0 0 |
Definition at line 56 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_1 1 |
Definition at line 57 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_2 8 |
Definition at line 58 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_3 64 |
Definition at line 59 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_4 256 |
Definition at line 60 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_5 1024 |
Definition at line 61 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_6 -1 |
Definition at line 62 of file ATmega32U6.h.
| #define TIMER1_PRESCALER_REG_7 -2 |
Definition at line 63 of file ATmega32U6.h.
| #define TIMER1A_AVAILABLE |
Definition at line 109 of file ATmega32U6.h.
| #define TIMER1B_AVAILABLE |
Definition at line 110 of file ATmega32U6.h.
| #define TIMER1C_AVAILABLE |
Definition at line 111 of file ATmega32U6.h.
| #define TIMER2_AVAILABLE |
Definition at line 112 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_0 0 |
Definition at line 66 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_1 1 |
Definition at line 67 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_1024 7 |
Definition at line 73 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_128 5 |
Definition at line 71 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_256 6 |
Definition at line 72 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_32 3 |
Definition at line 69 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_64 4 |
Definition at line 70 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_DIV_8 2 |
Definition at line 68 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_0 0 |
Definition at line 75 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_1 1 |
Definition at line 76 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_2 8 |
Definition at line 77 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_3 32 |
Definition at line 78 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_4 64 |
Definition at line 79 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_5 128 |
Definition at line 80 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_6 256 |
Definition at line 81 of file ATmega32U6.h.
| #define TIMER2_PRESCALER_REG_7 1024 |
Definition at line 82 of file ATmega32U6.h.
| #define TIMER2A_AVAILABLE |
Definition at line 113 of file ATmega32U6.h.
| #define TIMER2B_AVAILABLE |
Definition at line 114 of file ATmega32U6.h.
| #define TIMER3_AVAILABLE |
Definition at line 115 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_0 0 |
Definition at line 85 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_1 1 |
Definition at line 86 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_1024 5 |
Definition at line 90 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_256 4 |
Definition at line 89 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_64 3 |
Definition at line 88 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_8 2 |
Definition at line 87 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_FALL 6 |
Definition at line 91 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_DIV_RISE 7 |
Definition at line 92 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_0 0 |
Definition at line 94 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_1 1 |
Definition at line 95 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_2 8 |
Definition at line 96 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_3 64 |
Definition at line 97 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_4 256 |
Definition at line 98 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_5 1024 |
Definition at line 99 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_6 -1 |
Definition at line 100 of file ATmega32U6.h.
| #define TIMER3_PRESCALER_REG_7 -2 |
Definition at line 101 of file ATmega32U6.h.
| #define TIMER3A_AVAILABLE |
Definition at line 116 of file ATmega32U6.h.
| #define TIMER3B_AVAILABLE |
Definition at line 117 of file ATmega32U6.h.
| #define TIMER3C_AVAILABLE |
Definition at line 118 of file ATmega32U6.h.
| #define TOIE0_REG TIMSK0 |
Definition at line 1240 of file ATmega32U6.h.
| #define TOIE1_REG TIMSK1 |
Definition at line 1245 of file ATmega32U6.h.
| #define TOIE2_REG TIMSK2 |
Definition at line 1228 of file ATmega32U6.h.
| #define TOIE3_REG TIMSK3 |
Definition at line 1233 of file ATmega32U6.h.
| #define TOV0_REG TIFR0 |
Definition at line 1365 of file ATmega32U6.h.
| #define TOV1_REG TIFR1 |
Definition at line 680 of file ATmega32U6.h.
| #define TOV2_REG TIFR2 |
Definition at line 658 of file ATmega32U6.h.
| #define TOV3_REG TIFR3 |
Definition at line 663 of file ATmega32U6.h.
| #define TSM_REG GTCCR |
Definition at line 729 of file ATmega32U6.h.
| #define TWA0_REG TWAR |
Definition at line 624 of file ATmega32U6.h.
| #define TWA1_REG TWAR |
Definition at line 625 of file ATmega32U6.h.
| #define TWA2_REG TWAR |
Definition at line 626 of file ATmega32U6.h.
| #define TWA3_REG TWAR |
Definition at line 627 of file ATmega32U6.h.
| #define TWA4_REG TWAR |
Definition at line 628 of file ATmega32U6.h.
| #define TWA5_REG TWAR |
Definition at line 629 of file ATmega32U6.h.
| #define TWA6_REG TWAR |
Definition at line 630 of file ATmega32U6.h.
| #define TWAM0_REG TWAMR |
Definition at line 1044 of file ATmega32U6.h.
| #define TWAM1_REG TWAMR |
Definition at line 1045 of file ATmega32U6.h.
| #define TWAM2_REG TWAMR |
Definition at line 1046 of file ATmega32U6.h.
| #define TWAM3_REG TWAMR |
Definition at line 1047 of file ATmega32U6.h.
| #define TWAM4_REG TWAMR |
Definition at line 1048 of file ATmega32U6.h.
| #define TWAM5_REG TWAMR |
Definition at line 1049 of file ATmega32U6.h.
| #define TWAM6_REG TWAMR |
Definition at line 1050 of file ATmega32U6.h.
| #define TWBR0_REG TWBR |
Definition at line 733 of file ATmega32U6.h.
| #define TWBR1_REG TWBR |
Definition at line 734 of file ATmega32U6.h.
| #define TWBR2_REG TWBR |
Definition at line 735 of file ATmega32U6.h.
| #define TWBR3_REG TWBR |
Definition at line 736 of file ATmega32U6.h.
| #define TWBR4_REG TWBR |
Definition at line 737 of file ATmega32U6.h.
| #define TWBR5_REG TWBR |
Definition at line 738 of file ATmega32U6.h.
| #define TWBR6_REG TWBR |
Definition at line 739 of file ATmega32U6.h.
| #define TWBR7_REG TWBR |
Definition at line 740 of file ATmega32U6.h.
| #define TWD0_REG TWDR |
Definition at line 1029 of file ATmega32U6.h.
| #define TWD1_REG TWDR |
Definition at line 1030 of file ATmega32U6.h.
| #define TWD2_REG TWDR |
Definition at line 1031 of file ATmega32U6.h.
| #define TWD3_REG TWDR |
Definition at line 1032 of file ATmega32U6.h.
| #define TWD4_REG TWDR |
Definition at line 1033 of file ATmega32U6.h.
| #define TWD5_REG TWDR |
Definition at line 1034 of file ATmega32U6.h.
| #define TWD6_REG TWDR |
Definition at line 1035 of file ATmega32U6.h.
| #define TWD7_REG TWDR |
Definition at line 1036 of file ATmega32U6.h.
| #define TWEA_REG TWCR |
Definition at line 871 of file ATmega32U6.h.
| #define TWEN_REG TWCR |
Definition at line 867 of file ATmega32U6.h.
| #define TWGCE_REG TWAR |
Definition at line 623 of file ATmega32U6.h.
| #define TWIE_REG TWCR |
Definition at line 866 of file ATmega32U6.h.
| #define TWINT_REG TWCR |
Definition at line 872 of file ATmega32U6.h.
| #define TWPS0_REG TWSR |
Definition at line 900 of file ATmega32U6.h.
| #define TWPS1_REG TWSR |
Definition at line 901 of file ATmega32U6.h.
| #define TWS3_REG TWSR |
Definition at line 902 of file ATmega32U6.h.
| #define TWS4_REG TWSR |
Definition at line 903 of file ATmega32U6.h.
| #define TWS5_REG TWSR |
Definition at line 904 of file ATmega32U6.h.
| #define TWS6_REG TWSR |
Definition at line 905 of file ATmega32U6.h.
| #define TWS7_REG TWSR |
Definition at line 906 of file ATmega32U6.h.
| #define TWSTA_REG TWCR |
Definition at line 870 of file ATmega32U6.h.
| #define TWSTO_REG TWCR |
Definition at line 869 of file ATmega32U6.h.
| #define TWWC_REG TWCR |
Definition at line 868 of file ATmega32U6.h.
| #define TXB81_REG UCSR1B |
Definition at line 979 of file ATmega32U6.h.
| #define TXC1_REG UCSR1A |
Definition at line 1005 of file ATmega32U6.h.
| #define TXCIE1_REG UCSR1B |
Definition at line 985 of file ATmega32U6.h.
| #define TXEN1_REG UCSR1B |
Definition at line 982 of file ATmega32U6.h.
| #define TXINE_REG UEIENX |
Definition at line 970 of file ATmega32U6.h.
| #define TXINI_REG UEINTX |
Definition at line 777 of file ATmega32U6.h.
| #define U2X1_REG UCSR1A |
Definition at line 1000 of file ATmega32U6.h.
| #define UADD0_REG UDADDR |
Definition at line 1139 of file ATmega32U6.h.
| #define UADD1_REG UDADDR |
Definition at line 1140 of file ATmega32U6.h.
| #define UADD2_REG UDADDR |
Definition at line 1141 of file ATmega32U6.h.
| #define UADD3_REG UDADDR |
Definition at line 1142 of file ATmega32U6.h.
| #define UADD4_REG UDADDR |
Definition at line 1143 of file ATmega32U6.h.
| #define UADD5_REG UDADDR |
Definition at line 1144 of file ATmega32U6.h.
| #define UADD6_REG UDADDR |
Definition at line 1145 of file ATmega32U6.h.
| #define UBRR_0_REG UBRR1L |
Definition at line 472 of file ATmega32U6.h.
| #define UBRR_10_REG UBRR1H |
Definition at line 1080 of file ATmega32U6.h.
| #define UBRR_11_REG UBRR1H |
Definition at line 1081 of file ATmega32U6.h.
| #define UBRR_1_REG UBRR1L |
Definition at line 473 of file ATmega32U6.h.
| #define UBRR_2_REG UBRR1L |
Definition at line 474 of file ATmega32U6.h.
| #define UBRR_3_REG UBRR1L |
Definition at line 475 of file ATmega32U6.h.
| #define UBRR_4_REG UBRR1L |
Definition at line 476 of file ATmega32U6.h.
| #define UBRR_5_REG UBRR1L |
Definition at line 477 of file ATmega32U6.h.
| #define UBRR_6_REG UBRR1L |
Definition at line 478 of file ATmega32U6.h.
| #define UBRR_7_REG UBRR1L |
Definition at line 479 of file ATmega32U6.h.
| #define UBRR_8_REG UBRR1H |
Definition at line 1078 of file ATmega32U6.h.
| #define UBRR_9_REG UBRR1H |
Definition at line 1079 of file ATmega32U6.h.
| #define UCPOL1_REG UCSR1C |
Definition at line 989 of file ATmega32U6.h.
| #define UCSZ10_REG UCSR1C |
Definition at line 990 of file ATmega32U6.h.
| #define UCSZ11_REG UCSR1C |
Definition at line 991 of file ATmega32U6.h.
| #define UCSZ12_REG UCSR1B |
Definition at line 981 of file ATmega32U6.h.
| #define UDFNUMH_0_REG UDFNUMH |
Definition at line 1039 of file ATmega32U6.h.
| #define UDFNUMH_1_REG UDFNUMH |
Definition at line 1040 of file ATmega32U6.h.
| #define UDFNUMH_2_REG UDFNUMH |
Definition at line 1041 of file ATmega32U6.h.
| #define UDFNUML_0_REG UDFNUML |
Definition at line 1019 of file ATmega32U6.h.
| #define UDFNUML_1_REG UDFNUML |
Definition at line 1020 of file ATmega32U6.h.
| #define UDFNUML_2_REG UDFNUML |
Definition at line 1021 of file ATmega32U6.h.
| #define UDFNUML_3_REG UDFNUML |
Definition at line 1022 of file ATmega32U6.h.
| #define UDFNUML_4_REG UDFNUML |
Definition at line 1023 of file ATmega32U6.h.
| #define UDFNUML_5_REG UDFNUML |
Definition at line 1024 of file ATmega32U6.h.
| #define UDFNUML_6_REG UDFNUML |
Definition at line 1025 of file ATmega32U6.h.
| #define UDFNUML_7_REG UDFNUML |
Definition at line 1026 of file ATmega32U6.h.
| #define UDR1_0_REG UDR1 |
Definition at line 372 of file ATmega32U6.h.
| #define UDR1_1_REG UDR1 |
Definition at line 373 of file ATmega32U6.h.
| #define UDR1_2_REG UDR1 |
Definition at line 374 of file ATmega32U6.h.
| #define UDR1_3_REG UDR1 |
Definition at line 375 of file ATmega32U6.h.
| #define UDR1_4_REG UDR1 |
Definition at line 376 of file ATmega32U6.h.
| #define UDR1_5_REG UDR1 |
Definition at line 377 of file ATmega32U6.h.
| #define UDR1_6_REG UDR1 |
Definition at line 378 of file ATmega32U6.h.
| #define UDR1_7_REG UDR1 |
Definition at line 379 of file ATmega32U6.h.
| #define UDRE1_REG UCSR1A |
Definition at line 1004 of file ATmega32U6.h.
| #define UDRIE1_REG UCSR1B |
Definition at line 984 of file ATmega32U6.h.
| #define UEBCHX_0_REG UEBCHX |
Definition at line 160 of file ATmega32U6.h.
| #define UEBCHX_1_REG UEBCHX |
Definition at line 161 of file ATmega32U6.h.
| #define UEBCHX_2_REG UEBCHX |
Definition at line 162 of file ATmega32U6.h.
| #define UEBCLX_0_REG UEBCLX |
Definition at line 693 of file ATmega32U6.h.
| #define UEBCLX_1_REG UEBCLX |
Definition at line 694 of file ATmega32U6.h.
| #define UEBCLX_2_REG UEBCLX |
Definition at line 695 of file ATmega32U6.h.
| #define UEBCLX_3_REG UEBCLX |
Definition at line 696 of file ATmega32U6.h.
| #define UEBCLX_4_REG UEBCLX |
Definition at line 697 of file ATmega32U6.h.
| #define UEBCLX_5_REG UEBCLX |
Definition at line 698 of file ATmega32U6.h.
| #define UEBCLX_6_REG UEBCLX |
Definition at line 699 of file ATmega32U6.h.
| #define UEBCLX_7_REG UEBCLX |
Definition at line 700 of file ATmega32U6.h.
| #define UEDATX_0_REG UEDATX |
Definition at line 392 of file ATmega32U6.h.
| #define UEDATX_1_REG UEDATX |
Definition at line 393 of file ATmega32U6.h.
| #define UEDATX_2_REG UEDATX |
Definition at line 394 of file ATmega32U6.h.
| #define UEDATX_3_REG UEDATX |
Definition at line 395 of file ATmega32U6.h.
| #define UEDATX_4_REG UEDATX |
Definition at line 396 of file ATmega32U6.h.
| #define UEDATX_5_REG UEDATX |
Definition at line 397 of file ATmega32U6.h.
| #define UEDATX_6_REG UEDATX |
Definition at line 398 of file ATmega32U6.h.
| #define UEDATX_7_REG UEDATX |
Definition at line 399 of file ATmega32U6.h.
| #define UENUM_0_REG UENUM |
Definition at line 467 of file ATmega32U6.h.
| #define UENUM_1_REG UENUM |
Definition at line 468 of file ATmega32U6.h.
| #define UENUM_2_REG UENUM |
Definition at line 469 of file ATmega32U6.h.
| #define UIDE_REG UHWCON |
Definition at line 635 of file ATmega32U6.h.
| #define UIMOD_REG UHWCON |
Definition at line 636 of file ATmega32U6.h.
| #define UMSEL10_REG UCSR1C |
Definition at line 995 of file ATmega32U6.h.
| #define UMSEL11_REG UCSR1C |
Definition at line 996 of file ATmega32U6.h.
| #define UNDERFI_REG UESTA0X |
Definition at line 1173 of file ATmega32U6.h.
| #define UPE1_REG UCSR1A |
Definition at line 1001 of file ATmega32U6.h.
| #define UPM10_REG UCSR1C |
Definition at line 993 of file ATmega32U6.h.
| #define UPM11_REG UCSR1C |
Definition at line 994 of file ATmega32U6.h.
| #define UPRSME_REG UDIEN |
Definition at line 180 of file ATmega32U6.h.
| #define UPRSMI_REG UDINT |
Definition at line 218 of file ATmega32U6.h.
| #define USBE_REG USBCON |
Definition at line 842 of file ATmega32U6.h.
| #define USBS1_REG UCSR1C |
Definition at line 992 of file ATmega32U6.h.
| #define UVCONE_REG UHWCON |
Definition at line 634 of file ATmega32U6.h.
| #define UVREGE_REG UHWCON |
Definition at line 633 of file ATmega32U6.h.
| #define V_REG SREG |
Definition at line 460 of file ATmega32U6.h.
| #define VBUS_REG USBSTA |
Definition at line 965 of file ATmega32U6.h.
| #define VBUSTE_REG USBCON |
Definition at line 837 of file ATmega32U6.h.
| #define VBUSTI_REG USBINT |
Definition at line 599 of file ATmega32U6.h.
| #define WAKEUPE_REG UDIEN |
Definition at line 178 of file ATmega32U6.h.
| #define WAKEUPI_REG UDINT |
Definition at line 216 of file ATmega32U6.h.
| #define WCOL_REG SPSR |
Definition at line 269 of file ATmega32U6.h.
| #define WDCE_REG WDTCSR |
Definition at line 187 of file ATmega32U6.h.
| #define WDE_REG WDTCSR |
Definition at line 186 of file ATmega32U6.h.
| #define WDIE_REG WDTCSR |
Definition at line 189 of file ATmega32U6.h.
| #define WDIF_REG WDTCSR |
Definition at line 190 of file ATmega32U6.h.
| #define WDP0_REG WDTCSR |
Definition at line 183 of file ATmega32U6.h.
| #define WDP1_REG WDTCSR |
Definition at line 184 of file ATmega32U6.h.
| #define WDP2_REG WDTCSR |
Definition at line 185 of file ATmega32U6.h.
| #define WDP3_REG WDTCSR |
Definition at line 188 of file ATmega32U6.h.
| #define WDRF_REG MCUSR |
Definition at line 849 of file ATmega32U6.h.
| #define WGM00_REG TCCR0A |
Definition at line 650 of file ATmega32U6.h.
| #define WGM01_REG TCCR0A |
Definition at line 651 of file ATmega32U6.h.
| #define WGM02_REG TCCR0B |
Definition at line 642 of file ATmega32U6.h.
| #define WGM10_REG TCCR1A |
Definition at line 512 of file ATmega32U6.h.
| #define WGM11_REG TCCR1A |
Definition at line 513 of file ATmega32U6.h.
| #define WGM12_REG TCCR1B |
Definition at line 535 of file ATmega32U6.h.
| #define WGM13_REG TCCR1B |
Definition at line 536 of file ATmega32U6.h.
| #define WGM20_REG TCCR2A |
Definition at line 878 of file ATmega32U6.h.
| #define WGM21_REG TCCR2A |
Definition at line 879 of file ATmega32U6.h.
| #define WGM22_REG TCCR2B |
Definition at line 889 of file ATmega32U6.h.
| #define WGM30_REG TCCR3A |
Definition at line 767 of file ATmega32U6.h.
| #define WGM31_REG TCCR3A |
Definition at line 768 of file ATmega32U6.h.
| #define WGM32_REG TCCR3B |
Definition at line 761 of file ATmega32U6.h.
| #define WGM33_REG TCCR3B |
Definition at line 762 of file ATmega32U6.h.
| #define XMBK_REG XMCRB |
Definition at line 1272 of file ATmega32U6.h.
| #define XMM0_REG XMCRB |
Definition at line 1269 of file ATmega32U6.h.
| #define XMM1_REG XMCRB |
Definition at line 1270 of file ATmega32U6.h.
| #define XMM2_REG XMCRB |
Definition at line 1271 of file ATmega32U6.h.
| #define Z_REG SREG |
Definition at line 458 of file ATmega32U6.h.
1.5.6