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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER0A_AVAILABLE
00069 #define TIMER0B_AVAILABLE
00070 #define TIMER1_AVAILABLE
00071 #define TIMER1A_AVAILABLE
00072 #define TIMER1B_AVAILABLE
00073
00074
00075 #define SIG_OVERFLOW0_NUM 0
00076 #define SIG_OVERFLOW1_NUM 1
00077 #define SIG_OVERFLOW_TOTAL_NUM 2
00078
00079
00080 #define SIG_OUTPUT_COMPARE0A_NUM 0
00081 #define SIG_OUTPUT_COMPARE0B_NUM 1
00082 #define SIG_OUTPUT_COMPARE1A_NUM 2
00083 #define SIG_OUTPUT_COMPARE1B_NUM 3
00084 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00085
00086
00087 #define PWM0A_NUM 0
00088 #define PWM0B_NUM 1
00089 #define PWM1A_NUM 2
00090 #define PWM1B_NUM 3
00091 #define PWM_TOTAL_NUM 4
00092
00093
00094 #define SIG_INPUT_CAPTURE1_NUM 0
00095 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00096
00097
00098
00099 #define PORTB0_REG PORTB
00100 #define PORTB1_REG PORTB
00101 #define PORTB2_REG PORTB
00102 #define PORTB3_REG PORTB
00103 #define PORTB4_REG PORTB
00104 #define PORTB5_REG PORTB
00105 #define PORTB6_REG PORTB
00106 #define PORTB7_REG PORTB
00107
00108
00109 #define LBT0_REG LINBTR
00110 #define LBT1_REG LINBTR
00111 #define LBT2_REG LINBTR
00112 #define LBT3_REG LINBTR
00113 #define LBT4_REG LINBTR
00114 #define LBT5_REG LINBTR
00115 #define LDISR_REG LINBTR
00116
00117
00118 #define MUX0_REG ADMUX
00119 #define MUX1_REG ADMUX
00120 #define MUX2_REG ADMUX
00121 #define MUX3_REG ADMUX
00122 #define MUX4_REG ADMUX
00123 #define ADLAR_REG ADMUX
00124 #define REFS0_REG ADMUX
00125 #define REFS1_REG ADMUX
00126
00127
00128 #define LID0_REG LINIDR
00129 #define LID1_REG LINIDR
00130 #define LID2_REG LINIDR
00131 #define LID3_REG LINIDR
00132 #define LID4_REG LINIDR
00133 #define LID5_REG LINIDR
00134 #define LP0_REG LINIDR
00135 #define LP1_REG LINIDR
00136
00137
00138 #define WDP0_REG WDTCSR
00139 #define WDP1_REG WDTCSR
00140 #define WDP2_REG WDTCSR
00141 #define WDE_REG WDTCSR
00142 #define WDCE_REG WDTCSR
00143 #define WDP3_REG WDTCSR
00144 #define WDIE_REG WDTCSR
00145 #define WDIF_REG WDTCSR
00146
00147
00148 #define EEDR0_REG EEDR
00149 #define EEDR1_REG EEDR
00150 #define EEDR2_REG EEDR
00151 #define EEDR3_REG EEDR
00152 #define EEDR4_REG EEDR
00153 #define EEDR5_REG EEDR
00154 #define EEDR6_REG EEDR
00155 #define EEDR7_REG EEDR
00156
00157
00158 #define AC0O_REG ACSR
00159 #define AC1O_REG ACSR
00160 #define AC2O_REG ACSR
00161 #define AC3O_REG ACSR
00162 #define AC0IF_REG ACSR
00163 #define AC1IF_REG ACSR
00164 #define AC2IF_REG ACSR
00165 #define AC3IF_REG ACSR
00166
00167
00168 #define LINDX0_REG LINSEL
00169 #define LINDX1_REG LINSEL
00170 #define LINDX2_REG LINSEL
00171 #define LAINC_REG LINSEL
00172
00173
00174 #define LCMD0_REG LINCR
00175 #define LCMD1_REG LINCR
00176 #define LCMD2_REG LINCR
00177 #define LENA_REG LINCR
00178 #define LCONF0_REG LINCR
00179 #define LCONF1_REG LINCR
00180 #define LIN13_REG LINCR
00181 #define LSWRES_REG LINCR
00182
00183
00184 #define SPDR0_REG SPDR
00185 #define SPDR1_REG SPDR
00186 #define SPDR2_REG SPDR
00187 #define SPDR3_REG SPDR
00188 #define SPDR4_REG SPDR
00189 #define SPDR5_REG SPDR
00190 #define SPDR6_REG SPDR
00191 #define SPDR7_REG SPDR
00192
00193
00194 #define SPI2X_REG SPSR
00195 #define WCOL_REG SPSR
00196 #define SPIF_REG SPSR
00197
00198
00199 #define ICR1H0_REG ICR1H
00200 #define ICR1H1_REG ICR1H
00201 #define ICR1H2_REG ICR1H
00202 #define ICR1H3_REG ICR1H
00203 #define ICR1H4_REG ICR1H
00204 #define ICR1H5_REG ICR1H
00205 #define ICR1H6_REG ICR1H
00206 #define ICR1H7_REG ICR1H
00207
00208
00209 #define ICR1L0_REG ICR1L
00210 #define ICR1L1_REG ICR1L
00211 #define ICR1L2_REG ICR1L
00212 #define ICR1L3_REG ICR1L
00213 #define ICR1L4_REG ICR1L
00214 #define ICR1L5_REG ICR1L
00215 #define ICR1L6_REG ICR1L
00216 #define ICR1L7_REG ICR1L
00217
00218
00219 #define AC1M0_REG AC1CON
00220 #define AC1M1_REG AC1CON
00221 #define AC1M2_REG AC1CON
00222 #define AC1ICE_REG AC1CON
00223 #define AC1IS0_REG AC1CON
00224 #define AC1IS1_REG AC1CON
00225 #define AC1IE_REG AC1CON
00226 #define AC1EN_REG AC1CON
00227
00228
00229 #define PRADC_REG PRR
00230 #define PRLIN_REG PRR
00231 #define PRSPI_REG PRR
00232 #define PRTIM0_REG PRR
00233 #define PRTIM1_REG PRR
00234 #define PRPSC_REG PRR
00235 #define PRCAN_REG PRR
00236
00237
00238 #define LDIV0_REG LINBRRL
00239 #define LDIV1_REG LINBRRL
00240 #define LDIV2_REG LINBRRL
00241 #define LDIV3_REG LINBRRL
00242 #define LDIV4_REG LINBRRL
00243 #define LDIV5_REG LINBRRL
00244 #define LDIV6_REG LINBRRL
00245 #define LDIV7_REG LINBRRL
00246
00247
00248 #define LDIV8_REG LINBRRH
00249 #define LDIV9_REG LINBRRH
00250 #define LDIV10_REG LINBRRH
00251 #define LDIV11_REG LINBRRH
00252
00253
00254 #define ERRP_REG CANGSTA
00255 #define BOFF_REG CANGSTA
00256 #define ENFG_REG CANGSTA
00257 #define RXBSY_REG CANGSTA
00258 #define TXBSY_REG CANGSTA
00259 #define OVFG_REG CANGSTA
00260
00261
00262 #define SWRES_REG CANGCON
00263 #define ENASTB_REG CANGCON
00264 #define TEST_REG CANGCON
00265 #define LISTEN_REG CANGCON
00266 #define SYNTTC_REG CANGCON
00267 #define TTC_REG CANGCON
00268 #define OVRQ_REG CANGCON
00269 #define ABRQ_REG CANGCON
00270
00271
00272 #define PORTD0_REG PORTD
00273 #define PORTD1_REG PORTD
00274 #define PORTD2_REG PORTD
00275 #define PORTD3_REG PORTD
00276 #define PORTD4_REG PORTD
00277 #define PORTD5_REG PORTD
00278 #define PORTD6_REG PORTD
00279 #define PORTD7_REG PORTD
00280
00281
00282 #define PORTE0_REG PORTE
00283 #define PORTE1_REG PORTE
00284 #define PORTE2_REG PORTE
00285
00286
00287 #define TCNT1H0_REG TCNT1H
00288 #define TCNT1H1_REG TCNT1H
00289 #define TCNT1H2_REG TCNT1H
00290 #define TCNT1H3_REG TCNT1H
00291 #define TCNT1H4_REG TCNT1H
00292 #define TCNT1H5_REG TCNT1H
00293 #define TCNT1H6_REG TCNT1H
00294 #define TCNT1H7_REG TCNT1H
00295
00296
00297 #define PORTC0_REG PORTC
00298 #define PORTC1_REG PORTC
00299 #define PORTC2_REG PORTC
00300 #define PORTC3_REG PORTC
00301 #define PORTC4_REG PORTC
00302 #define PORTC5_REG PORTC
00303 #define PORTC6_REG PORTC
00304 #define PORTC7_REG PORTC
00305
00306
00307 #define AMP1TS0_REG AMP1CSR
00308 #define AMP1TS1_REG AMP1CSR
00309 #define AMP1TS2_REG AMP1CSR
00310 #define AMPCMP1_REG AMP1CSR
00311 #define AMP1G0_REG AMP1CSR
00312 #define AMP1G1_REG AMP1CSR
00313 #define AMP1IS_REG AMP1CSR
00314 #define AMP1EN_REG AMP1CSR
00315
00316
00317 #define AC2M0_REG AC2CON
00318 #define AC2M1_REG AC2CON
00319 #define AC2M2_REG AC2CON
00320 #define AC2IS0_REG AC2CON
00321 #define AC2IS1_REG AC2CON
00322 #define AC2IE_REG AC2CON
00323 #define AC2EN_REG AC2CON
00324
00325
00326 #define EEAR0_REG EEARL
00327 #define EEAR1_REG EEARL
00328 #define EEAR2_REG EEARL
00329 #define EEAR3_REG EEARL
00330 #define EEAR4_REG EEARL
00331 #define EEAR5_REG EEARL
00332 #define EEAR6_REG EEARL
00333 #define EEAR7_REG EEARL
00334
00335
00336 #define INT0_REG EIMSK
00337 #define INT1_REG EIMSK
00338 #define INT2_REG EIMSK
00339 #define INT3_REG EIMSK
00340
00341
00342 #define ISC00_REG EICRA
00343 #define ISC01_REG EICRA
00344 #define ISC10_REG EICRA
00345 #define ISC11_REG EICRA
00346 #define ISC20_REG EICRA
00347 #define ISC21_REG EICRA
00348 #define ISC30_REG EICRA
00349 #define ISC31_REG EICRA
00350
00351
00352 #define LRXOK_REG LINSIR
00353 #define LTXOK_REG LINSIR
00354 #define LIDOK_REG LINSIR
00355 #define LERR_REG LINSIR
00356 #define LBUSY_REG LINSIR
00357 #define LIDST0_REG LINSIR
00358 #define LIDST1_REG LINSIR
00359 #define LIDST2_REG LINSIR
00360
00361
00362 #define ADC0D_REG DIDR0
00363 #define ADC1D_REG DIDR0
00364 #define ADC2D_REG DIDR0
00365 #define ADC3D_REG DIDR0
00366 #define ADC4D_REG DIDR0
00367 #define ADC5D_REG DIDR0
00368 #define ADC6D_REG DIDR0
00369 #define ADC7D_REG DIDR0
00370
00371
00372 #define ADC8D_REG DIDR1
00373 #define ADC9D_REG DIDR1
00374 #define ADC10D_REG DIDR1
00375 #define AMP0ND_REG DIDR1
00376 #define AMP0PD_REG DIDR1
00377 #define ACMP0D_REG DIDR1
00378 #define AMP2PD_REG DIDR1
00379
00380
00381 #define CLKPS0_REG CLKPR
00382 #define CLKPS1_REG CLKPR
00383 #define CLKPS2_REG CLKPR
00384 #define CLKPS3_REG CLKPR
00385 #define CLKPCE_REG CLKPR
00386
00387
00388 #define C_REG SREG
00389 #define Z_REG SREG
00390 #define N_REG SREG
00391 #define V_REG SREG
00392 #define S_REG SREG
00393 #define H_REG SREG
00394 #define T_REG SREG
00395 #define I_REG SREG
00396
00397
00398 #define IDMSK21_REG CANIDM1
00399 #define IDMSK22_REG CANIDM1
00400 #define IDMSK23_REG CANIDM1
00401 #define IDMSK24_REG CANIDM1
00402 #define IDMSK25_REG CANIDM1
00403 #define IDMSK26_REG CANIDM1
00404 #define IDMSK27_REG CANIDM1
00405 #define IDMSK28_REG CANIDM1
00406
00407
00408 #define IDMSK5_REG CANIDM3
00409 #define IDMSK6_REG CANIDM3
00410 #define IDMSK7_REG CANIDM3
00411 #define IDMSK8_REG CANIDM3
00412 #define IDMSK9_REG CANIDM3
00413 #define IDMSK10_REG CANIDM3
00414 #define IDMSK11_REG CANIDM3
00415 #define IDMSK12_REG CANIDM3
00416
00417
00418 #define IDMSK13_REG CANIDM2
00419 #define IDMSK14_REG CANIDM2
00420 #define IDMSK15_REG CANIDM2
00421 #define IDMSK16_REG CANIDM2
00422 #define IDMSK17_REG CANIDM2
00423 #define IDMSK18_REG CANIDM2
00424 #define IDMSK19_REG CANIDM2
00425 #define IDMSK20_REG CANIDM2
00426
00427
00428 #define IDEMSK_REG CANIDM4
00429 #define RTRMSK_REG CANIDM4
00430 #define IDMSK0_REG CANIDM4
00431 #define IDMSK1_REG CANIDM4
00432 #define IDMSK2_REG CANIDM4
00433 #define IDMSK3_REG CANIDM4
00434 #define IDMSK4_REG CANIDM4
00435
00436
00437 #define DDB0_REG DDRB
00438 #define DDB1_REG DDRB
00439 #define DDB2_REG DDRB
00440 #define DDB3_REG DDRB
00441 #define DDB4_REG DDRB
00442 #define DDB5_REG DDRB
00443 #define DDB6_REG DDRB
00444 #define DDB7_REG DDRB
00445
00446
00447 #define DDC0_REG DDRC
00448 #define DDC1_REG DDRC
00449 #define DDC2_REG DDRC
00450 #define DDC3_REG DDRC
00451 #define DDC4_REG DDRC
00452 #define DDC5_REG DDRC
00453 #define DDC6_REG DDRC
00454 #define DDC7_REG DDRC
00455
00456
00457 #define WGM10_REG TCCR1A
00458 #define WGM11_REG TCCR1A
00459 #define COM1B0_REG TCCR1A
00460 #define COM1B1_REG TCCR1A
00461 #define COM1A0_REG TCCR1A
00462 #define COM1A1_REG TCCR1A
00463
00464
00465 #define FOC1B_REG TCCR1C
00466 #define FOC1A_REG TCCR1C
00467
00468
00469 #define CS10_REG TCCR1B
00470 #define CS11_REG TCCR1B
00471 #define CS12_REG TCCR1B
00472 #define WGM12_REG TCCR1B
00473 #define WGM13_REG TCCR1B
00474 #define ICES1_REG TCCR1B
00475 #define ICNC1_REG TCCR1B
00476
00477
00478 #define CAL0_REG OSCCAL
00479 #define CAL1_REG OSCCAL
00480 #define CAL2_REG OSCCAL
00481 #define CAL3_REG OSCCAL
00482 #define CAL4_REG OSCCAL
00483 #define CAL5_REG OSCCAL
00484 #define CAL6_REG OSCCAL
00485
00486
00487 #define GPIOR10_REG GPIOR1
00488 #define GPIOR11_REG GPIOR1
00489 #define GPIOR12_REG GPIOR1
00490 #define GPIOR13_REG GPIOR1
00491 #define GPIOR14_REG GPIOR1
00492 #define GPIOR15_REG GPIOR1
00493 #define GPIOR16_REG GPIOR1
00494 #define GPIOR17_REG GPIOR1
00495
00496
00497 #define GPIOR00_REG GPIOR0
00498 #define GPIOR01_REG GPIOR0
00499 #define GPIOR02_REG GPIOR0
00500 #define GPIOR03_REG GPIOR0
00501 #define GPIOR04_REG GPIOR0
00502 #define GPIOR05_REG GPIOR0
00503 #define GPIOR06_REG GPIOR0
00504 #define GPIOR07_REG GPIOR0
00505
00506
00507 #define GPIOR20_REG GPIOR2
00508 #define GPIOR21_REG GPIOR2
00509 #define GPIOR22_REG GPIOR2
00510 #define GPIOR23_REG GPIOR2
00511 #define GPIOR24_REG GPIOR2
00512 #define GPIOR25_REG GPIOR2
00513 #define GPIOR26_REG GPIOR2
00514 #define GPIOR27_REG GPIOR2
00515
00516
00517 #define AERG_REG CANGIT
00518 #define FERG_REG CANGIT
00519 #define CERG_REG CANGIT
00520 #define SERG_REG CANGIT
00521 #define BXOK_REG CANGIT
00522 #define OVRTIM_REG CANGIT
00523 #define BOFFIT_REG CANGIT
00524 #define CANIT_REG CANGIT
00525
00526
00527 #define AC3M0_REG AC3CON
00528 #define AC3M1_REG AC3CON
00529 #define AC3M2_REG AC3CON
00530 #define AC3IS0_REG AC3CON
00531 #define AC3IS1_REG AC3CON
00532 #define AC3IE_REG AC3CON
00533 #define AC3EN_REG AC3CON
00534
00535
00536 #define LBERR_REG LINERR
00537 #define LCERR_REG LINERR
00538 #define LPERR_REG LINERR
00539 #define LSERR_REG LINERR
00540 #define LFERR_REG LINERR
00541 #define LOVERR_REG LINERR
00542 #define LTOERR_REG LINERR
00543 #define LABORT_REG LINERR
00544
00545
00546 #define PCIE0_REG PCICR
00547 #define PCIE1_REG PCICR
00548 #define PCIE2_REG PCICR
00549 #define PCIE3_REG PCICR
00550
00551
00552 #define ENOVRT_REG CANGIE
00553 #define ENERG_REG CANGIE
00554 #define ENBX_REG CANGIE
00555 #define ENERR_REG CANGIE
00556 #define ENTX_REG CANGIE
00557 #define ENRX_REG CANGIE
00558 #define ENBOFF_REG CANGIE
00559 #define ENIT_REG CANGIE
00560
00561
00562 #define TCNT0_0_REG TCNT0
00563 #define TCNT0_1_REG TCNT0
00564 #define TCNT0_2_REG TCNT0
00565 #define TCNT0_3_REG TCNT0
00566 #define TCNT0_4_REG TCNT0
00567 #define TCNT0_5_REG TCNT0
00568 #define TCNT0_6_REG TCNT0
00569 #define TCNT0_7_REG TCNT0
00570
00571
00572 #define IEMOB0_REG CANIE2
00573 #define IEMOB1_REG CANIE2
00574 #define IEMOB2_REG CANIE2
00575 #define IEMOB3_REG CANIE2
00576 #define IEMOB4_REG CANIE2
00577 #define IEMOB5_REG CANIE2
00578
00579
00580 #define SIT0_REG CANSIT2
00581 #define SIT1_REG CANSIT2
00582 #define SIT2_REG CANSIT2
00583 #define SIT3_REG CANSIT2
00584 #define SIT4_REG CANSIT2
00585 #define SIT5_REG CANSIT2
00586
00587
00588 #define CS00_REG TCCR0B
00589 #define CS01_REG TCCR0B
00590 #define CS02_REG TCCR0B
00591 #define WGM02_REG TCCR0B
00592 #define FOC0B_REG TCCR0B
00593 #define FOC0A_REG TCCR0B
00594
00595
00596 #define WGM00_REG TCCR0A
00597 #define WGM01_REG TCCR0A
00598 #define COM0B0_REG TCCR0A
00599 #define COM0B1_REG TCCR0A
00600 #define COM0A0_REG TCCR0A
00601 #define COM0A1_REG TCCR0A
00602
00603
00604 #define SPR0_REG SPCR
00605 #define SPR1_REG SPCR
00606 #define CPHA_REG SPCR
00607 #define CPOL_REG SPCR
00608 #define MSTR_REG SPCR
00609 #define DORD_REG SPCR
00610 #define SPE_REG SPCR
00611 #define SPIE_REG SPCR
00612
00613
00614 #define TOV1_REG TIFR1
00615 #define OCF1A_REG TIFR1
00616 #define OCF1B_REG TIFR1
00617 #define ICF1_REG TIFR1
00618
00619
00620 #define RB0TAG_REG CANIDT4
00621 #define RB1TAG_REG CANIDT4
00622 #define RTRTAG_REG CANIDT4
00623 #define IDT0_REG CANIDT4
00624 #define IDT1_REG CANIDT4
00625 #define IDT2_REG CANIDT4
00626 #define IDT3_REG CANIDT4
00627 #define IDT4_REG CANIDT4
00628
00629
00630 #define IDT13_REG CANIDT2
00631 #define IDT14_REG CANIDT2
00632 #define IDT15_REG CANIDT2
00633 #define IDT16_REG CANIDT2
00634 #define IDT17_REG CANIDT2
00635 #define IDT18_REG CANIDT2
00636 #define IDT19_REG CANIDT2
00637 #define IDT20_REG CANIDT2
00638
00639
00640 #define IDT5_REG CANIDT3
00641 #define IDT6_REG CANIDT3
00642 #define IDT7_REG CANIDT3
00643 #define IDT8_REG CANIDT3
00644 #define IDT9_REG CANIDT3
00645 #define IDT10_REG CANIDT3
00646 #define IDT11_REG CANIDT3
00647 #define IDT12_REG CANIDT3
00648
00649
00650 #define IDT21_REG CANIDT1
00651 #define IDT22_REG CANIDT1
00652 #define IDT23_REG CANIDT1
00653 #define IDT24_REG CANIDT1
00654 #define IDT25_REG CANIDT1
00655 #define IDT26_REG CANIDT1
00656 #define IDT27_REG CANIDT1
00657 #define IDT28_REG CANIDT1
00658
00659
00660 #define PSR10_REG GTCCR
00661 #define ICPSEL1_REG GTCCR
00662 #define TSM_REG GTCCR
00663 #define PSRSYNC_REG GTCCR
00664
00665
00666 #define DLC0_REG CANCDMOB
00667 #define DLC1_REG CANCDMOB
00668 #define DLC2_REG CANCDMOB
00669 #define DLC3_REG CANCDMOB
00670 #define IDE_REG CANCDMOB
00671 #define RPLV_REG CANCDMOB
00672 #define CONMOB0_REG CANCDMOB
00673 #define CONMOB1_REG CANCDMOB
00674
00675
00676 #define SP8_REG SPH
00677 #define SP9_REG SPH
00678 #define SP10_REG SPH
00679 #define SP11_REG SPH
00680 #define SP12_REG SPH
00681 #define SP13_REG SPH
00682 #define SP14_REG SPH
00683 #define SP15_REG SPH
00684
00685
00686 #define CGP0_REG CANHPMOB
00687 #define CGP1_REG CANHPMOB
00688 #define CGP2_REG CANHPMOB
00689 #define CGP3_REG CANHPMOB
00690 #define HPMOB0_REG CANHPMOB
00691 #define HPMOB1_REG CANHPMOB
00692 #define HPMOB2_REG CANHPMOB
00693 #define HPMOB3_REG CANHPMOB
00694
00695
00696 #define OCR1BL0_REG OCR1BL
00697 #define OCR1BL1_REG OCR1BL
00698 #define OCR1BL2_REG OCR1BL
00699 #define OCR1BL3_REG OCR1BL
00700 #define OCR1BL4_REG OCR1BL
00701 #define OCR1BL5_REG OCR1BL
00702 #define OCR1BL6_REG OCR1BL
00703 #define OCR1BL7_REG OCR1BL
00704
00705
00706 #define OCR1BH0_REG OCR1BH
00707 #define OCR1BH1_REG OCR1BH
00708 #define OCR1BH2_REG OCR1BH
00709 #define OCR1BH3_REG OCR1BH
00710 #define OCR1BH4_REG OCR1BH
00711 #define OCR1BH5_REG OCR1BH
00712 #define OCR1BH6_REG OCR1BH
00713 #define OCR1BH7_REG OCR1BH
00714
00715
00716 #define SP0_REG SPL
00717 #define SP1_REG SPL
00718 #define SP2_REG SPL
00719 #define SP3_REG SPL
00720 #define SP4_REG SPL
00721 #define SP5_REG SPL
00722 #define SP6_REG SPL
00723 #define SP7_REG SPL
00724
00725
00726 #define PORF_REG MCUSR
00727 #define EXTRF_REG MCUSR
00728 #define BORF_REG MCUSR
00729 #define WDRF_REG MCUSR
00730
00731
00732 #define EERE_REG EECR
00733 #define EEWE_REG EECR
00734 #define EEMWE_REG EECR
00735 #define EERIE_REG EECR
00736 #define EEPM0_REG EECR
00737 #define EEPM1_REG EECR
00738
00739
00740 #define LENRXOK_REG LINENIR
00741 #define LENTXOK_REG LINENIR
00742 #define LENIDOK_REG LINENIR
00743 #define LENERR_REG LINENIR
00744
00745
00746 #define SE_REG SMCR
00747 #define SM0_REG SMCR
00748 #define SM1_REG SMCR
00749 #define SM2_REG SMCR
00750
00751
00752 #define DAEN_REG DACON
00753 #define DALA_REG DACON
00754 #define DATS0_REG DACON
00755 #define DATS1_REG DACON
00756 #define DATS2_REG DACON
00757 #define DAATE_REG DACON
00758
00759
00760 #define PCIF0_REG PCIFR
00761 #define PCIF1_REG PCIFR
00762 #define PCIF2_REG PCIFR
00763 #define PCIF3_REG PCIFR
00764
00765
00766 #define AMP2TS0_REG AMP2CSR
00767 #define AMP2TS1_REG AMP2CSR
00768 #define AMP2TS2_REG AMP2CSR
00769 #define AMPCMP2_REG AMP2CSR
00770 #define AMP2G0_REG AMP2CSR
00771 #define AMP2G1_REG AMP2CSR
00772 #define AMP2IS_REG AMP2CSR
00773 #define AMP2EN_REG AMP2CSR
00774
00775
00776 #define LDATA0_REG LINDAT
00777 #define LDATA1_REG LINDAT
00778 #define LDATA2_REG LINDAT
00779 #define LDATA3_REG LINDAT
00780 #define LDATA4_REG LINDAT
00781 #define LDATA5_REG LINDAT
00782 #define LDATA6_REG LINDAT
00783 #define LDATA7_REG LINDAT
00784
00785
00786 #define EEAR8_REG EEARH
00787 #define EEAR9_REG EEARH
00788
00789
00790 #define INDX0_REG CANPAGE
00791 #define INDX1_REG CANPAGE
00792 #define INDX2_REG CANPAGE
00793 #define AINC_REG CANPAGE
00794 #define MOBNB0_REG CANPAGE
00795 #define MOBNB1_REG CANPAGE
00796 #define MOBNB2_REG CANPAGE
00797 #define MOBNB3_REG CANPAGE
00798
00799
00800 #define LRXDL0_REG LINDLR
00801 #define LRXDL1_REG LINDLR
00802 #define LRXDL2_REG LINDLR
00803 #define LRXDL3_REG LINDLR
00804 #define LTXDL0_REG LINDLR
00805 #define LTXDL1_REG LINDLR
00806 #define LTXDL2_REG LINDLR
00807 #define LTXDL3_REG LINDLR
00808
00809
00810 #define IVCE_REG MCUCR
00811 #define IVSEL_REG MCUCR
00812 #define PUD_REG MCUCR
00813 #define SPIPS_REG MCUCR
00814
00815
00816 #define INTF0_REG EIFR
00817 #define INTF1_REG EIFR
00818 #define INTF2_REG EIFR
00819 #define INTF3_REG EIFR
00820
00821
00822 #define AERR_REG CANSTMOB
00823 #define FERR_REG CANSTMOB
00824 #define CERR_REG CANSTMOB
00825 #define SERR_REG CANSTMOB
00826 #define BERR_REG CANSTMOB
00827 #define RXOK_REG CANSTMOB
00828 #define TXOK_REG CANSTMOB
00829 #define DLCW_REG CANSTMOB
00830
00831
00832 #define DACH0_REG DACH
00833 #define DACH1_REG DACH
00834 #define DACH2_REG DACH
00835 #define DACH3_REG DACH
00836 #define DACH4_REG DACH
00837 #define DACH5_REG DACH
00838 #define DACH6_REG DACH
00839 #define DACH7_REG DACH
00840
00841
00842 #define ADPS0_REG ADCSRA
00843 #define ADPS1_REG ADCSRA
00844 #define ADPS2_REG ADCSRA
00845 #define ADIE_REG ADCSRA
00846 #define ADIF_REG ADCSRA
00847 #define ADATE_REG ADCSRA
00848 #define ADSC_REG ADCSRA
00849 #define ADEN_REG ADCSRA
00850
00851
00852 #define ENMOB0_REG CANEN2
00853 #define ENMOB1_REG CANEN2
00854 #define ENMOB2_REG CANEN2
00855 #define ENMOB3_REG CANEN2
00856 #define ENMOB4_REG CANEN2
00857 #define ENMOB5_REG CANEN2
00858
00859
00860 #define ADTS0_REG ADCSRB
00861 #define ADTS1_REG ADCSRB
00862 #define ADTS2_REG ADCSRB
00863 #define ADTS3_REG ADCSRB
00864 #define AREFEN_REG ADCSRB
00865 #define ISRCEN_REG ADCSRB
00866 #define ADHSM_REG ADCSRB
00867
00868
00869
00870
00871
00872
00873
00874
00875
00876
00877
00878
00879
00880
00881
00882
00883
00884
00885
00886
00887
00888
00889 #define TCNT1L0_REG TCNT1L
00890 #define TCNT1L1_REG TCNT1L
00891 #define TCNT1L2_REG TCNT1L
00892 #define TCNT1L3_REG TCNT1L
00893 #define TCNT1L4_REG TCNT1L
00894 #define TCNT1L5_REG TCNT1L
00895 #define TCNT1L6_REG TCNT1L
00896 #define TCNT1L7_REG TCNT1L
00897
00898
00899 #define DDD0_REG DDRD
00900 #define DDD1_REG DDRD
00901 #define DDD2_REG DDRD
00902 #define DDD3_REG DDRD
00903 #define DDD4_REG DDRD
00904 #define DDD5_REG DDRD
00905 #define DDD6_REG DDRD
00906 #define DDD7_REG DDRD
00907
00908
00909 #define DDE0_REG DDRE
00910 #define DDE1_REG DDRE
00911 #define DDE2_REG DDRE
00912
00913
00914 #define SPMEN_REG SPMCSR
00915 #define PGERS_REG SPMCSR
00916 #define PGWRT_REG SPMCSR
00917 #define BLBSET_REG SPMCSR
00918 #define RWWSRE_REG SPMCSR
00919 #define SIGRD_REG SPMCSR
00920 #define RWWSB_REG SPMCSR
00921 #define SPMIE_REG SPMCSR
00922
00923
00924 #define PRS0_REG CANBT2
00925 #define PRS1_REG CANBT2
00926 #define PRS2_REG CANBT2
00927 #define SJW0_REG CANBT2
00928 #define SJW1_REG CANBT2
00929
00930
00931 #define SMP_REG CANBT3
00932 #define PHS10_REG CANBT3
00933 #define PHS11_REG CANBT3
00934 #define PHS12_REG CANBT3
00935 #define PHS20_REG CANBT3
00936 #define PHS21_REG CANBT3
00937 #define PHS22_REG CANBT3
00938
00939
00940 #define ADCL0_REG ADCL
00941 #define ADCL1_REG ADCL
00942 #define ADCL2_REG ADCL
00943 #define ADCL3_REG ADCL
00944 #define ADCL4_REG ADCL
00945 #define ADCL5_REG ADCL
00946 #define ADCL6_REG ADCL
00947 #define ADCL7_REG ADCL
00948
00949
00950 #define BRP0_REG CANBT1
00951 #define BRP1_REG CANBT1
00952 #define BRP2_REG CANBT1
00953 #define BRP3_REG CANBT1
00954 #define BRP4_REG CANBT1
00955 #define BRP5_REG CANBT1
00956
00957
00958 #define ADCH0_REG ADCH
00959 #define ADCH1_REG ADCH
00960 #define ADCH2_REG ADCH
00961 #define ADCH3_REG ADCH
00962 #define ADCH4_REG ADCH
00963 #define ADCH5_REG ADCH
00964 #define ADCH6_REG ADCH
00965 #define ADCH7_REG ADCH
00966
00967
00968 #define DACL0_REG DACL
00969 #define DACL1_REG DACL
00970 #define DACL2_REG DACL
00971 #define DACL3_REG DACL
00972 #define DACL4_REG DACL
00973 #define DACL5_REG DACL
00974 #define DACL6_REG DACL
00975 #define DACL7_REG DACL
00976
00977
00978 #define TOIE0_REG TIMSK0
00979 #define OCIE0A_REG TIMSK0
00980 #define OCIE0B_REG TIMSK0
00981
00982
00983 #define TOIE1_REG TIMSK1
00984 #define OCIE1A_REG TIMSK1
00985 #define OCIE1B_REG TIMSK1
00986 #define ICIE1_REG TIMSK1
00987
00988
00989 #define AMP0TS0_REG AMP0CSR
00990 #define AMP0TS1_REG AMP0CSR
00991 #define AMP0TS2_REG AMP0CSR
00992 #define AMPCMP0_REG AMP0CSR
00993 #define AMP0G0_REG AMP0CSR
00994 #define AMP0G1_REG AMP0CSR
00995 #define AMP0IS_REG AMP0CSR
00996 #define AMP0EN_REG AMP0CSR
00997
00998
00999 #define PLOCK_REG PLLCSR
01000 #define PLLE_REG PLLCSR
01001 #define PLLF_REG PLLCSR
01002
01003
01004 #define PCINT0_REG PCMSK0
01005 #define PCINT1_REG PCMSK0
01006 #define PCINT2_REG PCMSK0
01007 #define PCINT3_REG PCMSK0
01008 #define PCINT4_REG PCMSK0
01009 #define PCINT5_REG PCMSK0
01010 #define PCINT6_REG PCMSK0
01011 #define PCINT7_REG PCMSK0
01012
01013
01014 #define PCINT8_REG PCMSK1
01015 #define PCINT9_REG PCMSK1
01016 #define PCINT10_REG PCMSK1
01017 #define PCINT11_REG PCMSK1
01018 #define PCINT12_REG PCMSK1
01019 #define PCINT13_REG PCMSK1
01020 #define PCINT14_REG PCMSK1
01021 #define PCINT15_REG PCMSK1
01022
01023
01024 #define PCINT16_REG PCMSK2
01025 #define PCINT17_REG PCMSK2
01026 #define PCINT18_REG PCMSK2
01027 #define PCINT19_REG PCMSK2
01028 #define PCINT20_REG PCMSK2
01029 #define PCINT21_REG PCMSK2
01030 #define PCINT22_REG PCMSK2
01031 #define PCINT23_REG PCMSK2
01032
01033
01034 #define PCINT24_REG PCMSK3
01035 #define PCINT25_REG PCMSK3
01036 #define PCINT26_REG PCMSK3
01037
01038
01039 #define PINC0_REG PINC
01040 #define PINC1_REG PINC
01041 #define PINC2_REG PINC
01042 #define PINC3_REG PINC
01043 #define PINC4_REG PINC
01044 #define PINC5_REG PINC
01045 #define PINC6_REG PINC
01046 #define PINC7_REG PINC
01047
01048
01049 #define PINB0_REG PINB
01050 #define PINB1_REG PINB
01051 #define PINB2_REG PINB
01052 #define PINB3_REG PINB
01053 #define PINB4_REG PINB
01054 #define PINB5_REG PINB
01055 #define PINB6_REG PINB
01056 #define PINB7_REG PINB
01057
01058
01059 #define AC0M0_REG AC0CON
01060 #define AC0M1_REG AC0CON
01061 #define AC0M2_REG AC0CON
01062 #define ACCKSEL_REG AC0CON
01063 #define AC0IS0_REG AC0CON
01064 #define AC0IS1_REG AC0CON
01065 #define AC0IE_REG AC0CON
01066 #define AC0EN_REG AC0CON
01067
01068
01069 #define PINE0_REG PINE
01070 #define PINE1_REG PINE
01071 #define PINE2_REG PINE
01072
01073
01074 #define PIND0_REG PIND
01075 #define PIND1_REG PIND
01076 #define PIND2_REG PIND
01077 #define PIND3_REG PIND
01078 #define PIND4_REG PIND
01079 #define PIND5_REG PIND
01080 #define PIND6_REG PIND
01081 #define PIND7_REG PIND
01082
01083
01084 #define OCR1AH0_REG OCR1AH
01085 #define OCR1AH1_REG OCR1AH
01086 #define OCR1AH2_REG OCR1AH
01087 #define OCR1AH3_REG OCR1AH
01088 #define OCR1AH4_REG OCR1AH
01089 #define OCR1AH5_REG OCR1AH
01090 #define OCR1AH6_REG OCR1AH
01091 #define OCR1AH7_REG OCR1AH
01092
01093
01094 #define OCR1AL0_REG OCR1AL
01095 #define OCR1AL1_REG OCR1AL
01096 #define OCR1AL2_REG OCR1AL
01097 #define OCR1AL3_REG OCR1AL
01098 #define OCR1AL4_REG OCR1AL
01099 #define OCR1AL5_REG OCR1AL
01100 #define OCR1AL6_REG OCR1AL
01101 #define OCR1AL7_REG OCR1AL
01102
01103
01104 #define TOV0_REG TIFR0
01105 #define OCF0A_REG TIFR0
01106 #define OCF0B_REG TIFR0
01107
01108
01109 #define MISO_PORT PORTB
01110 #define MISO_BIT 0
01111 #define PCINT0_PORT PORTB
01112 #define PCINT0_BIT 0
01113
01114 #define MOSI_PORT PORTB
01115 #define MOSI_BIT 1
01116 #define PCINT1_PORT PORTB
01117 #define PCINT1_BIT 1
01118
01119 #define ADC5_PORT PORTB
01120 #define ADC5_BIT 2
01121 #define INT1_PORT PORTB
01122 #define INT1_BIT 2
01123 #define ACMPN0_PORT PORTB
01124 #define ACMPN0_BIT 2
01125 #define PCINT2_PORT PORTB
01126 #define PCINT2_BIT 2
01127
01128 #define AMP0-_PORT PORTB
01129 #define AMP0-_BIT 3
01130 #define PCINT3_PORT PORTB
01131 #define PCINT3_BIT 3
01132
01133 #define AMP0+_PORT PORTB
01134 #define AMP0+_BIT 4
01135 #define PCINT4_PORT PORTB
01136 #define PCINT4_BIT 4
01137
01138 #define ADC6_PORT PORTB
01139 #define ADC6_BIT 5
01140 #define INT2_PORT PORTB
01141 #define INT2_BIT 5
01142 #define ACMPN1_PORT PORTB
01143 #define ACMPN1_BIT 5
01144 #define AMP2-_PORT PORTB
01145 #define AMP2-_BIT 5
01146 #define PCINT5_PORT PORTB
01147 #define PCINT5_BIT 5
01148
01149 #define ADC7_PORT PORTB
01150 #define ADC7_BIT 6
01151 #define PCINT6_PORT PORTB
01152 #define PCINT6_BIT 6
01153
01154 #define ADC4_PORT PORTB
01155 #define ADC4_BIT 7
01156 #define SCK_PORT PORTB
01157 #define SCK_BIT 7
01158 #define PCINT7_PORT PORTB
01159 #define PCINT7_BIT 7
01160
01161 #define INT3_PORT PORTC
01162 #define INT3_BIT 0
01163 #define PCINT8_PORT PORTC
01164 #define PCINT8_BIT 0
01165
01166 #define OC1B_PORT PORTC
01167 #define OC1B_BIT 1
01168 #define SS_A_PORT PORTC
01169 #define SS_A_BIT 1
01170 #define PCINT9_PORT PORTC
01171 #define PCINT9_BIT 1
01172
01173 #define T0_PORT PORTC
01174 #define T0_BIT 2
01175 #define TXCAN_PORT PORTC
01176 #define TXCAN_BIT 2
01177 #define PCINT10_PORT PORTC
01178 #define PCINT10_BIT 2
01179
01180 #define T1_PORT PORTC
01181 #define T1_BIT 3
01182 #define RXCAN_PORT PORTC
01183 #define RXCAN_BIT 3
01184 #define ICP1B_PORT PORTC
01185 #define ICP1B_BIT 3
01186 #define PCINT11_PORT PORTC
01187 #define PCINT11_BIT 3
01188
01189 #define ADC8_PORT PORTC
01190 #define ADC8_BIT 4
01191 #define AMP1-_PORT PORTC
01192 #define AMP1-_BIT 4
01193 #define ACMPN3_PORT PORTC
01194 #define ACMPN3_BIT 4
01195 #define PCINT12_PORT PORTC
01196 #define PCINT12_BIT 4
01197
01198 #define ADC9_PORT PORTC
01199 #define ADC9_BIT 5
01200 #define AMP1+_PORT PORTC
01201 #define AMP1+_BIT 5
01202 #define ACMP3_PORT PORTC
01203 #define ACMP3_BIT 5
01204 #define PCINT13_PORT PORTC
01205 #define PCINT13_BIT 5
01206
01207 #define ADC10_PORT PORTC
01208 #define ADC10_BIT 6
01209 #define ACMP1_PORT PORTC
01210 #define ACMP1_BIT 6
01211 #define PCINT14_PORT PORTC
01212 #define PCINT14_BIT 6
01213
01214 #define D2A_PORT PORTC
01215 #define D2A_BIT 7
01216 #define AMP2+_PORT PORTC
01217 #define AMP2+_BIT 7
01218 #define PCINT15_PORT PORTC
01219 #define PCINT15_BIT 7
01220
01221 #define PCINT16_PORT PORTD
01222 #define PCINT16_BIT 0
01223
01224 #define CLK0_PORT PORTD
01225 #define CLK0_BIT 1
01226 #define PCINT17_PORT PORTD
01227 #define PCINT17_BIT 1
01228
01229 #define OC1A_PORT PORTD
01230 #define OC1A_BIT 2
01231 #define MISO_A_PORT PORTD
01232 #define MISO_A_BIT 2
01233 #define PCINT18_PORT PORTD
01234 #define PCINT18_BIT 2
01235
01236 #define TXD_PORT PORTD
01237 #define TXD_BIT 3
01238 #define TXLIN_PORT PORTD
01239 #define TXLIN_BIT 3
01240 #define OC0A_PORT PORTD
01241 #define OC0A_BIT 3
01242 #define SS_PORT PORTD
01243 #define SS_BIT 3
01244 #define MOSI_A_PORT PORTD
01245 #define MOSI_A_BIT 3
01246 #define PCINT19_PORT PORTD
01247 #define PCINT19_BIT 3
01248
01249 #define ADC1_PORT PORTD
01250 #define ADC1_BIT 4
01251 #define RXD_PORT PORTD
01252 #define RXD_BIT 4
01253 #define RXLIN_PORT PORTD
01254 #define RXLIN_BIT 4
01255 #define ICP1A_PORT PORTD
01256 #define ICP1A_BIT 4
01257 #define SCK_A_PORT PORTD
01258 #define SCK_A_BIT 4
01259 #define PCINT20_PORT PORTD
01260 #define PCINT20_BIT 4
01261
01262 #define ADC2_PORT PORTD
01263 #define ADC2_BIT 5
01264 #define ACMP2_PORT PORTD
01265 #define ACMP2_BIT 5
01266 #define PCINT21_PORT PORTD
01267 #define PCINT21_BIT 5
01268
01269 #define ADC3_PORT PORTD
01270 #define ADC3_BIT 6
01271 #define ACMPN2_PORT PORTD
01272 #define ACMPN2_BIT 6
01273 #define INT0_PORT PORTD
01274 #define INT0_BIT 6
01275 #define PCINT22_PORT PORTD
01276 #define PCINT22_BIT 6
01277
01278 #define ACMP0_PORT PORTD
01279 #define ACMP0_BIT 7
01280 #define PCINT23_PORT PORTD
01281 #define PCINT23_BIT 7
01282
01283 #define RESET_PORT PORTE
01284 #define RESET_BIT 0
01285 #define OCD_PORT PORTE
01286 #define OCD_BIT 0
01287 #define PCINT24_PORT PORTE
01288 #define PCINT24_BIT 0
01289
01290 #define OC0B_PORT PORTE
01291 #define OC0B_BIT 1
01292 #define XTAL1_PORT PORTE
01293 #define XTAL1_BIT 1
01294 #define PCINT25_PORT PORTE
01295 #define PCINT25_BIT 1
01296
01297 #define ADC0_PORT PORTE
01298 #define ADC0_BIT 2
01299 #define XTAL2_PORT PORTE
01300 #define XTAL2_BIT 2
01301 #define PCINT26_PORT PORTE
01302 #define PCINT26_BIT 2
01303
01304