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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE1A_NUM 0
00100 #define SIG_OUTPUT_COMPARE1B_NUM 1
00101 #define SIG_OUTPUT_COMPARE2_NUM 2
00102 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
00103
00104
00105 #define PWM1A_NUM 0
00106 #define PWM1B_NUM 1
00107 #define PWM2_NUM 2
00108 #define PWM_TOTAL_NUM 3
00109
00110
00111 #define SIG_INPUT_CAPTURE1_NUM 0
00112 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00113
00114
00115
00116 #define WDP0_REG WDTCR
00117 #define WDP1_REG WDTCR
00118 #define WDP2_REG WDTCR
00119 #define WDE_REG WDTCR
00120 #define WDTOE_REG WDTCR
00121
00122
00123 #define INT0_REG GIMSK
00124 #define INT1_REG GIMSK
00125
00126
00127 #define ICR1H0_REG ICR1H
00128 #define ICR1H1_REG ICR1H
00129 #define ICR1H2_REG ICR1H
00130 #define ICR1H3_REG ICR1H
00131 #define ICR1H4_REG ICR1H
00132 #define ICR1H5_REG ICR1H
00133 #define ICR1H6_REG ICR1H
00134 #define ICR1H7_REG ICR1H
00135
00136
00137 #define MUX0_REG ADMUX
00138 #define MUX1_REG ADMUX
00139 #define MUX2_REG ADMUX
00140 #define MUX3_REG ADMUX
00141 #define MUX4_REG ADMUX
00142 #define ADLAR_REG ADMUX
00143 #define REFS0_REG ADMUX
00144 #define REFS1_REG ADMUX
00145
00146
00147 #define CS00_REG TCCR0
00148 #define CS01_REG TCCR0
00149 #define CS02_REG TCCR0
00150
00151
00152 #define C_REG SREG
00153 #define Z_REG SREG
00154 #define N_REG SREG
00155 #define V_REG SREG
00156 #define S_REG SREG
00157 #define H_REG SREG
00158 #define T_REG SREG
00159 #define I_REG SREG
00160
00161
00162 #define DDB0_REG DDRB
00163 #define DDB1_REG DDRB
00164 #define DDB2_REG DDRB
00165 #define DDB3_REG DDRB
00166 #define DDB4_REG DDRB
00167 #define DDB5_REG DDRB
00168 #define DDB6_REG DDRB
00169 #define DDB7_REG DDRB
00170
00171
00172 #define SPI2X_REG SPSR
00173 #define WCOL_REG SPSR
00174 #define SPIF_REG SPSR
00175
00176
00177 #define TWD0_REG TWDR
00178 #define TWD1_REG TWDR
00179 #define TWD2_REG TWDR
00180 #define TWD3_REG TWDR
00181 #define TWD4_REG TWDR
00182 #define TWD5_REG TWDR
00183 #define TWD6_REG TWDR
00184 #define TWD7_REG TWDR
00185
00186
00187 #define EEDR0_REG EEDR
00188 #define EEDR1_REG EEDR
00189 #define EEDR2_REG EEDR
00190 #define EEDR3_REG EEDR
00191 #define EEDR4_REG EEDR
00192 #define EEDR5_REG EEDR
00193 #define EEDR6_REG EEDR
00194 #define EEDR7_REG EEDR
00195
00196
00197 #define DDC0_REG DDRC
00198 #define DDC1_REG DDRC
00199 #define DDC2_REG DDRC
00200 #define DDC3_REG DDRC
00201 #define DDC4_REG DDRC
00202 #define DDC5_REG DDRC
00203 #define DDC6_REG DDRC
00204 #define DDC7_REG DDRC
00205
00206
00207 #define DDA0_REG DDRA
00208 #define DDA1_REG DDRA
00209 #define DDA2_REG DDRA
00210 #define DDA3_REG DDRA
00211 #define DDA4_REG DDRA
00212 #define DDA5_REG DDRA
00213 #define DDA6_REG DDRA
00214 #define DDA7_REG DDRA
00215
00216
00217 #define PWM10_REG TCCR1A
00218 #define PWM11_REG TCCR1A
00219 #define FOC1B_REG TCCR1A
00220 #define FOC1A_REG TCCR1A
00221 #define COM1B0_REG TCCR1A
00222 #define COM1B1_REG TCCR1A
00223 #define COM1A0_REG TCCR1A
00224 #define COM1A1_REG TCCR1A
00225
00226
00227 #define DDD0_REG DDRD
00228 #define DDD1_REG DDRD
00229 #define DDD2_REG DDRD
00230 #define DDD3_REG DDRD
00231 #define DDD4_REG DDRD
00232 #define DDD5_REG DDRD
00233 #define DDD6_REG DDRD
00234 #define DDD7_REG DDRD
00235
00236
00237 #define CS10_REG TCCR1B
00238 #define CS11_REG TCCR1B
00239 #define CS12_REG TCCR1B
00240 #define CTC1_REG TCCR1B
00241 #define ICES1_REG TCCR1B
00242 #define ICNC1_REG TCCR1B
00243
00244
00245 #define INTF0_REG GIFR
00246 #define INTF1_REG GIFR
00247
00248
00249 #define TOIE0_REG TIMSK
00250 #define TOIE1_REG TIMSK
00251 #define OCIE1B_REG TIMSK
00252 #define OCIE1A_REG TIMSK
00253 #define TICIE1_REG TIMSK
00254 #define TOIE2_REG TIMSK
00255 #define OCIE2_REG TIMSK
00256
00257
00258 #define MPCM_REG UCSRA
00259 #define U2X_REG UCSRA
00260 #define OR_REG UCSRA
00261 #define FE_REG UCSRA
00262 #define UDRE_REG UCSRA
00263 #define TXC_REG UCSRA
00264 #define RXC_REG UCSRA
00265
00266
00267 #define SPDR0_REG SPDR
00268 #define SPDR1_REG SPDR
00269 #define SPDR2_REG SPDR
00270 #define SPDR3_REG SPDR
00271 #define SPDR4_REG SPDR
00272 #define SPDR5_REG SPDR
00273 #define SPDR6_REG SPDR
00274 #define SPDR7_REG SPDR
00275
00276
00277 #define TXB8_REG UCSRB
00278 #define RXB8_REG UCSRB
00279 #define CHR9_REG UCSRB
00280 #define TXEN_REG UCSRB
00281 #define RXEN_REG UCSRB
00282 #define UDRIE_REG UCSRB
00283 #define TXCIE_REG UCSRB
00284 #define RXCIE_REG UCSRB
00285
00286
00287 #define PSR10_REG SFIOR
00288 #define PSR2_REG SFIOR
00289 #define PUD_REG SFIOR
00290 #define ACME_REG SFIOR
00291
00292
00293 #define ACIS0_REG ACSR
00294 #define ACIS1_REG ACSR
00295 #define ACIC_REG ACSR
00296 #define ACIE_REG ACSR
00297 #define ACI_REG ACSR
00298 #define ACO_REG ACSR
00299 #define ACBG_REG ACSR
00300 #define ACD_REG ACSR
00301
00302
00303 #define SP8_REG SPH
00304 #define SP9_REG SPH
00305 #define SP10_REG SPH
00306
00307
00308 #define OCR1BL0_REG OCR1BL
00309 #define OCR1BL1_REG OCR1BL
00310 #define OCR1BL2_REG OCR1BL
00311 #define OCR1BL3_REG OCR1BL
00312 #define OCR1BL4_REG OCR1BL
00313 #define OCR1BL5_REG OCR1BL
00314 #define OCR1BL6_REG OCR1BL
00315 #define OCR1BL7_REG OCR1BL
00316
00317
00318 #define UBRRHI0_REG UBRRHI
00319 #define UBRRHI1_REG UBRRHI
00320 #define UBRRHI2_REG UBRRHI
00321 #define UBRRHI3_REG UBRRHI
00322
00323
00324 #define SP0_REG SPL
00325 #define SP1_REG SPL
00326 #define SP2_REG SPL
00327 #define SP3_REG SPL
00328 #define SP4_REG SPL
00329 #define SP5_REG SPL
00330 #define SP6_REG SPL
00331 #define SP7_REG SPL
00332
00333
00334 #define OCR1BH0_REG OCR1BH
00335 #define OCR1BH1_REG OCR1BH
00336 #define OCR1BH2_REG OCR1BH
00337 #define OCR1BH3_REG OCR1BH
00338 #define OCR1BH4_REG OCR1BH
00339 #define OCR1BH5_REG OCR1BH
00340 #define OCR1BH6_REG OCR1BH
00341 #define OCR1BH7_REG OCR1BH
00342
00343
00344 #define PIND0_REG PIND
00345 #define PIND1_REG PIND
00346 #define PIND2_REG PIND
00347 #define PIND3_REG PIND
00348 #define PIND4_REG PIND
00349 #define PIND5_REG PIND
00350 #define PIND6_REG PIND
00351 #define PIND7_REG PIND
00352
00353
00354 #define SPMEN_REG SPMCR
00355 #define PGERS_REG SPMCR
00356 #define PGWRT_REG SPMCR
00357 #define BLBSET_REG SPMCR
00358 #define ASRE_REG SPMCR
00359 #define ASB_REG SPMCR
00360
00361
00362 #define TWBR0_REG TWBR
00363 #define TWBR1_REG TWBR
00364 #define TWBR2_REG TWBR
00365 #define TWBR3_REG TWBR
00366 #define TWBR4_REG TWBR
00367 #define TWBR5_REG TWBR
00368 #define TWBR6_REG TWBR
00369 #define TWBR7_REG TWBR
00370
00371
00372 #define ADCL0_REG ADCL
00373 #define ADCL1_REG ADCL
00374 #define ADCL2_REG ADCL
00375 #define ADCL3_REG ADCL
00376 #define ADCL4_REG ADCL
00377 #define ADCL5_REG ADCL
00378 #define ADCL6_REG ADCL
00379 #define ADCL7_REG ADCL
00380
00381
00382 #define PORF_REG MCUSR
00383 #define EXTRF_REG MCUSR
00384 #define BORF_REG MCUSR
00385 #define WDRF_REG MCUSR
00386
00387
00388 #define EERE_REG EECR
00389 #define EEWE_REG EECR
00390 #define EEMWE_REG EECR
00391 #define EERIE_REG EECR
00392
00393
00394 #define CAL0_REG OSCCAL
00395 #define CAL1_REG OSCCAL
00396 #define CAL2_REG OSCCAL
00397 #define CAL3_REG OSCCAL
00398 #define CAL4_REG OSCCAL
00399 #define CAL5_REG OSCCAL
00400 #define CAL6_REG OSCCAL
00401 #define CAL7_REG OSCCAL
00402
00403
00404 #define TCNT1L0_REG TCNT1L
00405 #define TCNT1L1_REG TCNT1L
00406 #define TCNT1L2_REG TCNT1L
00407 #define TCNT1L3_REG TCNT1L
00408 #define TCNT1L4_REG TCNT1L
00409 #define TCNT1L5_REG TCNT1L
00410 #define TCNT1L6_REG TCNT1L
00411 #define TCNT1L7_REG TCNT1L
00412
00413
00414 #define PORTB0_REG PORTB
00415 #define PORTB1_REG PORTB
00416 #define PORTB2_REG PORTB
00417 #define PORTB3_REG PORTB
00418 #define PORTB4_REG PORTB
00419 #define PORTB5_REG PORTB
00420 #define PORTB6_REG PORTB
00421 #define PORTB7_REG PORTB
00422
00423
00424 #define PORTD0_REG PORTD
00425 #define PORTD1_REG PORTD
00426 #define PORTD2_REG PORTD
00427 #define PORTD3_REG PORTD
00428 #define PORTD4_REG PORTD
00429 #define PORTD5_REG PORTD
00430 #define PORTD6_REG PORTD
00431 #define PORTD7_REG PORTD
00432
00433
00434 #define TCNT1H0_REG TCNT1H
00435 #define TCNT1H1_REG TCNT1H
00436 #define TCNT1H2_REG TCNT1H
00437 #define TCNT1H3_REG TCNT1H
00438 #define TCNT1H4_REG TCNT1H
00439 #define TCNT1H5_REG TCNT1H
00440 #define TCNT1H6_REG TCNT1H
00441 #define TCNT1H7_REG TCNT1H
00442
00443
00444 #define PORTC0_REG PORTC
00445 #define PORTC1_REG PORTC
00446 #define PORTC2_REG PORTC
00447 #define PORTC3_REG PORTC
00448 #define PORTC4_REG PORTC
00449 #define PORTC5_REG PORTC
00450 #define PORTC6_REG PORTC
00451 #define PORTC7_REG PORTC
00452
00453
00454 #define ADCH0_REG ADCH
00455 #define ADCH1_REG ADCH
00456 #define ADCH2_REG ADCH
00457 #define ADCH3_REG ADCH
00458 #define ADCH4_REG ADCH
00459 #define ADCH5_REG ADCH
00460 #define ADCH6_REG ADCH
00461 #define ADCH7_REG ADCH
00462
00463
00464 #define PORTA0_REG PORTA
00465 #define PORTA1_REG PORTA
00466 #define PORTA2_REG PORTA
00467 #define PORTA3_REG PORTA
00468 #define PORTA4_REG PORTA
00469 #define PORTA5_REG PORTA
00470 #define PORTA6_REG PORTA
00471 #define PORTA7_REG PORTA
00472
00473
00474 #define TWIE_REG TWCR
00475 #define TWEN_REG TWCR
00476 #define TWWC_REG TWCR
00477 #define TWSTO_REG TWCR
00478 #define TWSTA_REG TWCR
00479 #define TWEA_REG TWCR
00480 #define TWINT_REG TWCR
00481
00482
00483 #define TCNT00_REG TCNT0
00484 #define TCNT01_REG TCNT0
00485 #define TCNT02_REG TCNT0
00486 #define TCNT03_REG TCNT0
00487 #define TCNT04_REG TCNT0
00488 #define TCNT05_REG TCNT0
00489 #define TCNT06_REG TCNT0
00490 #define TCNT07_REG TCNT0
00491
00492
00493 #define UDR0_REG UDR
00494 #define UDR1_REG UDR
00495 #define UDR2_REG UDR
00496 #define UDR3_REG UDR
00497 #define UDR4_REG UDR
00498 #define UDR5_REG UDR
00499 #define UDR6_REG UDR
00500 #define UDR7_REG UDR
00501
00502
00503 #define TWGCE_REG TWAR
00504 #define TWA0_REG TWAR
00505 #define TWA1_REG TWAR
00506 #define TWA2_REG TWAR
00507 #define TWA3_REG TWAR
00508 #define TWA4_REG TWAR
00509 #define TWA5_REG TWAR
00510 #define TWA6_REG TWAR
00511
00512
00513 #define UBRR0_REG UBRR
00514 #define UBRR1_REG UBRR
00515 #define UBRR2_REG UBRR
00516 #define UBRR3_REG UBRR
00517 #define UBRR4_REG UBRR
00518 #define UBRR5_REG UBRR
00519 #define UBRR6_REG UBRR
00520 #define UBRR7_REG UBRR
00521
00522
00523 #define ADPS0_REG ADCSR
00524 #define ADPS1_REG ADCSR
00525 #define ADPS2_REG ADCSR
00526 #define ADIE_REG ADCSR
00527 #define ADIF_REG ADCSR
00528 #define ADFR_REG ADCSR
00529 #define ADSC_REG ADCSR
00530 #define ADEN_REG ADCSR
00531
00532
00533 #define CS20_REG TCCR2
00534 #define CS21_REG TCCR2
00535 #define CS22_REG TCCR2
00536 #define WGM21_REG TCCR2
00537 #define COM20_REG TCCR2
00538 #define COM21_REG TCCR2
00539 #define WGM20_REG TCCR2
00540 #define FOC2_REG TCCR2
00541
00542
00543 #define TOV0_REG TIFR
00544 #define TOV1_REG TIFR
00545 #define OCF1B_REG TIFR
00546 #define OCF1A_REG TIFR
00547 #define ICF1_REG TIFR
00548 #define TOV2_REG TIFR
00549 #define OCF2_REG TIFR
00550
00551
00552 #define EEAR8_REG EEARH
00553
00554
00555 #define TCNT2_0_REG TCNT2
00556 #define TCNT2_1_REG TCNT2
00557 #define TCNT2_2_REG TCNT2
00558 #define TCNT2_3_REG TCNT2
00559 #define TCNT2_4_REG TCNT2
00560 #define TCNT2_5_REG TCNT2
00561 #define TCNT2_6_REG TCNT2
00562 #define TCNT2_7_REG TCNT2
00563
00564
00565 #define EEAR0_REG EEARL
00566 #define EEAR1_REG EEARL
00567 #define EEAR2_REG EEARL
00568 #define EEAR3_REG EEARL
00569 #define EEAR4_REG EEARL
00570 #define EEAR5_REG EEARL
00571 #define EEAR6_REG EEARL
00572 #define EEAR7_REG EEARL
00573
00574
00575 #define TWS3_REG TWSR
00576 #define TWS4_REG TWSR
00577 #define TWS5_REG TWSR
00578 #define TWS6_REG TWSR
00579 #define TWS7_REG TWSR
00580
00581
00582 #define PINC0_REG PINC
00583 #define PINC1_REG PINC
00584 #define PINC2_REG PINC
00585 #define PINC3_REG PINC
00586 #define PINC4_REG PINC
00587 #define PINC5_REG PINC
00588 #define PINC6_REG PINC
00589 #define PINC7_REG PINC
00590
00591
00592 #define PINB0_REG PINB
00593 #define PINB1_REG PINB
00594 #define PINB2_REG PINB
00595 #define PINB3_REG PINB
00596 #define PINB4_REG PINB
00597 #define PINB5_REG PINB
00598 #define PINB6_REG PINB
00599 #define PINB7_REG PINB
00600
00601
00602 #define PINA0_REG PINA
00603 #define PINA1_REG PINA
00604 #define PINA2_REG PINA
00605 #define PINA3_REG PINA
00606 #define PINA4_REG PINA
00607 #define PINA5_REG PINA
00608 #define PINA6_REG PINA
00609 #define PINA7_REG PINA
00610
00611
00612 #define ISC00_REG MCUCR
00613 #define ISC01_REG MCUCR
00614 #define ISC10_REG MCUCR
00615 #define ISC11_REG MCUCR
00616 #define SM0_REG MCUCR
00617 #define SM1_REG MCUCR
00618 #define SE_REG MCUCR
00619
00620
00621 #define OCR1AH0_REG OCR1AH
00622 #define OCR1AH1_REG OCR1AH
00623 #define OCR1AH2_REG OCR1AH
00624 #define OCR1AH3_REG OCR1AH
00625 #define OCR1AH4_REG OCR1AH
00626 #define OCR1AH5_REG OCR1AH
00627 #define OCR1AH6_REG OCR1AH
00628 #define OCR1AH7_REG OCR1AH
00629
00630
00631 #define OCR1AL0_REG OCR1AL
00632 #define OCR1AL1_REG OCR1AL
00633 #define OCR1AL2_REG OCR1AL
00634 #define OCR1AL3_REG OCR1AL
00635 #define OCR1AL4_REG OCR1AL
00636 #define OCR1AL5_REG OCR1AL
00637 #define OCR1AL6_REG OCR1AL
00638 #define OCR1AL7_REG OCR1AL
00639
00640
00641 #define SPR0_REG SPCR
00642 #define SPR1_REG SPCR
00643 #define CPHA_REG SPCR
00644 #define CPOL_REG SPCR
00645 #define MSTR_REG SPCR
00646 #define DORD_REG SPCR
00647 #define SPE_REG SPCR
00648 #define SPIE_REG SPCR
00649
00650
00651 #define TCR2UB_REG ASSR
00652 #define OCR2UB_REG ASSR
00653 #define TCN2UB_REG ASSR
00654 #define AS2_REG ASSR
00655
00656
00657 #define OCR2_0_REG OCR2
00658 #define OCR2_1_REG OCR2
00659 #define OCR2_2_REG OCR2
00660 #define OCR2_3_REG OCR2
00661 #define OCR2_4_REG OCR2
00662 #define OCR2_5_REG OCR2
00663 #define OCR2_6_REG OCR2
00664 #define OCR2_7_REG OCR2
00665
00666
00667 #define ICR1L0_REG ICR1L
00668 #define ICR1L1_REG ICR1L
00669 #define ICR1L2_REG ICR1L
00670 #define ICR1L3_REG ICR1L
00671 #define ICR1L4_REG ICR1L
00672 #define ICR1L5_REG ICR1L
00673 #define ICR1L6_REG ICR1L
00674 #define ICR1L7_REG ICR1L
00675
00676
00677 #define ADC0_PORT PORTA
00678 #define ADC0_BIT 0
00679
00680 #define ADC1_PORT PORTA
00681 #define ADC1_BIT 1
00682
00683 #define ADC2_PORT PORTA
00684 #define ADC2_BIT 2
00685
00686 #define ADC3_PORT PORTA
00687 #define ADC3_BIT 3
00688
00689 #define ADC4_PORT PORTA
00690 #define ADC4_BIT 4
00691
00692 #define ADc5_PORT PORTA
00693 #define ADc5_BIT 5
00694
00695 #define ADC6_PORT PORTA
00696 #define ADC6_BIT 6
00697
00698 #define ADC7_PORT PORTA
00699 #define ADC7_BIT 7
00700
00701 #define T0_PORT PORTB
00702 #define T0_BIT 0
00703
00704 #define T1_PORT PORTB
00705 #define T1_BIT 1
00706
00707 #define AIN0_PORT PORTB
00708 #define AIN0_BIT 2
00709
00710 #define AIN1_PORT PORTB
00711 #define AIN1_BIT 3
00712
00713 #define SS_PORT PORTB
00714 #define SS_BIT 4
00715
00716 #define MOSI_PORT PORTB
00717 #define MOSI_BIT 5
00718
00719 #define MISO_PORT PORTB
00720 #define MISO_BIT 6
00721
00722
00723 #define SCL_PORT PORTC
00724 #define SCL_BIT 0
00725
00726 #define SDA_PORT PORTC
00727 #define SDA_BIT 1
00728
00729
00730
00731
00732
00733 #define TOSC1_PORT PORTC
00734 #define TOSC1_BIT 6
00735
00736 #define TOSC2_PORT PORTC
00737 #define TOSC2_BIT 7
00738
00739 #define RXD_PORT PORTD
00740 #define RXD_BIT 0
00741
00742 #define TXD_PORT PORTD
00743 #define TXD_BIT 1
00744
00745 #define INT0_PORT PORTD
00746 #define INT0_BIT 2
00747
00748 #define INT1_PORT PORTD
00749 #define INT1_BIT 3
00750
00751 #define OC1B_PORT PORTD
00752 #define OC1B_BIT 4
00753
00754 #define OC1A_PORT PORTD
00755 #define OC1A_BIT 5
00756
00757 #define ICP_PORT PORTD
00758 #define ICP_BIT 6
00759
00760 #define OC2_PORT PORTD
00761 #define OC2_BIT 7
00762
00763