AVR: aversive_10-03-12/modules/hardware/adc/adc

00001 /*  
00002  *  Copyright Droids Corporation, Microb Technology, Eirbot (2005)
00003  * 
00004  *  This program is free software; you can redistribute it and/or modify
00005  *  it under the terms of the GNU General Public License as published by
00006  *  the Free Software Foundation; either version 2 of the License, or
00007  *  (at your option) any later version.
00008  *
00009  *  This program is distributed in the hope that it will be useful,
00010  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
00011  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012  *  GNU General Public License for more details.
00013  *
00014  *  You should have received a copy of the GNU General Public License
00015  *  along with this program; if not, write to the Free Software
00016  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
00017  *
00018  *  Revision : $Id: adc_archs.h,v 1.6 2009-03-15 21:51:19 zer0 Exp $
00019  *
00020  */
00021 #ifndef _ADC_ARCHS_
00022 #define _ADC_ARCHS_
00023 
00024 
00035 /* ------------------------------------------------------------------------------------
00036    ----------------------------   REGISTER VARIATIONS   -------------------------------
00037    ------------------------------------------------------------------------------------ */
00038 
00039 /*
00040 
00041 Detailed register configurations, over the various AVR micros: 
00042 
00043            ADMUX                                                ADCSRA                                               ADCSRB                                             SFIOR
00044            7     6     5     4     3     2     1     0          7     6     5     4     3     2     1     0          7     6     5     4     3     2     1     0         7     6     5     4     3     2     1    0
00045 ATM64      REFS1 REFS0 ADLAR MUX4  MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0                                    ADTS2 ADTS1 ADTS0
00046 also AT90CAN64 AT90CAN64 ATM164 ATM324 ATM644 ATM165 (ATM325 ATM3250 ATM645 ATM5450)
00047 
00048 ATM128     REFS1 REFS0 ADLAR MUX4  MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADFR  ADIF  ADIE  ADPS2 ADPS1 ADPS0
00049 also ATtiny26
00050 
00051 AT90CAN128 REFS1 REFS0 ADLAR MUX4  MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0      ADHSM                         ADTS2 ADTS1 ADTS0
00052 also AT90USB1286 ATUSB1287 ATUSB646 ATUSB647
00053 
00054 ATM16      REFS1 REFS0 ADLAR MUX4  MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0                                                          ADTS2 ADTS1 ADTS0
00055 also ATM32 ATM8535
00056 
00057 ATM48      REFS1 REFS0 ADLAR -     MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0                                    ADTS2 ADTS1 ADTS0
00058 also ATM88 ATM168 ATM169 ATM329 ATM3290 ATM649  ATM6490
00059 
00060 ATM8       REFS1 REFS0 ADLAR -     MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADFR  ADIF  ADIE  ADPS2 ADPS1 ADPS0
00061 
00062 AT90PWM2   REFS1 REFS0 ADLAR -     MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0      ADHSM                  ADASCR ADTS2 ADTS1 ADTS0
00063 also AT90PWM3 (! AT90PWM2B and 3B do not have ADASCR !)
00064 
00065 ATM640     REFS1 REFS0 ADLAR MUX4  MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0                               MUX5 ADTS2 ADTS1 ADTS0
00066 also ATM1280 ATM1281 ATM2560 ATM2561
00067 
00068 ATtiny13   -     REFS0 ADLAR -     -     -     MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0                                    ADTS2 ADTS1 ADTS0
00069 ATtiny15   REFS1 REFS0 ADLAR -     -     MUX2  MUX1  MUX0       ADEN  ADSC  ADFR  ADIF  ADIE  ADPS2 ADPS1 ADPS0
00070 ATtiny24   REFS1 REFS0 MUX5  MUX4  MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0      BIN                    ADLAR  ADTS2 ADTS1 ADTS0
00071 also ATtiny44 ATtiny84
00072 ATtiny25   REFS1 REFS0 ADLAR REFS2 MUX3  MUX2  MUX1  MUX0       ADEN  ADSC  ADATE ADIF  ADIE  ADPS2 ADPS1 ADPS0      BIN   -     IPR               ADTS2 ADTS1 ADTS0
00073 also ATtiny45 ATtiny85
00074 
00075 
00076 
00077 ----------
00078 ATmega325_3250_645_6540 : preliminary incomplete DS, so not implemented now
00079 
00080 NO ADC : ATM162 ATM8515 ATtiny11 ATtiny12 ATtiny2313 ATtiny28
00081 
00082 ATMEGA406 : completely different, 12bits, not implemented
00083 */
00084 
00085 
00086 /* some default defines */
00087 #define MUX5_MASK_IN_CONFIG (1<<MUX5)
00088 #define ADLAR_MASK_IN_CONFIG (1<<ADLAR)
00089 
00090 
00091 
00092 
00093 #if ( defined (__AVR_ATmega162__)     \
00094     || defined (__AVR_ATmega8515__)   \
00095     || defined (__AVR_ATtiny11__) || defined (__AVR_ATtiny12__) \
00096     || defined (__AVR_ATtiny2313__) || defined (__AVR_ATtiny28__)  )
00097 
00098 #  error no ADC on your AVR device, please deactivate the ADC module
00099 #endif // ...
00100 
00101 #if ( defined (__AVR_ATmega406__) )
00102 #  error no The ADC of the ATmega406 is currently not supported by the ADC module
00103 #endif // ...
00104 
00105 #if ( defined (__AVR_ATmega325__) || defined (__AVR_ATmega2350__)   \
00106     || defined (__AVR_ATmega645__) || defined (__AVR_ATmega6540__) )
00107 
00108 #  error ADC module not implemented currently for your device (only incomplete preliminary Datasheet available)
00109 #endif // ...
00110 
00111 /* this is not used for the moment */
00112 #if ( defined (__AVR_ATmega16__) || defined (__AVR_ATmega32__)   \
00113     || defined (__AVR_ATmega8535__) )
00114     
00115 #  define ADTS_IN_SFIOR
00116 #endif // ...
00117 
00118 /* this is a pity, on these devices, two bits are relocated */
00119 #if ( defined (__AVR_ATtiny24__) || defined (__AVR_ATtiny44__)   \
00120     || defined (__AVR_ATtiny84__) )
00121     
00122 #  define ADLAR_IN_ADCSRB
00123 #  define MUX5_IN_ADMUX
00124   
00125 #  undef ADLAR_MASK_IN_CONFIG
00126 #  define ADLAR_MASK_IN_CONFIG 0x0100
00127 #endif // ...
00128 
00129 /* additional mux5, this time at another location */
00130 #if ( defined (__AVR_ATmega640__) \
00131     || defined (__AVR_ATmega1280__)  || defined (__AVR_ATmega1281__)   \
00132     || defined (__AVR_ATmega2560__)  || defined (__AVR_ATmega2561__)   )
00133     
00134 #  define MUX5_IN_ADCSRB
00135 
00136 #  undef MUX5_MASK_IN_CONFIG
00137 #  define MUX5_MASK_IN_CONFIG 0x0100
00138 #endif // ...
00139 
00140 // substitute
00141 #ifndef ADFR
00142 #define ADFR ADATE
00143 #endif
00144 
00145 
00146 
00147 /* ------------------------------------------------------------------------------------
00148    ----------------------------   REF SELECTION   -------------------------------------
00149    ------------------------------------------------------------------------------------ */
00150 /*
00151 ----------
00152 REFS1-0 bits : 
00153 0 : AREF is reference
00154 1 : AVCC is reference
00155 2 : internal reference2 (rarely available)
00156 3 : internal reference1 (2.56 or 1.1 V, depends on AVR type, see DS)
00157 
00158 VREF2 is available on : ATM164 ATM324 ATM644 ATM640 ATM1280 ATM1281 ATM2561
00159 VREF2 is without external cap on : ATtiny24-44-84
00160 more options on ATtiny25-45-85, not implmented yet
00161 ----------
00162 */
00163 
00164 #define ADC_REF_AREF  (0 << REFS0)
00165 #define ADC_REF_AVCC  (1 << REFS0)
00166 #define ADC_REF_VREF2 (2 << REFS0)
00167 #define ADC_REF_VREF  (3 << REFS0)
00168 
00169 
00170 
00171 /* ------------------------------------------------------------------------------------
00172    ----------------------------   MUX  ------------------------------------------------
00173    ------------------------------------------------------------------------------------ */
00174 
00175 
00176 
00179 /* lacking configs on some devices : 
00180 
00181 
00182 no gain stages : ATM165 ATM169 aTM329 ATM3290 ATM649 ATM6490
00183 no gain and no differential stages : ATM48 ATM88 ATM168 ATM8
00184 
00185 */
00186 #if ( defined (__AVR_ATmega165__)     \
00187     || defined (__AVR_ATmega169__) || defined (__AVR_ATmega329__) || defined (__AVR_ATmega3290__) \
00188     || defined (__AVR_ATmega649__) || defined (__AVR_ATmega6490__) )
00189 
00190 #  define MUX_NO_GAINS
00191 #endif // ...
00192 
00193 /*   we let a bit more in the config, not a problem, this will just set the reserved bit, with no effect */
00194 #if ( defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)  \
00195     || defined (__AVR_ATmega8__) )
00196 
00197 #  define MUX_NO_GAINS
00198 #  define MUX_NO_DIFF
00199   
00200 #endif // ...
00201 
00202 
00203 
00204 /* 0x20 + 0x0-0x7 : individual channel 8 to 15 (ATM640 ATM1280 ATM1281 ATM2561 only !!) */
00205 
00206 #if ( defined (__AVR_ATmega640__) || defined (__AVR_ATmega1280__) || defined (__AVR_ATmega1281__) \
00207     || defined (__AVR_ATmega2561__) || defined (__AVR_ATmega2560__) )
00208 
00209 
00210 #  define MUX_ADC8   ((0 <<MUX0) | MUX5_MASK_IN_CONFIG)
00211 #  define MUX_ADC9   ((1 <<MUX0) | MUX5_MASK_IN_CONFIG)
00212 #  define MUX_ADC10  ((2 <<MUX0) | MUX5_MASK_IN_CONFIG)
00213 #  define MUX_ADC11  ((3 <<MUX0) | MUX5_MASK_IN_CONFIG)
00214 #  define MUX_ADC12  ((4 <<MUX0) | MUX5_MASK_IN_CONFIG)
00215 #  define MUX_ADC13  ((5 <<MUX0) | MUX5_MASK_IN_CONFIG)
00216 #  define MUX_ADC14  ((6 <<MUX0) | MUX5_MASK_IN_CONFIG)
00217 #  define MUX_ADC15  ((7 <<MUX0) | MUX5_MASK_IN_CONFIG)
00218   
00219 #endif // ...
00220 
00221 /*
00222 AT30PWM2 &3 : only 4 MUX bits, as follow : 
00223 0x0 - 0xA : individual channel 0 to 10
00224 0xB : amplifier0
00225 0xC : amplifier1
00226 0xE : Vbg
00227 0xF : GND
00228 
00229   we let a bit more in the config, not a problem, this will just set the reserved bit, with no effect
00230 */
00231 #if ( defined (__AVR_ATmega48__) || defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__)  \
00232     || defined (__AVR_ATmega8__) )
00233 
00234 #  define MUX_NO_GAINS
00235 #  define MUX_NO_DIFF
00236   
00237 #  define MUX_AMP0 (0xB<<MUX0)
00238 #  define MUX_AMP1 (0xC<<MUX0)
00239   
00240 #endif // ...
00241 
00243 /*
00244 ATtiny13 : only 4 inputs, no gain, no diff, no ref voltage
00245 ATtiny15 : 
00246 
00247 0x0 - 0x3 : individual channel
00248 0x4 : ADC2-ADC2
00249 0x5 : (ADC2 - ADC2) *20
00250 0x6 : ADC2-ADC3
00251 0x7 : (ADC2 - ADC3) *20
00252 
00253 ATtiny24-44-84 : different table, not implemented yet
00254 ATtiny25-45-85 : different table, not implemented yet
00255 ATtiny26       : different table, not implemented yet
00256 ATUSBxxx       : different gains not implemanted yet, diffs available
00257 
00258 TO IMPLEMENT FULLY!!
00259 yet these devices generate a warning, and select the default table, limited to 8 inputs 
00260 
00261 */
00262 
00263 #if ( defined (__AVR_ATtiny13__) || defined (__AVR_ATtiny15__) \
00264     || defined (__AVR_ATtiny24__) || defined (__AVR_ATtiny44__) || defined (__AVR_ATtiny84__) \
00265     || defined (__AVR_ATtiny25__) || defined (__AVR_ATtiny45__) || defined (__AVR_ATtiny85__) \
00266     || defined (__AVR_ATtiny26__)   \
00267     || defined (__AVR_AT90USB1286__) || defined (__AVR_AT90USB1287__) \
00268     || defined (__AVR_AT90USB646__) || defined (__AVR_AT90USB647__) )
00269     
00270 #  warning The ADC MUX table of your device is not fully defined, some inputs could not work correctly, see adc_archs.h
00271   
00272 #  define MUX_NO_GAINS
00273 #  define MUX_NO_DIFF
00274   
00275 #endif // ...
00276 
00277 
00278 
00279 /*
00280 currently implemented STD table is following : 
00281 
00282 MUX4-0 bits : 
00283 0x0 - 0x7 : individual channel
00284 
00285 01000 : (ADC0 - ADC0) * 10
00286 01001 : (ADC1 - ADC0) * 10
00287 01010 : (ADC0 - ADC0) * 200
00288 01011 : (ADC1 - ADC0) * 200
00289 
00290 01100 : (ADC2 - ADC2) * 10
00291 01101 : (ADC3 - ADC2) * 10
00292 01110 : (ADC2 - ADC2) * 200
00293 01111 : (ADC3 - ADC2) * 200
00294 
00295 10000 + 0x0-0x7 : ADCx - ADC1
00296 11000 + 0x0-0x5 : ADCx - ADC2
00297 
00298 0x1E  : internal VBG reference (1.22V)
00299 0x1F  : GND
00300 
00301 
00302 */
00303 
00304 #ifndef MUX_NON_STD
00305 
00306 #  define MUX_ADC0 (0 <<MUX0)
00307 #  define MUX_ADC1 (1 <<MUX0)
00308 #  define MUX_ADC2 (2 <<MUX0)
00309 #  define MUX_ADC3 (3 <<MUX0)
00310 #  define MUX_ADC4 (4 <<MUX0)
00311 #  define MUX_ADC5 (5 <<MUX0)
00312 #  define MUX_ADC6 (6 <<MUX0)
00313 #  define MUX_ADC7 (7 <<MUX0)
00314 
00315 #  ifndef MUX_NO_GAINS
00316 #    define MUX_ADC0_ADC0_GAIN10  ((0x8 <<MUX0) | ADC_RESULT_SIGNED ) /* specifies that the result is in signed mode */
00317 #    define MUX_ADC1_ADC0_GAIN10  ((0x9 <<MUX0) | ADC_RESULT_SIGNED )
00318 #    define MUX_ADC0_ADC0_GAIN200 ((0xA <<MUX0) | ADC_RESULT_SIGNED )
00319 #    define MUX_ADC1_ADC0_GAIN200 ((0xB <<MUX0) | ADC_RESULT_SIGNED )
00320 
00321 #    define MUX_ADC2_ADC2_GAIN10  ((0xC <<MUX0) | ADC_RESULT_SIGNED )
00322 #    define MUX_ADC3_ADC2_GAIN10  ((0xD <<MUX0) | ADC_RESULT_SIGNED )
00323 #    define MUX_ADC2_ADC2_GAIN200 ((0xE <<MUX0) | ADC_RESULT_SIGNED )
00324 #    define MUX_ADC3_ADC2_GAIN200 ((0xF <<MUX0) | ADC_RESULT_SIGNED )
00325 #  endif // MUX_NO_GAINS
00326   
00327 #  ifndef MUX_NO_DIFF
00328 #    define MUX_ADC0_ADC1 ((0x10 <<MUX0) | ADC_RESULT_SIGNED )
00329 #    define MUX_ADC1_ADC1 ((0x11 <<MUX0) | ADC_RESULT_SIGNED )
00330 #    define MUX_ADC2_ADC1 ((0x12 <<MUX0) | ADC_RESULT_SIGNED )
00331 #    define MUX_ADC3_ADC1 ((0x13 <<MUX0) | ADC_RESULT_SIGNED )
00332 #    define MUX_ADC4_ADC1 ((0x14 <<MUX0) | ADC_RESULT_SIGNED )
00333 #    define MUX_ADC5_ADC1 ((0x15 <<MUX0) | ADC_RESULT_SIGNED )
00334 #    define MUX_ADC6_ADC1 ((0x16 <<MUX0) | ADC_RESULT_SIGNED )
00335 #    define MUX_ADC7_ADC1 ((0x17 <<MUX0) | ADC_RESULT_SIGNED )
00336     
00337 #    define MUX_ADC0_ADC2 ((0x18 <<MUX0) | ADC_RESULT_SIGNED )
00338 #    define MUX_ADC1_ADC2 ((0x19 <<MUX0) | ADC_RESULT_SIGNED )
00339 #    define MUX_ADC2_ADC2 ((0x1A <<MUX0) | ADC_RESULT_SIGNED )
00340 #    define MUX_ADC3_ADC2 ((0x1B <<MUX0) | ADC_RESULT_SIGNED )
00341 #    define MUX_ADC4_ADC2 ((0x1C <<MUX0) | ADC_RESULT_SIGNED )
00342 #    define MUX_ADC5_ADC2 ((0x1D <<MUX0) | ADC_RESULT_SIGNED )
00343 #    define MUX_ADC6_ADC2 ((0x1E <<MUX0) | ADC_RESULT_SIGNED )
00344 #    define MUX_ADC7_ADC2 ((0x1F <<MUX0) | ADC_RESULT_SIGNED )
00345 #  endif // MUX_NO_DIFF
00346   
00347 #  ifndef MUX5
00348 #    define MUX_VBG (0x1E <<MUX0)
00349 #    define MUX_GND (0x1F <<MUX0)
00350 #  else
00351 #    define MUX_VBG ((0x1E <<MUX0) | MUX5_MASK_IN_CONFIG)
00352 #    define MUX_GND ((0x1F <<MUX0) | MUX5_MASK_IN_CONFIG)
00353 #  endif // MUX5
00354 
00355 #endif // MUX_NON_STD
00356 
00357 
00358 
00359 
00360 /* ------------------------------------------------------------------------------------
00361    ----------------------------   PRESCALER   -----------------------------------------
00362    ------------------------------------------------------------------------------------ */
00363 
00364 /*
00365 ----------
00366 ADPS bits : 
00367 
00368 0 : prescaler = 2
00369 1 : prescaler = 2
00370 2 : prescaler = 4
00371 3 : prescaler = 8
00372 4 : prescaler = 16
00373 5 : prescaler = 32
00374 6 : prescaler = 64
00375 7 : prescaler = 128
00376 
00377 This table is yet totally standard 
00378 the selection is based on the quartz frequency, given in autoconf.h
00379 
00380 */
00381 
00382 #include <autoconf.h>
00383 
00384 #if ( CONFIG_QUARTZ < 100000l)
00385 #  warning your clock is too slow, the ADC result is not guaranted
00386 #endif
00387 
00388 #if (CONFIG_QUARTZ <= 400000l)      // up to 400 kHz : PS = 2
00389 #  define ADC_PRESCALE 0
00390 #elif (CONFIG_QUARTZ <= 800000l)   // up to 800 kHz : PS = 4
00391 #  define ADC_PRESCALE 2
00392 #elif (CONFIG_QUARTZ <= 1600000l)  // up to 1.6 MHz : PS = 8
00393 #  define ADC_PRESCALE 3
00394 #elif (CONFIG_QUARTZ <= 3200000l)  // up to 3.2 MHz : PS = 16
00395 #  define ADC_PRESCALE 4
00396 #elif (CONFIG_QUARTZ <= 6400000l)  // up to 6.4 MHz : PS = 32
00397 #  define ADC_PRESCALE 5
00398 #elif (CONFIG_QUARTZ <= 12800000l) // up to 12.8 MHz : PS = 64
00399 #  define ADC_PRESCALE 6
00400 #elif ( CONFIG_QUARTZ <= 25600000l) // up to 25.6 MHz : PS = 128
00401 #  define ADC_PRESCALE 7
00402 #else
00403 #  define ADC_PRESCALE 7
00404 #  warning your clock is too fast, the ADC result is not guaranted
00405 #endif
00406 
00407 
00408 
00409 
00410 
00411 
00412 #endif // _ADC_ARCHS_
aversive_10-03-12/modules/hardware/adc/adc_archs.h
