00001 /* 00002 * Copyright Droids Corporation, Microb Technology, Eirbot (2009) 00003 * 00004 * This program is free software; you can redistribute it and/or modify 00005 * it under the terms of the GNU General Public License as published by 00006 * the Free Software Foundation; either version 2 of the License, or 00007 * (at your option) any later version. 00008 * 00009 * This program is distributed in the hope that it will be useful, 00010 * but WITHOUT ANY WARRANTY; without even the implied warranty of 00011 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 00012 * GNU General Public License for more details. 00013 * 00014 * You should have received a copy of the GNU General Public License 00015 * along with this program; if not, write to the Free Software 00016 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 00017 * 00018 * Revision : $Id $ 00019 * 00020 */ 00021 00022 /* WARNING : this file is automatically generated by scripts. 00023 * You should not edit it. If you find something wrong in it, 00024 * write to zer0@droids-corp.org */ 00025 00026 00027 00028 /* available timers */ 00029 00030 /* overflow interrupt number */ 00031 #define SIG_OVERFLOW_TOTAL_NUM 0 00032 00033 /* output compare interrupt number */ 00034 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0 00035 00036 /* Pwm nums */ 00037 #define PWM_TOTAL_NUM 0 00038 00039 /* input capture interrupt number */ 00040 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0 00041 00042 00043 /* SPH */ 00044 #define SP8_REG SPH 00045 #define SP9_REG SPH 00046 #define SP10_REG SPH 00047 #define SP11_REG SPH 00048 #define SP12_REG SPH 00049 #define SP13_REG SPH 00050 #define SP14_REG SPH 00051 #define SP15_REG SPH 00052 00053 /* SPL */ 00054 #define SP0_REG SPL 00055 #define SP1_REG SPL 00056 #define SP2_REG SPL 00057 #define SP3_REG SPL 00058 #define SP4_REG SPL 00059 #define SP5_REG SPL 00060 #define SP6_REG SPL 00061 #define SP7_REG SPL 00062 00063 /* SREG */ 00064 #define C_REG SREG 00065 #define Z_REG SREG 00066 #define N_REG SREG 00067 #define V_REG SREG 00068 #define S_REG SREG 00069 #define H_REG SREG 00070 #define T_REG SREG 00071 #define I_REG SREG 00072 00073 /* pins mapping */ 00074
1.5.6