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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_2 2
00050 #define TIMER1_PRESCALER_DIV_4 3
00051 #define TIMER1_PRESCALER_DIV_8 4
00052 #define TIMER1_PRESCALER_DIV_16 5
00053 #define TIMER1_PRESCALER_DIV_32 6
00054 #define TIMER1_PRESCALER_DIV_64 7
00055 #define TIMER1_PRESCALER_DIV_128 8
00056 #define TIMER1_PRESCALER_DIV_256 9
00057 #define TIMER1_PRESCALER_DIV_512 10
00058 #define TIMER1_PRESCALER_DIV_1024 11
00059 #define TIMER1_PRESCALER_DIV_2048 12
00060 #define TIMER1_PRESCALER_DIV_4096 13
00061 #define TIMER1_PRESCALER_DIV_8192 14
00062 #define TIMER1_PRESCALER_DIV_16384 15
00063
00064 #define TIMER1_PRESCALER_REG_0 0
00065 #define TIMER1_PRESCALER_REG_1 1
00066 #define TIMER1_PRESCALER_REG_2 2
00067 #define TIMER1_PRESCALER_REG_3 4
00068 #define TIMER1_PRESCALER_REG_4 8
00069 #define TIMER1_PRESCALER_REG_5 16
00070 #define TIMER1_PRESCALER_REG_6 32
00071 #define TIMER1_PRESCALER_REG_7 64
00072 #define TIMER1_PRESCALER_REG_8 128
00073 #define TIMER1_PRESCALER_REG_9 256
00074 #define TIMER1_PRESCALER_REG_10 512
00075 #define TIMER1_PRESCALER_REG_11 1024
00076 #define TIMER1_PRESCALER_REG_12 2048
00077 #define TIMER1_PRESCALER_REG_13 4096
00078 #define TIMER1_PRESCALER_REG_14 8192
00079 #define TIMER1_PRESCALER_REG_15 16384
00080
00081
00082
00083 #define TIMER0_AVAILABLE
00084 #define TIMER0A_AVAILABLE
00085 #define TIMER0B_AVAILABLE
00086 #define TIMER1_AVAILABLE
00087 #define TIMER1A_AVAILABLE
00088 #define TIMER1B_AVAILABLE
00089
00090
00091 #define SIG_OVERFLOW0_NUM 0
00092 #define SIG_OVERFLOW1_NUM 1
00093 #define SIG_OVERFLOW_TOTAL_NUM 2
00094
00095
00096 #define SIG_OUTPUT_COMPARE0A_NUM 0
00097 #define SIG_OUTPUT_COMPARE0B_NUM 1
00098 #define SIG_OUTPUT_COMPARE1_NUM 2
00099 #define SIG_OUTPUT_COMPARE1A_NUM 3
00100 #define SIG_OUTPUT_COMPARE1B_NUM 4
00101 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
00102
00103
00104 #define PWM0A_NUM 0
00105 #define PWM0B_NUM 1
00106 #define PWM1_NUM 2
00107 #define PWM1A_NUM 3
00108 #define PWM1B_NUM 4
00109 #define PWM_TOTAL_NUM 5
00110
00111
00112 #define SIG_INPUT_CAPTURE0_NUM 0
00113 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00114
00115
00116
00117 #define CLKPS0_REG CLKPR
00118 #define CLKPS1_REG CLKPR
00119 #define CLKPS2_REG CLKPR
00120 #define CLKPS3_REG CLKPR
00121 #define CLKPCE_REG CLKPR
00122
00123
00124 #define WDP0_REG WDTCR
00125 #define WDP1_REG WDTCR
00126 #define WDP2_REG WDTCR
00127 #define WDE_REG WDTCR
00128 #define WDCE_REG WDTCR
00129 #define WDP3_REG WDTCR
00130 #define WDIE_REG WDTCR
00131 #define WDIF_REG WDTCR
00132
00133
00134 #define PCIE0_REG GIMSK
00135 #define PCIE1_REG GIMSK
00136 #define INT0_REG GIMSK
00137 #define INT1_REG GIMSK
00138
00139
00140 #define ADC0D_REG DIDR0
00141 #define ADC1D_REG DIDR0
00142 #define ADC2D_REG DIDR0
00143 #define AREFD_REG DIDR0
00144 #define ADC3D_REG DIDR0
00145 #define ADC4D_REG DIDR0
00146 #define ADC5D_REG DIDR0
00147 #define ADC6D_REG DIDR0
00148
00149
00150 #define MUX0_REG ADMUX
00151 #define MUX1_REG ADMUX
00152 #define MUX2_REG ADMUX
00153 #define MUX3_REG ADMUX
00154 #define MUX4_REG ADMUX
00155 #define ADLAR_REG ADMUX
00156 #define REFS0_REG ADMUX
00157 #define REFS1_REG ADMUX
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171
00172
00173
00174
00175
00176
00177
00178
00179
00180 #define DDB0_REG DDRB
00181 #define DDB1_REG DDRB
00182 #define DDB2_REG DDRB
00183 #define DDB3_REG DDRB
00184 #define DDB4_REG DDRB
00185 #define DDB5_REG DDRB
00186 #define DDB6_REG DDRB
00187 #define DDB7_REG DDRB
00188
00189
00190 #define EEDR0_REG EEDR
00191 #define EEDR1_REG EEDR
00192 #define EEDR2_REG EEDR
00193 #define EEDR3_REG EEDR
00194 #define EEDR4_REG EEDR
00195 #define EEDR5_REG EEDR
00196 #define EEDR6_REG EEDR
00197 #define EEDR7_REG EEDR
00198
00199
00200 #define WGM10_REG TCCR1D
00201 #define WGM11_REG TCCR1D
00202 #define FPF1_REG TCCR1D
00203 #define FPAC1_REG TCCR1D
00204 #define FPES1_REG TCCR1D
00205 #define FPNC1_REG TCCR1D
00206 #define FPEN1_REG TCCR1D
00207 #define FPIE1_REG TCCR1D
00208
00209
00210 #define ISC00_REG MCUCR
00211 #define ISC01_REG MCUCR
00212 #define SM0_REG MCUCR
00213 #define SM1_REG MCUCR
00214 #define SE_REG MCUCR
00215 #define PUD_REG MCUCR
00216
00217
00218 #define PWM1B_REG TCCR1A
00219 #define PWM1A_REG TCCR1A
00220 #define FOC1B_REG TCCR1A
00221 #define FOC1A_REG TCCR1A
00222 #define COM1B0_REG TCCR1A
00223 #define COM1B1_REG TCCR1A
00224 #define COM1A0_REG TCCR1A
00225 #define COM1A1_REG TCCR1A
00226
00227
00228 #define PWM1D_REG TCCR1C
00229 #define FOC1D_REG TCCR1C
00230 #define COM1D0_REG TCCR1C
00231 #define COM1D1_REG TCCR1C
00232 #define COM1B0S_REG TCCR1C
00233 #define COM1B1S_REG TCCR1C
00234 #define COM1A0S_REG TCCR1C
00235 #define COM1A1S_REG TCCR1C
00236
00237
00238 #define CS10_REG TCCR1B
00239 #define CS11_REG TCCR1B
00240 #define CS12_REG TCCR1B
00241 #define CS13_REG TCCR1B
00242 #define DTPS10_REG TCCR1B
00243 #define DTPS11_REG TCCR1B
00244 #define PSR1_REG TCCR1B
00245
00246
00247 #define PCIF_REG GIFR
00248 #define INTF0_REG GIFR
00249 #define INTF1_REG GIFR
00250
00251
00252 #define TICIE0_REG TIMSK
00253 #define TOIE0_REG TIMSK
00254 #define OCIE0B_REG TIMSK
00255 #define OCIE0A_REG TIMSK
00256 #define TOIE1_REG TIMSK
00257 #define OCIE1B_REG TIMSK
00258 #define OCIE1A_REG TIMSK
00259 #define OCIE1D_REG TIMSK
00260
00261
00262 #define DDA0_REG DDRA
00263 #define DDA1_REG DDRA
00264 #define DDA2_REG DDRA
00265 #define DDA3_REG DDRA
00266 #define DDA4_REG DDRA
00267 #define DDA5_REG DDRA
00268 #define DDA6_REG DDRA
00269 #define DDA7_REG DDRA
00270
00271
00272 #define ADPS0_REG ADCSRA
00273 #define ADPS1_REG ADCSRA
00274 #define ADPS2_REG ADCSRA
00275 #define ADIE_REG ADCSRA
00276 #define ADIF_REG ADCSRA
00277 #define ADATE_REG ADCSRA
00278 #define ADSC_REG ADCSRA
00279 #define ADEN_REG ADCSRA
00280
00281
00282 #define ACM0_REG ACSRB
00283 #define ACM1_REG ACSRB
00284 #define ACM2_REG ACSRB
00285 #define HLEV_REG ACSRB
00286 #define HSEL_REG ACSRB
00287
00288
00289 #define ADTS0_REG ADCSRB
00290 #define ADTS1_REG ADCSRB
00291 #define ADTS2_REG ADCSRB
00292 #define MUX5_REG ADCSRB
00293 #define REFS2_REG ADCSRB
00294 #define IPR_REG ADCSRB
00295 #define GSEL_REG ADCSRB
00296 #define BIN_REG ADCSRB
00297
00298
00299 #define TC18_REG TC1H
00300 #define TC19_REG TC1H
00301
00302
00303 #define OC1OE0_REG TCCR1E
00304 #define OC1OE1_REG TCCR1E
00305 #define OC1OE2_REG TCCR1E
00306 #define OC1OE3_REG TCCR1E
00307 #define OC1OE4_REG TCCR1E
00308 #define OC1OE5_REG TCCR1E
00309
00310
00311
00312
00313
00314
00315
00316
00317
00318
00319
00320
00321
00322
00323
00324
00325
00326
00327
00328
00329
00330
00331 #define SP8_REG SPH
00332 #define SP9_REG SPH
00333
00334
00335 #define SP0_REG SPL
00336 #define SP1_REG SPL
00337 #define SP2_REG SPL
00338 #define SP3_REG SPL
00339 #define SP4_REG SPL
00340 #define SP5_REG SPL
00341 #define SP6_REG SPL
00342 #define SP7_REG SPL
00343
00344
00345 #define PRADC_REG PRR
00346 #define PRUSI_REG PRR
00347 #define PRTIM0_REG PRR
00348 #define PRTIM1_REG PRR
00349
00350
00351 #define GPIOR10_REG GPIOR1
00352 #define GPIOR11_REG GPIOR1
00353 #define GPIOR12_REG GPIOR1
00354 #define GPIOR13_REG GPIOR1
00355 #define GPIOR14_REG GPIOR1
00356 #define GPIOR15_REG GPIOR1
00357 #define GPIOR16_REG GPIOR1
00358 #define GPIOR17_REG GPIOR1
00359
00360
00361 #define GPIOR00_REG GPIOR0
00362 #define GPIOR01_REG GPIOR0
00363 #define GPIOR02_REG GPIOR0
00364 #define GPIOR03_REG GPIOR0
00365 #define GPIOR04_REG GPIOR0
00366 #define GPIOR05_REG GPIOR0
00367 #define GPIOR06_REG GPIOR0
00368 #define GPIOR07_REG GPIOR0
00369
00370
00371 #define USITC_REG USICR
00372 #define USICLK_REG USICR
00373 #define USICS0_REG USICR
00374 #define USICS1_REG USICR
00375 #define USIWM0_REG USICR
00376 #define USIWM1_REG USICR
00377 #define USIOIE_REG USICR
00378 #define USISIE_REG USICR
00379
00380
00381 #define PORF_REG MCUSR
00382 #define EXTRF_REG MCUSR
00383 #define BORF_REG MCUSR
00384 #define WDRF_REG MCUSR
00385
00386
00387 #define EERE_REG EECR
00388 #define EEPE_REG EECR
00389 #define EEMPE_REG EECR
00390 #define EERIE_REG EECR
00391 #define EEPM0_REG EECR
00392 #define EEPM1_REG EECR
00393
00394
00395 #define SPMEN_REG SPMCSR
00396 #define PGERS_REG SPMCSR
00397 #define PGWRT_REG SPMCSR
00398 #define RFLB_REG SPMCSR
00399 #define CTPB_REG SPMCSR
00400
00401
00402 #define CAL0_REG OSCCAL
00403 #define CAL1_REG OSCCAL
00404 #define CAL2_REG OSCCAL
00405 #define CAL3_REG OSCCAL
00406 #define CAL4_REG OSCCAL
00407 #define CAL5_REG OSCCAL
00408 #define CAL6_REG OSCCAL
00409 #define CAL7_REG OSCCAL
00410
00411
00412 #define ADCL0_REG ADCL
00413 #define ADCL1_REG ADCL
00414 #define ADCL2_REG ADCL
00415 #define ADCL3_REG ADCL
00416 #define ADCL4_REG ADCL
00417 #define ADCL5_REG ADCL
00418 #define ADCL6_REG ADCL
00419 #define ADCL7_REG ADCL
00420
00421
00422 #define USICNT0_REG USISR
00423 #define USICNT1_REG USISR
00424 #define USICNT2_REG USISR
00425 #define USICNT3_REG USISR
00426 #define USIDC_REG USISR
00427 #define USIPF_REG USISR
00428 #define USIOIF_REG USISR
00429 #define USISIF_REG USISR
00430
00431
00432 #define PORTB0_REG PORTB
00433 #define PORTB1_REG PORTB
00434 #define PORTB2_REG PORTB
00435 #define PORTB3_REG PORTB
00436 #define PORTB4_REG PORTB
00437 #define PORTB5_REG PORTB
00438 #define PORTB6_REG PORTB
00439 #define PORTB7_REG PORTB
00440
00441
00442 #define ADCH0_REG ADCH
00443 #define ADCH1_REG ADCH
00444 #define ADCH2_REG ADCH
00445 #define ADCH3_REG ADCH
00446 #define ADCH4_REG ADCH
00447 #define ADCH5_REG ADCH
00448 #define ADCH6_REG ADCH
00449 #define ADCH7_REG ADCH
00450
00451
00452 #define PORTA0_REG PORTA
00453 #define PORTA1_REG PORTA
00454 #define PORTA2_REG PORTA
00455 #define PORTA3_REG PORTA
00456 #define PORTA4_REG PORTA
00457 #define PORTA5_REG PORTA
00458 #define PORTA6_REG PORTA
00459 #define PORTA7_REG PORTA
00460
00461
00462 #define ACIS0_REG ACSRA
00463 #define ACIS1_REG ACSRA
00464 #define ACME_REG ACSRA
00465 #define ACIE_REG ACSRA
00466 #define ACI_REG ACSRA
00467 #define ACO_REG ACSRA
00468 #define ACBG_REG ACSRA
00469 #define ACD_REG ACSRA
00470
00471
00472 #define TC1H_0_REG TCNT1
00473 #define TC1H_1_REG TCNT1
00474 #define TC1H_2_REG TCNT1
00475 #define TC1H_3_REG TCNT1
00476 #define TC1H_4_REG TCNT1
00477 #define TC1H_5_REG TCNT1
00478 #define TC1H_6_REG TCNT1
00479 #define TC1H_7_REG TCNT1
00480
00481
00482 #define EEAR0_REG EEARL
00483 #define EEAR1_REG EEARL
00484 #define EEAR2_REG EEARL
00485 #define EEAR3_REG EEARL
00486 #define EEAR4_REG EEARL
00487 #define EEAR5_REG EEARL
00488 #define EEAR6_REG EEARL
00489 #define EEAR7_REG EEARL
00490
00491
00492 #define C_REG SREG
00493 #define Z_REG SREG
00494 #define N_REG SREG
00495 #define V_REG SREG
00496 #define S_REG SREG
00497 #define H_REG SREG
00498 #define T_REG SREG
00499 #define I_REG SREG
00500
00501
00502 #define CS00_REG TCCR0B
00503 #define CS01_REG TCCR0B
00504 #define CS02_REG TCCR0B
00505 #define PSR0_REG TCCR0B
00506 #define TSM_REG TCCR0B
00507
00508
00509 #define ICF0_REG TIFR
00510 #define TOV0_REG TIFR
00511 #define OCF0B_REG TIFR
00512 #define OCF0A_REG TIFR
00513 #define TOV1_REG TIFR
00514 #define OCF1B_REG TIFR
00515 #define OCF1A_REG TIFR
00516 #define OCF1D_REG TIFR
00517
00518
00519 #define WGM00_REG TCCR0A
00520 #define ACIC0_REG TCCR0A
00521 #define ICES0_REG TCCR0A
00522 #define ICNC0_REG TCCR0A
00523 #define ICEN0_REG TCCR0A
00524 #define TCW0_REG TCCR0A
00525
00526
00527 #define EEAR8_REG EEARH
00528
00529
00530 #define PLOCK_REG PLLCSR
00531 #define PLLE_REG PLLCSR
00532 #define PCKE_REG PLLCSR
00533 #define LSM_REG PLLCSR
00534
00535
00536 #define GPIOR20_REG GPIOR2
00537 #define GPIOR21_REG GPIOR2
00538 #define GPIOR22_REG GPIOR2
00539 #define GPIOR23_REG GPIOR2
00540 #define GPIOR24_REG GPIOR2
00541 #define GPIOR25_REG GPIOR2
00542 #define GPIOR26_REG GPIOR2
00543 #define GPIOR27_REG GPIOR2
00544
00545
00546 #define PCINT0_REG PCMSK0
00547 #define PCINT1_REG PCMSK0
00548 #define PCINT2_REG PCMSK0
00549 #define PCINT3_REG PCMSK0
00550 #define PCINT4_REG PCMSK0
00551 #define PCINT5_REG PCMSK0
00552 #define PCINT6_REG PCMSK0
00553 #define PCINT7_REG PCMSK0
00554
00555
00556 #define PCINT8_REG PCMSK1
00557 #define PCINT9_REG PCMSK1
00558 #define PCINT10_REG PCMSK1
00559 #define PCINT11_REG PCMSK1
00560 #define PCINT12_REG PCMSK1
00561 #define PCINT13_REG PCMSK1
00562 #define PCINT14_REG PCMSK1
00563 #define PCINT15_REG PCMSK1
00564
00565
00566 #define DWDR0_REG DWDR
00567 #define DWDR1_REG DWDR
00568 #define DWDR2_REG DWDR
00569 #define DWDR3_REG DWDR
00570 #define DWDR4_REG DWDR
00571 #define DWDR5_REG DWDR
00572 #define DWDR6_REG DWDR
00573 #define DWDR7_REG DWDR
00574
00575
00576 #define OCR1D0_REG OCR1D
00577 #define OCR1D1_REG OCR1D
00578 #define OCR1D2_REG OCR1D
00579 #define OCR1D3_REG OCR1D
00580 #define OCR1D4_REG OCR1D
00581 #define OCR1D5_REG OCR1D
00582 #define OCR1D6_REG OCR1D
00583
00584
00585
00586 #define OCR1B0_REG OCR1B
00587 #define OCR1B1_REG OCR1B
00588 #define OCR1B2_REG OCR1B
00589 #define OCR1B3_REG OCR1B
00590 #define OCR1B4_REG OCR1B
00591 #define OCR1B5_REG OCR1B
00592 #define OCR1B6_REG OCR1B
00593 #define OCR1B7_REG OCR1B
00594
00595
00596 #define OCR1C0_REG OCR1C
00597 #define OCR1C1_REG OCR1C
00598 #define OCR1C2_REG OCR1C
00599 #define OCR1C3_REG OCR1C
00600 #define OCR1C4_REG OCR1C
00601 #define OCR1C5_REG OCR1C
00602 #define OCR1C6_REG OCR1C
00603
00604
00605
00606 #define OCR1A0_REG OCR1A
00607 #define OCR1A1_REG OCR1A
00608 #define OCR1A2_REG OCR1A
00609 #define OCR1A3_REG OCR1A
00610 #define OCR1A4_REG OCR1A
00611 #define OCR1A5_REG OCR1A
00612 #define OCR1A6_REG OCR1A
00613 #define OCR1A7_REG OCR1A
00614
00615
00616 #define USIPOS_REG USIPP
00617
00618
00619 #define PINB0_REG PINB
00620 #define PINB1_REG PINB
00621 #define PINB2_REG PINB
00622 #define PINB3_REG PINB
00623 #define PINB4_REG PINB
00624 #define PINB5_REG PINB
00625 #define PINB6_REG PINB
00626 #define PINB7_REG PINB
00627
00628
00629 #define USIBR0_REG USIBR
00630 #define USIBR1_REG USIBR
00631 #define USIBR2_REG USIBR
00632 #define USIBR3_REG USIBR
00633 #define USIBR4_REG USIBR
00634 #define USIBR5_REG USIBR
00635 #define USIBR6_REG USIBR
00636 #define USIBR7_REG USIBR
00637
00638
00639 #define DT1L0_REG DT1
00640 #define DT1L1_REG DT1
00641 #define DT1L2_REG DT1
00642 #define DT1L3_REG DT1
00643 #define DT1H0_REG DT1
00644 #define DT1H1_REG DT1
00645 #define DT1H2_REG DT1
00646 #define DT1H3_REG DT1
00647
00648
00649 #define PINA0_REG PINA
00650 #define PINA1_REG PINA
00651 #define PINA2_REG PINA
00652 #define PINA3_REG PINA
00653 #define PINA4_REG PINA
00654 #define PINA5_REG PINA
00655 #define PINA6_REG PINA
00656 #define PINA7_REG PINA
00657
00658
00659 #define USIDR0_REG USIDR
00660 #define USIDR1_REG USIDR
00661 #define USIDR2_REG USIDR
00662 #define USIDR3_REG USIDR
00663 #define USIDR4_REG USIDR
00664 #define USIDR5_REG USIDR
00665 #define USIDR6_REG USIDR
00666 #define USIDR7_REG USIDR
00667
00668
00669 #define ADC7D_REG DIDR1
00670 #define ADC8D_REG DIDR1
00671 #define ADC9D_REG DIDR1
00672 #define ADC10D_REG DIDR1
00673
00674
00675