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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER0A_AVAILABLE
00069 #define TIMER0B_AVAILABLE
00070 #define TIMER1_AVAILABLE
00071 #define TIMER1A_AVAILABLE
00072 #define TIMER1B_AVAILABLE
00073
00074
00075 #define SIG_OVERFLOW0_NUM 0
00076 #define SIG_OVERFLOW1_NUM 1
00077 #define SIG_OVERFLOW_TOTAL_NUM 2
00078
00079
00080 #define SIG_OUTPUT_COMPARE0A_NUM 0
00081 #define SIG_OUTPUT_COMPARE0B_NUM 1
00082 #define SIG_OUTPUT_COMPARE1A_NUM 2
00083 #define SIG_OUTPUT_COMPARE1B_NUM 3
00084 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00085
00086
00087 #define PWM0A_NUM 0
00088 #define PWM0B_NUM 1
00089 #define PWM1A_NUM 2
00090 #define PWM1B_NUM 3
00091 #define PWM_TOTAL_NUM 4
00092
00093
00094 #define SIG_INPUT_CAPTURE1_NUM 0
00095 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00096
00097
00098
00099 #define CLKPS0_REG CLKPR
00100 #define CLKPS1_REG CLKPR
00101 #define CLKPS2_REG CLKPR
00102 #define CLKPS3_REG CLKPR
00103 #define CLKPCE_REG CLKPR
00104
00105
00106 #define SP8_REG SPH
00107
00108
00109 #define PCIF0_REG PCIFR
00110 #define PCIF1_REG PCIFR
00111 #define PCIF2_REG PCIFR
00112 #define PCIF3_REG PCIFR
00113
00114
00115 #define MUX0_REG ADMUX
00116 #define MUX1_REG ADMUX
00117 #define MUX2_REG ADMUX
00118 #define MUX3_REG ADMUX
00119 #define ADLAR_REG ADMUX
00120 #define REFS0_REG ADMUX
00121 #define REFS1_REG ADMUX
00122
00123
00124 #define PUDA_REG PORTCR
00125 #define PUDB_REG PORTCR
00126 #define PUDC_REG PORTCR
00127 #define PUDD_REG PORTCR
00128 #define BBMA_REG PORTCR
00129 #define BBMB_REG PORTCR
00130 #define BBMC_REG PORTCR
00131 #define BBMD_REG PORTCR
00132
00133
00134 #define C_REG SREG
00135 #define Z_REG SREG
00136 #define N_REG SREG
00137 #define V_REG SREG
00138 #define S_REG SREG
00139 #define H_REG SREG
00140 #define T_REG SREG
00141 #define I_REG SREG
00142
00143
00144 #define DDB0_REG DDRB
00145 #define DDB1_REG DDRB
00146 #define DDB2_REG DDRB
00147 #define DDB3_REG DDRB
00148 #define DDB4_REG DDRB
00149 #define DDB5_REG DDRB
00150 #define DDB6_REG DDRB
00151 #define DDB7_REG DDRB
00152
00153
00154 #define WDP0_REG WDTCSR
00155 #define WDP1_REG WDTCSR
00156 #define WDP2_REG WDTCSR
00157 #define WDE_REG WDTCSR
00158 #define WDCE_REG WDTCSR
00159 #define WDP3_REG WDTCSR
00160 #define WDIE_REG WDTCSR
00161 #define WDIF_REG WDTCSR
00162
00163
00164 #define EEDR0_REG EEDR
00165 #define EEDR1_REG EEDR
00166 #define EEDR2_REG EEDR
00167 #define EEDR3_REG EEDR
00168 #define EEDR4_REG EEDR
00169 #define EEDR5_REG EEDR
00170 #define EEDR6_REG EEDR
00171 #define EEDR7_REG EEDR
00172
00173
00174 #define TWD0_REG TWDR
00175 #define TWD1_REG TWDR
00176 #define TWD2_REG TWDR
00177 #define TWD3_REG TWDR
00178 #define TWD4_REG TWDR
00179 #define TWD5_REG TWDR
00180 #define TWD6_REG TWDR
00181 #define TWD7_REG TWDR
00182
00183
00184 #define OCR0B_0_REG OCR0B
00185 #define OCR0B_1_REG OCR0B
00186 #define OCR0B_2_REG OCR0B
00187 #define OCR0B_3_REG OCR0B
00188 #define OCR0B_4_REG OCR0B
00189 #define OCR0B_5_REG OCR0B
00190 #define OCR0B_6_REG OCR0B
00191 #define OCR0B_7_REG OCR0B
00192
00193
00194 #define WGM10_REG TCCR1A
00195 #define WGM11_REG TCCR1A
00196 #define COM1B0_REG TCCR1A
00197 #define COM1B1_REG TCCR1A
00198 #define COM1A0_REG TCCR1A
00199 #define COM1A1_REG TCCR1A
00200
00201
00202 #define FOC1B_REG TCCR1C
00203 #define FOC1A_REG TCCR1C
00204
00205
00206 #define CS10_REG TCCR1B
00207 #define CS11_REG TCCR1B
00208 #define CS12_REG TCCR1B
00209 #define WGM12_REG TCCR1B
00210 #define WGM13_REG TCCR1B
00211 #define ICES1_REG TCCR1B
00212 #define ICNC1_REG TCCR1B
00213
00214
00215 #define OCR1AH0_REG OCR1AH
00216 #define OCR1AH1_REG OCR1AH
00217 #define OCR1AH2_REG OCR1AH
00218 #define OCR1AH3_REG OCR1AH
00219 #define OCR1AH4_REG OCR1AH
00220 #define OCR1AH5_REG OCR1AH
00221 #define OCR1AH6_REG OCR1AH
00222 #define OCR1AH7_REG OCR1AH
00223
00224
00225 #define PSRSYNC_REG GTCCR
00226 #define TSM_REG GTCCR
00227
00228
00229 #define DDA0_REG DDRA
00230 #define DDA1_REG DDRA
00231 #define DDA2_REG DDRA
00232 #define DDA3_REG DDRA
00233
00234
00235 #define ADPS0_REG ADCSRA
00236 #define ADPS1_REG ADCSRA
00237 #define ADPS2_REG ADCSRA
00238 #define ADIE_REG ADCSRA
00239 #define ADIF_REG ADCSRA
00240 #define ADATE_REG ADCSRA
00241 #define ADSC_REG ADCSRA
00242 #define ADEN_REG ADCSRA
00243
00244
00245 #define ADTS0_REG ADCSRB
00246 #define ADTS1_REG ADCSRB
00247 #define ADTS2_REG ADCSRB
00248 #define ACME_REG ADCSRB
00249
00250
00251 #define SPDR0_REG SPDR
00252 #define SPDR1_REG SPDR
00253 #define SPDR2_REG SPDR
00254 #define SPDR3_REG SPDR
00255 #define SPDR4_REG SPDR
00256 #define SPDR5_REG SPDR
00257 #define SPDR6_REG SPDR
00258 #define SPDR7_REG SPDR
00259
00260
00261 #define OCR0A_0_REG OCR0A
00262 #define OCR0A_1_REG OCR0A
00263 #define OCR0A_2_REG OCR0A
00264 #define OCR0A_3_REG OCR0A
00265 #define OCR0A_4_REG OCR0A
00266 #define OCR0A_5_REG OCR0A
00267 #define OCR0A_6_REG OCR0A
00268 #define OCR0A_7_REG OCR0A
00269
00270
00271 #define SPI2X_REG SPSR
00272 #define WCOL_REG SPSR
00273 #define SPIF_REG SPSR
00274
00275
00276 #define ACIS0_REG ACSR
00277 #define ACIS1_REG ACSR
00278 #define ACIC_REG ACSR
00279 #define ACIE_REG ACSR
00280 #define ACI_REG ACSR
00281 #define ACO_REG ACSR
00282 #define ACBG_REG ACSR
00283 #define ACD_REG ACSR
00284
00285
00286 #define ICR1H0_REG ICR1H
00287 #define ICR1H1_REG ICR1H
00288 #define ICR1H2_REG ICR1H
00289 #define ICR1H3_REG ICR1H
00290 #define ICR1H4_REG ICR1H
00291 #define ICR1H5_REG ICR1H
00292 #define ICR1H6_REG ICR1H
00293 #define ICR1H7_REG ICR1H
00294
00295
00296 #define OCR1BL0_REG OCR1BL
00297 #define OCR1BL1_REG OCR1BL
00298 #define OCR1BL2_REG OCR1BL
00299 #define OCR1BL3_REG OCR1BL
00300 #define OCR1BL4_REG OCR1BL
00301 #define OCR1BL5_REG OCR1BL
00302 #define OCR1BL6_REG OCR1BL
00303 #define OCR1BL7_REG OCR1BL
00304
00305
00306 #define ICR1L0_REG ICR1L
00307 #define ICR1L1_REG ICR1L
00308 #define ICR1L2_REG ICR1L
00309 #define ICR1L3_REG ICR1L
00310 #define ICR1L4_REG ICR1L
00311 #define ICR1L5_REG ICR1L
00312 #define ICR1L6_REG ICR1L
00313 #define ICR1L7_REG ICR1L
00314
00315
00316 #define OCR1BH0_REG OCR1BH
00317 #define OCR1BH1_REG OCR1BH
00318 #define OCR1BH2_REG OCR1BH
00319 #define OCR1BH3_REG OCR1BH
00320 #define OCR1BH4_REG OCR1BH
00321 #define OCR1BH5_REG OCR1BH
00322 #define OCR1BH6_REG OCR1BH
00323 #define OCR1BH7_REG OCR1BH
00324
00325
00326 #define PRADC_REG PRR
00327 #define PRSPI_REG PRR
00328 #define PRTIM1_REG PRR
00329 #define PRTIM0_REG PRR
00330 #define PRTWI_REG PRR
00331
00332
00333 #define GPIOR10_REG GPIOR1
00334 #define GPIOR11_REG GPIOR1
00335 #define GPIOR12_REG GPIOR1
00336 #define GPIOR13_REG GPIOR1
00337 #define GPIOR14_REG GPIOR1
00338 #define GPIOR15_REG GPIOR1
00339 #define GPIOR16_REG GPIOR1
00340 #define GPIOR17_REG GPIOR1
00341
00342
00343 #define SP0_REG SPL
00344 #define SP1_REG SPL
00345 #define SP2_REG SPL
00346 #define SP3_REG SPL
00347 #define SP4_REG SPL
00348 #define SP5_REG SPL
00349 #define SP6_REG SPL
00350 #define SP7_REG SPL
00351
00352
00353 #define TWBR0_REG TWBR
00354 #define TWBR1_REG TWBR
00355 #define TWBR2_REG TWBR
00356 #define TWBR3_REG TWBR
00357 #define TWBR4_REG TWBR
00358 #define TWBR5_REG TWBR
00359 #define TWBR6_REG TWBR
00360 #define TWBR7_REG TWBR
00361
00362
00363 #define PORTD0_REG PORTD
00364 #define PORTD1_REG PORTD
00365 #define PORTD2_REG PORTD
00366 #define PORTD3_REG PORTD
00367 #define PORTD4_REG PORTD
00368 #define PORTD5_REG PORTD
00369 #define PORTD6_REG PORTD
00370 #define PORTD7_REG PORTD
00371
00372
00373 #define PORF_REG MCUSR
00374 #define EXTRF_REG MCUSR
00375 #define BORF_REG MCUSR
00376 #define WDRF_REG MCUSR
00377
00378
00379 #define INT0_REG EIMSK
00380 #define INT1_REG EIMSK
00381
00382
00383 #define EERE_REG EECR
00384 #define EEPE_REG EECR
00385 #define EEMPE_REG EECR
00386 #define EERIE_REG EECR
00387 #define EEPM0_REG EECR
00388 #define EEPM1_REG EECR
00389
00390
00391 #define SELFPRGEN_REG SPMCSR
00392 #define PGERS_REG SPMCSR
00393 #define PGWRT_REG SPMCSR
00394 #define RFLB_REG SPMCSR
00395 #define CTPB_REG SPMCSR
00396 #define RWWSB_REG SPMCSR
00397
00398
00399 #define CAL0_REG OSCCAL
00400 #define CAL1_REG OSCCAL
00401 #define CAL2_REG OSCCAL
00402 #define CAL3_REG OSCCAL
00403 #define CAL4_REG OSCCAL
00404 #define CAL5_REG OSCCAL
00405 #define CAL6_REG OSCCAL
00406 #define CAL7_REG OSCCAL
00407
00408
00409 #define TCNT1L0_REG TCNT1L
00410 #define TCNT1L1_REG TCNT1L
00411 #define TCNT1L2_REG TCNT1L
00412 #define TCNT1L3_REG TCNT1L
00413 #define TCNT1L4_REG TCNT1L
00414 #define TCNT1L5_REG TCNT1L
00415 #define TCNT1L6_REG TCNT1L
00416 #define TCNT1L7_REG TCNT1L
00417
00418
00419 #define PORTB0_REG PORTB
00420 #define PORTB1_REG PORTB
00421 #define PORTB2_REG PORTB
00422 #define PORTB3_REG PORTB
00423 #define PORTB4_REG PORTB
00424 #define PORTB5_REG PORTB
00425 #define PORTB6_REG PORTB
00426 #define PORTB7_REG PORTB
00427
00428
00429 #define ADCL0_REG ADCL
00430 #define ADCL1_REG ADCL
00431 #define ADCL2_REG ADCL
00432 #define ADCL3_REG ADCL
00433 #define ADCL4_REG ADCL
00434 #define ADCL5_REG ADCL
00435 #define ADCL6_REG ADCL
00436 #define ADCL7_REG ADCL
00437
00438
00439 #define SE_REG SMCR
00440 #define SM0_REG SMCR
00441 #define SM1_REG SMCR
00442
00443
00444 #define TCNT1H0_REG TCNT1H
00445 #define TCNT1H1_REG TCNT1H
00446 #define TCNT1H2_REG TCNT1H
00447 #define TCNT1H3_REG TCNT1H
00448 #define TCNT1H4_REG TCNT1H
00449 #define TCNT1H5_REG TCNT1H
00450 #define TCNT1H6_REG TCNT1H
00451 #define TCNT1H7_REG TCNT1H
00452
00453
00454 #define PORTC0_REG PORTC
00455 #define PORTC1_REG PORTC
00456 #define PORTC2_REG PORTC
00457 #define PORTC3_REG PORTC
00458 #define PORTC4_REG PORTC
00459 #define PORTC5_REG PORTC
00460 #define PORTC6_REG PORTC
00461 #define PORTC7_REG PORTC
00462
00463
00464 #define ADCH0_REG ADCH
00465 #define ADCH1_REG ADCH
00466 #define ADCH2_REG ADCH
00467 #define ADCH3_REG ADCH
00468 #define ADCH4_REG ADCH
00469 #define ADCH5_REG ADCH
00470 #define ADCH6_REG ADCH
00471 #define ADCH7_REG ADCH
00472
00473
00474 #define TWIHS_REG TWHSR
00475
00476
00477 #define TWIE_REG TWCR
00478 #define TWEN_REG TWCR
00479 #define TWWC_REG TWCR
00480 #define TWSTO_REG TWCR
00481 #define TWSTA_REG TWCR
00482 #define TWEA_REG TWCR
00483 #define TWINT_REG TWCR
00484
00485
00486 #define TCNT0_0_REG TCNT0
00487 #define TCNT0_1_REG TCNT0
00488 #define TCNT0_2_REG TCNT0
00489 #define TCNT0_3_REG TCNT0
00490 #define TCNT0_4_REG TCNT0
00491 #define TCNT0_5_REG TCNT0
00492 #define TCNT0_6_REG TCNT0
00493 #define TCNT0_7_REG TCNT0
00494
00495
00496 #define PCIE0_REG PCICR
00497 #define PCIE1_REG PCICR
00498 #define PCIE2_REG PCICR
00499 #define PCIE3_REG PCICR
00500
00501
00502 #define TWGCE_REG TWAR
00503 #define TWA0_REG TWAR
00504 #define TWA1_REG TWAR
00505 #define TWA2_REG TWAR
00506 #define TWA3_REG TWAR
00507 #define TWA4_REG TWAR
00508 #define TWA5_REG TWAR
00509 #define TWA6_REG TWAR
00510
00511
00512 #define GPIOR00_REG GPIOR0
00513 #define GPIOR01_REG GPIOR0
00514 #define GPIOR02_REG GPIOR0
00515 #define GPIOR03_REG GPIOR0
00516 #define GPIOR04_REG GPIOR0
00517 #define GPIOR05_REG GPIOR0
00518 #define GPIOR06_REG GPIOR0
00519 #define GPIOR07_REG GPIOR0
00520
00521
00522 #define EEAR0_REG EEARL
00523 #define EEAR1_REG EEARL
00524 #define EEAR2_REG EEARL
00525 #define EEAR3_REG EEARL
00526 #define EEAR4_REG EEARL
00527 #define EEAR5_REG EEARL
00528 #define EEAR6_REG EEARL
00529 #define EEAR7_REG EEARL
00530
00531
00532 #define TOIE0_REG TIMSK0
00533 #define OCIE0A_REG TIMSK0
00534 #define OCIE0B_REG TIMSK0
00535
00536
00537 #define TOIE1_REG TIMSK1
00538 #define OCIE1A_REG TIMSK1
00539 #define OCIE1B_REG TIMSK1
00540 #define ICIE1_REG TIMSK1
00541
00542
00543 #define CS00_REG TCCR0A
00544 #define CS01_REG TCCR0A
00545 #define CS02_REG TCCR0A
00546 #define CTC0_REG TCCR0A
00547
00548
00549 #define TWPS0_REG TWSR
00550 #define TWPS1_REG TWSR
00551 #define TWS3_REG TWSR
00552 #define TWS4_REG TWSR
00553 #define TWS5_REG TWSR
00554 #define TWS6_REG TWSR
00555 #define TWS7_REG TWSR
00556
00557
00558 #define GPIOR20_REG GPIOR2
00559 #define GPIOR21_REG GPIOR2
00560 #define GPIOR22_REG GPIOR2
00561 #define GPIOR23_REG GPIOR2
00562 #define GPIOR24_REG GPIOR2
00563 #define GPIOR25_REG GPIOR2
00564 #define GPIOR26_REG GPIOR2
00565 #define GPIOR27_REG GPIOR2
00566
00567
00568 #define PCINT0_REG PCMSK0
00569 #define PCINT1_REG PCMSK0
00570 #define PCINT2_REG PCMSK0
00571 #define PCINT3_REG PCMSK0
00572 #define PCINT4_REG PCMSK0
00573 #define PCINT5_REG PCMSK0
00574 #define PCINT6_REG PCMSK0
00575 #define PCINT7_REG PCMSK0
00576
00577
00578 #define PCINT8_REG PCMSK1
00579 #define PCINT9_REG PCMSK1
00580 #define PCINT10_REG PCMSK1
00581 #define PCINT11_REG PCMSK1
00582 #define PCINT12_REG PCMSK1
00583 #define PCINT13_REG PCMSK1
00584 #define PCINT14_REG PCMSK1
00585 #define PCINT15_REG PCMSK1
00586
00587
00588 #define PCINT16_REG PCMSK2
00589 #define PCINT17_REG PCMSK2
00590 #define PCINT18_REG PCMSK2
00591 #define PCINT19_REG PCMSK2
00592 #define PCINT20_REG PCMSK2
00593 #define PCINT21_REG PCMSK2
00594 #define PCINT22_REG PCMSK2
00595 #define PCINT23_REG PCMSK2
00596
00597
00598 #define PCINT24_REG PCMSK3
00599 #define PCINT25_REG PCMSK3
00600 #define PCINT26_REG PCMSK3
00601 #define PCINT27_REG PCMSK3
00602
00603
00604 #define PINC0_REG PINC
00605 #define PINC1_REG PINC
00606 #define PINC2_REG PINC
00607 #define PINC3_REG PINC
00608 #define PINC4_REG PINC
00609 #define PINC5_REG PINC
00610 #define PINC6_REG PINC
00611 #define PINC7_REG PINC
00612
00613
00614 #define DDC0_REG DDRC
00615 #define DDC1_REG DDRC
00616 #define DDC2_REG DDRC
00617 #define DDC3_REG DDRC
00618 #define DDC4_REG DDRC
00619 #define DDC5_REG DDRC
00620 #define DDC6_REG DDRC
00621 #define DDC7_REG DDRC
00622
00623
00624 #define INTF0_REG EIFR
00625 #define INTF1_REG EIFR
00626
00627
00628 #define ISC00_REG EICRA
00629 #define ISC01_REG EICRA
00630 #define ISC10_REG EICRA
00631 #define ISC11_REG EICRA
00632
00633
00634 #define ADC0D_REG DIDR0
00635 #define ADC1D_REG DIDR0
00636 #define ADC2D_REG DIDR0
00637 #define ADC3D_REG DIDR0
00638 #define ADC4D_REG DIDR0
00639 #define ADC5D_REG DIDR0
00640 #define ADC6D_REG DIDR0
00641 #define ADC7D_REG DIDR0
00642
00643
00644 #define AIN0D_REG DIDR1
00645 #define AIN1D_REG DIDR1
00646 #define AREFD_REG DIDR1
00647
00648
00649 #define PUD_REG MCUCR
00650 #define BODSE_REG MCUCR
00651 #define BODS_REG MCUCR
00652
00653
00654 #define TWAM0_REG TWAMR
00655 #define TWAM1_REG TWAMR
00656 #define TWAM2_REG TWAMR
00657 #define TWAM3_REG TWAMR
00658 #define TWAM4_REG TWAMR
00659 #define TWAM5_REG TWAMR
00660 #define TWAM6_REG TWAMR
00661
00662
00663 #define DDD0_REG DDRD
00664 #define DDD1_REG DDRD
00665 #define DDD2_REG DDRD
00666 #define DDD3_REG DDRD
00667 #define DDD4_REG DDRD
00668 #define DDD5_REG DDRD
00669 #define DDD6_REG DDRD
00670 #define DDD7_REG DDRD
00671
00672
00673 #define OCR1AL0_REG OCR1AL
00674 #define OCR1AL1_REG OCR1AL
00675 #define OCR1AL2_REG OCR1AL
00676 #define OCR1AL3_REG OCR1AL
00677 #define OCR1AL4_REG OCR1AL
00678 #define OCR1AL5_REG OCR1AL
00679 #define OCR1AL6_REG OCR1AL
00680 #define OCR1AL7_REG OCR1AL
00681
00682
00683 #define TOV0_REG TIFR0
00684 #define OCF0A_REG TIFR0
00685 #define OCF0B_REG TIFR0
00686
00687
00688 #define PINB0_REG PINB
00689 #define PINB1_REG PINB
00690 #define PINB2_REG PINB
00691 #define PINB3_REG PINB
00692 #define PINB4_REG PINB
00693 #define PINB5_REG PINB
00694 #define PINB6_REG PINB
00695 #define PINB7_REG PINB
00696
00697
00698 #define PORTA0_REG PORTA
00699 #define PORTA1_REG PORTA
00700 #define PORTA2_REG PORTA
00701 #define PORTA3_REG PORTA
00702
00703
00704 #define PIND0_REG PIND
00705 #define PIND1_REG PIND
00706 #define PIND2_REG PIND
00707 #define PIND3_REG PIND
00708 #define PIND4_REG PIND
00709 #define PIND5_REG PIND
00710 #define PIND6_REG PIND
00711 #define PIND7_REG PIND
00712
00713
00714 #define PINA0_REG PINA
00715 #define PINA1_REG PINA
00716 #define PINA2_REG PINA
00717 #define PINA3_REG PINA
00718
00719
00720 #define SPR0_REG SPCR
00721 #define SPR1_REG SPCR
00722 #define CPHA_REG SPCR
00723 #define CPOL_REG SPCR
00724 #define MSTR_REG SPCR
00725 #define DORD_REG SPCR
00726 #define SPE_REG SPCR
00727 #define SPIE_REG SPCR
00728
00729
00730 #define TOV1_REG TIFR1
00731 #define OCF1A_REG TIFR1
00732 #define OCF1B_REG TIFR1
00733 #define ICF1_REG TIFR1
00734
00735
00736 #define ICP1_PORT PORTB
00737 #define ICP1_BIT 0
00738 #define CLKO_PORT PORTB
00739 #define CLKO_BIT 0
00740 #define PCINT0_PORT PORTB
00741 #define PCINT0_BIT 0
00742
00743 #define OC1A_PORT PORTB
00744 #define OC1A_BIT 1
00745 #define PCINT1_PORT PORTB
00746 #define PCINT1_BIT 1
00747
00748 #define SS_PORT PORTB
00749 #define SS_BIT 2
00750 #define OC1B_PORT PORTB
00751 #define OC1B_BIT 2
00752 #define PCINT2_PORT PORTB
00753 #define PCINT2_BIT 2
00754
00755 #define MOSI_PORT PORTB
00756 #define MOSI_BIT 3
00757 #define OC2A_PORT PORTB
00758 #define OC2A_BIT 3
00759 #define PCINT3_PORT PORTB
00760 #define PCINT3_BIT 3
00761
00762 #define MISO_PORT PORTB
00763 #define MISO_BIT 4
00764 #define PCINT4_PORT PORTB
00765 #define PCINT4_BIT 4
00766
00767 #define SCK_PORT PORTB
00768 #define SCK_BIT 5
00769 #define PCINT5_PORT PORTB
00770 #define PCINT5_BIT 5
00771
00772 #define XTAL1_PORT PORTB
00773 #define XTAL1_BIT 6
00774 #define TOSC1_PORT PORTB
00775 #define TOSC1_BIT 6
00776 #define PCINT6_PORT PORTB
00777 #define PCINT6_BIT 6
00778
00779 #define XTAL2_PORT PORTB
00780 #define XTAL2_BIT 7
00781 #define TOSC2_PORT PORTB
00782 #define TOSC2_BIT 7
00783 #define PCINT7_PORT PORTB
00784 #define PCINT7_BIT 7
00785
00786 #define ADC0_PORT PORTC
00787 #define ADC0_BIT 0
00788 #define PCINT8_PORT PORTC
00789 #define PCINT8_BIT 0
00790
00791 #define ADC1_PORT PORTC
00792 #define ADC1_BIT 1
00793 #define PCINT9_PORT PORTC
00794 #define PCINT9_BIT 1
00795
00796 #define ADC2_PORT PORTC
00797 #define ADC2_BIT 2
00798 #define PCINT10_PORT PORTC
00799 #define PCINT10_BIT 2
00800
00801 #define ADC3_PORT PORTC
00802 #define ADC3_BIT 3
00803 #define PCINT11_PORT PORTC
00804 #define PCINT11_BIT 3
00805
00806 #define ADC4_PORT PORTC
00807 #define ADC4_BIT 4
00808 #define SDA_PORT PORTC
00809 #define SDA_BIT 4
00810 #define PCINT12_PORT PORTC
00811 #define PCINT12_BIT 4
00812
00813 #define ADC5_PORT PORTC
00814 #define ADC5_BIT 5
00815 #define SCL_PORT PORTC
00816 #define SCL_BIT 5
00817 #define PCINT13_PORT PORTC
00818 #define PCINT13_BIT 5
00819
00820 #define RESET_PORT PORTC
00821 #define RESET_BIT 6
00822 #define PCINT14_PORT PORTC
00823 #define PCINT14_BIT 6
00824
00825 #define RXD_PORT PORTD
00826 #define RXD_BIT 0
00827 #define PCINT16_PORT PORTD
00828 #define PCINT16_BIT 0
00829
00830 #define TXD_PORT PORTD
00831 #define TXD_BIT 1
00832 #define PCINT17_PORT PORTD
00833 #define PCINT17_BIT 1
00834
00835 #define INT0_PORT PORTD
00836 #define INT0_BIT 2
00837 #define PCINT18_PORT PORTD
00838 #define PCINT18_BIT 2
00839
00840 #define PCINT19_PORT PORTD
00841 #define PCINT19_BIT 3
00842 #define OC2B_PORT PORTD
00843 #define OC2B_BIT 3
00844 #define INT1_PORT PORTD
00845 #define INT1_BIT 3
00846
00847 #define XCK_PORT PORTD
00848 #define XCK_BIT 4
00849 #define T0_PORT PORTD
00850 #define T0_BIT 4
00851 #define PCINT20_PORT PORTD
00852 #define PCINT20_BIT 4
00853
00854 #define T1_PORT PORTD
00855 #define T1_BIT 5
00856 #define OC0B_PORT PORTD
00857 #define OC0B_BIT 5
00858 #define PCINT21_PORT PORTD
00859 #define PCINT21_BIT 5
00860
00861 #define AIN0_PORT PORTD
00862 #define AIN0_BIT 6
00863 #define OC0A_PORT PORTD
00864 #define OC0A_BIT 6
00865 #define PCINT22_PORT PORTD
00866 #define PCINT22_BIT 6
00867
00868 #define AIN1_PORT PORTD
00869 #define AIN1_BIT 7
00870 #define PCINT23_PORT PORTD
00871 #define PCINT23_BIT 7
00872
00873