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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067
00068
00069 #define SIG_OVERFLOW_TOTAL_NUM 0
00070
00071
00072 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
00073
00074
00075 #define PWM_TOTAL_NUM 0
00076
00077
00078 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
00079
00080
00081
00082 #define CLKPS0_REG CLKPR
00083 #define CLKPS1_REG CLKPR
00084 #define CLKPS2_REG CLKPR
00085 #define CLKPS3_REG CLKPR
00086 #define CLKPCE_REG CLKPR
00087
00088
00089 #define ACIS0_REG ACSR
00090 #define ACIS1_REG ACSR
00091 #define ACIC_REG ACSR
00092 #define ACIE_REG ACSR
00093 #define ACI_REG ACSR
00094 #define ACO_REG ACSR
00095 #define ACBG_REG ACSR
00096 #define ACD_REG ACSR
00097
00098
00099 #define PCIE0_REG GIMSK
00100 #define PCIE1_REG GIMSK
00101 #define INT0_REG GIMSK
00102
00103
00104 #define ICR1H0_REG ICR1H
00105 #define ICR1H1_REG ICR1H
00106 #define ICR1H2_REG ICR1H
00107 #define ICR1H3_REG ICR1H
00108 #define ICR1H4_REG ICR1H
00109 #define ICR1H5_REG ICR1H
00110 #define ICR1H6_REG ICR1H
00111 #define ICR1H7_REG ICR1H
00112
00113
00114 #define MUX0_REG ADMUX
00115 #define MUX1_REG ADMUX
00116 #define MUX2_REG ADMUX
00117 #define MUX3_REG ADMUX
00118 #define MUX4_REG ADMUX
00119 #define MUX5_REG ADMUX
00120 #define REFS0_REG ADMUX
00121 #define REFS1_REG ADMUX
00122
00123
00124 #define C_REG SREG
00125 #define Z_REG SREG
00126 #define N_REG SREG
00127 #define V_REG SREG
00128 #define S_REG SREG
00129 #define H_REG SREG
00130 #define T_REG SREG
00131 #define I_REG SREG
00132
00133
00134 #define DDB0_REG DDRB
00135 #define DDB1_REG DDRB
00136 #define DDB2_REG DDRB
00137 #define DDB3_REG DDRB
00138
00139
00140 #define WDP0_REG WDTCSR
00141 #define WDP1_REG WDTCSR
00142 #define WDP2_REG WDTCSR
00143 #define WDE_REG WDTCSR
00144 #define WDCE_REG WDTCSR
00145 #define WDP3_REG WDTCSR
00146 #define WDIE_REG WDTCSR
00147 #define WDIF_REG WDTCSR
00148
00149
00150 #define EEDR0_REG EEDR
00151 #define EEDR1_REG EEDR
00152 #define EEDR2_REG EEDR
00153 #define EEDR3_REG EEDR
00154 #define EEDR4_REG EEDR
00155 #define EEDR5_REG EEDR
00156 #define EEDR6_REG EEDR
00157 #define EEDR7_REG EEDR
00158
00159
00160 #define DDA0_REG DDRA
00161 #define DDA1_REG DDRA
00162 #define DDA2_REG DDRA
00163 #define DDA3_REG DDRA
00164 #define DDA4_REG DDRA
00165 #define DDA5_REG DDRA
00166 #define DDA6_REG DDRA
00167 #define DDA7_REG DDRA
00168
00169
00170 #define WGM10_REG TCCR1A
00171 #define WGM11_REG TCCR1A
00172 #define COM1B0_REG TCCR1A
00173 #define COM1B1_REG TCCR1A
00174 #define COM1A0_REG TCCR1A
00175 #define COM1A1_REG TCCR1A
00176
00177
00178 #define PSR10_REG GTCCR
00179 #define TSM_REG GTCCR
00180
00181
00182 #define CS10_REG TCCR1B
00183 #define CS11_REG TCCR1B
00184 #define CS12_REG TCCR1B
00185 #define WGM12_REG TCCR1B
00186 #define WGM13_REG TCCR1B
00187 #define ICES1_REG TCCR1B
00188 #define ICNC1_REG TCCR1B
00189
00190
00191 #define PCIF0_REG GIFR
00192 #define PCIF1_REG GIFR
00193 #define INTF0_REG GIFR
00194
00195
00196 #define CAL0_REG OSCCAL
00197 #define CAL1_REG OSCCAL
00198 #define CAL2_REG OSCCAL
00199 #define CAL3_REG OSCCAL
00200 #define CAL4_REG OSCCAL
00201 #define CAL5_REG OSCCAL
00202 #define CAL6_REG OSCCAL
00203 #define CAL7_REG OSCCAL
00204
00205
00206 #define ADPS0_REG ADCSRA
00207 #define ADPS1_REG ADCSRA
00208 #define ADPS2_REG ADCSRA
00209 #define ADIE_REG ADCSRA
00210 #define ADIF_REG ADCSRA
00211 #define ADATE_REG ADCSRA
00212 #define ADSC_REG ADCSRA
00213 #define ADEN_REG ADCSRA
00214
00215
00216 #define ACME_REG ADCSRB
00217 #define ADTS0_REG ADCSRB
00218 #define ADTS1_REG ADCSRB
00219 #define ADTS2_REG ADCSRB
00220 #define ADLAR_REG ADCSRB
00221 #define BIN_REG ADCSRB
00222
00223
00224
00225
00226
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00229
00230
00231
00232
00233
00234
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00242
00243
00244 #define SP8_REG SPH
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254
00255
00256
00257 #define SP0_REG SPL
00258 #define SP1_REG SPL
00259 #define SP2_REG SPL
00260 #define SP3_REG SPL
00261 #define SP4_REG SPL
00262 #define SP5_REG SPL
00263 #define SP6_REG SPL
00264 #define SP7_REG SPL
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274
00275
00276
00277 #define PRADC_REG PRR
00278 #define PRUSI_REG PRR
00279 #define PRTIM0_REG PRR
00280 #define PRTIM1_REG PRR
00281
00282
00283 #define GPIOR10_REG GPIOR1
00284 #define GPIOR11_REG GPIOR1
00285 #define GPIOR12_REG GPIOR1
00286 #define GPIOR13_REG GPIOR1
00287 #define GPIOR14_REG GPIOR1
00288 #define GPIOR15_REG GPIOR1
00289 #define GPIOR16_REG GPIOR1
00290 #define GPIOR17_REG GPIOR1
00291
00292
00293 #define ICR1L0_REG ICR1L
00294 #define ICR1L1_REG ICR1L
00295 #define ICR1L2_REG ICR1L
00296 #define ICR1L3_REG ICR1L
00297 #define ICR1L4_REG ICR1L
00298 #define ICR1L5_REG ICR1L
00299 #define ICR1L6_REG ICR1L
00300 #define ICR1L7_REG ICR1L
00301
00302
00303 #define GPIOR20_REG GPIOR2
00304 #define GPIOR21_REG GPIOR2
00305 #define GPIOR22_REG GPIOR2
00306 #define GPIOR23_REG GPIOR2
00307 #define GPIOR24_REG GPIOR2
00308 #define GPIOR25_REG GPIOR2
00309 #define GPIOR26_REG GPIOR2
00310 #define GPIOR27_REG GPIOR2
00311
00312
00313 #define PORF_REG MCUSR
00314 #define EXTRF_REG MCUSR
00315 #define BORF_REG MCUSR
00316 #define WDRF_REG MCUSR
00317
00318
00319 #define EERE_REG EECR
00320 #define EEPE_REG EECR
00321 #define EEMPE_REG EECR
00322 #define EERIE_REG EECR
00323 #define EEPM0_REG EECR
00324 #define EEPM1_REG EECR
00325
00326
00327 #define SPMEN_REG SPMCSR
00328 #define PGERS_REG SPMCSR
00329 #define PGWRT_REG SPMCSR
00330 #define RFLB_REG SPMCSR
00331 #define CTPB_REG SPMCSR
00332
00333
00334 #define TCNT1L0_REG TCNT1L
00335 #define TCNT1L1_REG TCNT1L
00336 #define TCNT1L2_REG TCNT1L
00337 #define TCNT1L3_REG TCNT1L
00338 #define TCNT1L4_REG TCNT1L
00339 #define TCNT1L5_REG TCNT1L
00340 #define TCNT1L6_REG TCNT1L
00341 #define TCNT1L7_REG TCNT1L
00342
00343
00344 #define PORTB0_REG PORTB
00345 #define PORTB1_REG PORTB
00346 #define PORTB2_REG PORTB
00347 #define PORTB3_REG PORTB
00348
00349
00350 #define ADCL0_REG ADCL
00351 #define ADCL1_REG ADCL
00352 #define ADCL2_REG ADCL
00353 #define ADCL3_REG ADCL
00354 #define ADCL4_REG ADCL
00355 #define ADCL5_REG ADCL
00356 #define ADCL6_REG ADCL
00357 #define ADCL7_REG ADCL
00358
00359
00360 #define USICNT0_REG USISR
00361 #define USICNT1_REG USISR
00362 #define USICNT2_REG USISR
00363 #define USICNT3_REG USISR
00364 #define USIDC_REG USISR
00365 #define USIPF_REG USISR
00366 #define USIOIF_REG USISR
00367 #define USISIF_REG USISR
00368
00369
00370 #define TCNT1H0_REG TCNT1H
00371 #define TCNT1H1_REG TCNT1H
00372 #define TCNT1H2_REG TCNT1H
00373 #define TCNT1H3_REG TCNT1H
00374 #define TCNT1H4_REG TCNT1H
00375 #define TCNT1H5_REG TCNT1H
00376 #define TCNT1H6_REG TCNT1H
00377 #define TCNT1H7_REG TCNT1H
00378
00379
00380 #define ADCH0_REG ADCH
00381 #define ADCH1_REG ADCH
00382 #define ADCH2_REG ADCH
00383 #define ADCH3_REG ADCH
00384 #define ADCH4_REG ADCH
00385 #define ADCH5_REG ADCH
00386 #define ADCH6_REG ADCH
00387 #define ADCH7_REG ADCH
00388
00389
00390 #define PORTA0_REG PORTA
00391 #define PORTA1_REG PORTA
00392 #define PORTA2_REG PORTA
00393 #define PORTA3_REG PORTA
00394 #define PORTA4_REG PORTA
00395 #define PORTA5_REG PORTA
00396 #define PORTA6_REG PORTA
00397 #define PORTA7_REG PORTA
00398
00399
00400 #define TCNT0_0_REG TCNT0
00401 #define TCNT0_1_REG TCNT0
00402 #define TCNT0_2_REG TCNT0
00403 #define TCNT0_3_REG TCNT0
00404 #define TCNT0_4_REG TCNT0
00405 #define TCNT0_5_REG TCNT0
00406 #define TCNT0_6_REG TCNT0
00407 #define TCNT0_7_REG TCNT0
00408
00409
00410 #define GPIOR00_REG GPIOR0
00411 #define GPIOR01_REG GPIOR0
00412 #define GPIOR02_REG GPIOR0
00413 #define GPIOR03_REG GPIOR0
00414 #define GPIOR04_REG GPIOR0
00415 #define GPIOR05_REG GPIOR0
00416 #define GPIOR06_REG GPIOR0
00417 #define GPIOR07_REG GPIOR0
00418
00419
00420 #define PCINT0_REG PCMSK0
00421 #define PCINT1_REG PCMSK0
00422 #define PCINT2_REG PCMSK0
00423 #define PCINT3_REG PCMSK0
00424 #define PCINT4_REG PCMSK0
00425 #define PCINT5_REG PCMSK0
00426 #define PCINT6_REG PCMSK0
00427 #define PCINT7_REG PCMSK0
00428
00429
00430 #define TOIE0_REG TIMSK0
00431 #define OCIE0A_REG TIMSK0
00432 #define OCIE0B_REG TIMSK0
00433
00434
00435 #define TOIE1_REG TIMSK1
00436 #define OCIE1A_REG TIMSK1
00437 #define OCIE1B_REG TIMSK1
00438 #define ICIE1_REG TIMSK1
00439
00440
00441 #define CS00_REG TCCR0B
00442 #define CS01_REG TCCR0B
00443 #define CS02_REG TCCR0B
00444 #define WGM02_REG TCCR0B
00445 #define FOC0B_REG TCCR0B
00446 #define FOC0A_REG TCCR0B
00447
00448
00449 #define FOC1B_REG TCCR1C
00450 #define FOC1A_REG TCCR1C
00451
00452
00453 #define WGM00_REG TCCR0A
00454 #define WGM01_REG TCCR0A
00455 #define COM0B0_REG TCCR0A
00456 #define COM0B1_REG TCCR0A
00457 #define COM0A0_REG TCCR0A
00458 #define COM0A1_REG TCCR0A
00459
00460
00461 #define EEAR8_REG EEARH
00462
00463
00464 #define USITC_REG USICR
00465 #define USICLK_REG USICR
00466 #define USICS0_REG USICR
00467 #define USICS1_REG USICR
00468 #define USIWM0_REG USICR
00469 #define USIWM1_REG USICR
00470 #define USIOIE_REG USICR
00471 #define USISIE_REG USICR
00472
00473
00474 #define EEAR0_REG EEARL
00475 #define EEAR1_REG EEARL
00476 #define EEAR2_REG EEARL
00477 #define EEAR3_REG EEARL
00478 #define EEAR4_REG EEARL
00479 #define EEAR5_REG EEARL
00480 #define EEAR6_REG EEARL
00481 #define EEAR7_REG EEARL
00482
00483
00484 #define PCINT8_REG PCMSK1
00485 #define PCINT9_REG PCMSK1
00486 #define PCINT10_REG PCMSK1
00487 #define PCINT11_REG PCMSK1
00488
00489
00490 #define PINB0_REG PINB
00491 #define PINB1_REG PINB
00492 #define PINB2_REG PINB
00493 #define PINB3_REG PINB
00494
00495
00496 #define PINA0_REG PINA
00497 #define PINA1_REG PINA
00498 #define PINA2_REG PINA
00499 #define PINA3_REG PINA
00500 #define PINA4_REG PINA
00501 #define PINA5_REG PINA
00502 #define PINA6_REG PINA
00503 #define PINA7_REG PINA
00504
00505
00506 #define ADC0D_REG DIDR0
00507 #define ADC1D_REG DIDR0
00508 #define ADC2D_REG DIDR0
00509 #define ADC3D_REG DIDR0
00510 #define ADC4D_REG DIDR0
00511 #define ADC5D_REG DIDR0
00512 #define ADC6D_REG DIDR0
00513 #define ADC7D_REG DIDR0
00514
00515
00516 #define ISC00_REG MCUCR
00517 #define ISC01_REG MCUCR
00518 #define SM0_REG MCUCR
00519 #define SM1_REG MCUCR
00520 #define SE_REG MCUCR
00521 #define PUD_REG MCUCR
00522
00523
00524
00525
00526
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539
00540
00541
00542
00543
00544 #define USIDR0_REG USIDR
00545 #define USIDR1_REG USIDR
00546 #define USIDR2_REG USIDR
00547 #define USIDR3_REG USIDR
00548 #define USIDR4_REG USIDR
00549 #define USIDR5_REG USIDR
00550 #define USIDR6_REG USIDR
00551 #define USIDR7_REG USIDR
00552
00553
00554 #define USIBR0_REG USIBR
00555 #define USIBR1_REG USIBR
00556 #define USIBR2_REG USIBR
00557 #define USIBR3_REG USIBR
00558 #define USIBR4_REG USIBR
00559 #define USIBR5_REG USIBR
00560 #define USIBR6_REG USIBR
00561 #define USIBR7_REG USIBR
00562
00563
00564 #define TOV0_REG TIFR0
00565 #define OCF0A_REG TIFR0
00566 #define OCF0B_REG TIFR0
00567
00568
00569 #define TOV1_REG TIFR1
00570 #define OCF1A_REG TIFR1
00571 #define OCF1B_REG TIFR1
00572 #define ICF1_REG TIFR1
00573
00574
00575 #define ADC0_PORT PORTA
00576 #define ADC0_BIT 0
00577 #define AREF_PORT PORTA
00578 #define AREF_BIT 0
00579 #define PCINT0_PORT PORTA
00580 #define PCINT0_BIT 0
00581
00582 #define ADC1_PORT PORTA
00583 #define ADC1_BIT 1
00584 #define AIN0_PORT PORTA
00585 #define AIN0_BIT 1
00586 #define PCINT1_PORT PORTA
00587 #define PCINT1_BIT 1
00588
00589 #define ADC2_PORT PORTA
00590 #define ADC2_BIT 2
00591 #define AIN1_PORT PORTA
00592 #define AIN1_BIT 2
00593 #define PCINT2_PORT PORTA
00594 #define PCINT2_BIT 2
00595
00596 #define ADC3_PORT PORTA
00597 #define ADC3_BIT 3
00598 #define T0_PORT PORTA
00599 #define T0_BIT 3
00600 #define PCINT3_PORT PORTA
00601 #define PCINT3_BIT 3
00602
00603 #define ADC4_PORT PORTA
00604 #define ADC4_BIT 4
00605 #define USCK_PORT PORTA
00606 #define USCK_BIT 4
00607 #define SCL_PORT PORTA
00608 #define SCL_BIT 4
00609 #define T1_PORT PORTA
00610 #define T1_BIT 4
00611 #define PCINT4_PORT PORTA
00612 #define PCINT4_BIT 4
00613
00614 #define ADC5_PORT PORTA
00615 #define ADC5_BIT 5
00616 #define DO_PORT PORTA
00617 #define DO_BIT 5
00618 #define MISO_PORT PORTA
00619 #define MISO_BIT 5
00620 #define OC1B_PORT PORTA
00621 #define OC1B_BIT 5
00622 #define PCINT5_PORT PORTA
00623 #define PCINT5_BIT 5
00624
00625 #define PCINT6_PORT PORTA
00626 #define PCINT6_BIT 6
00627 #define OC1A_PORT PORTA
00628 #define OC1A_BIT 6
00629 #define DI_PORT PORTA
00630 #define DI_BIT 6
00631 #define SDA_PORT PORTA
00632 #define SDA_BIT 6
00633 #define MOSI_PORT PORTA
00634 #define MOSI_BIT 6
00635 #define ADC6_PORT PORTA
00636 #define ADC6_BIT 6
00637
00638 #define PCINT7_PORT PORTA
00639 #define PCINT7_BIT 7
00640 #define ICP1_PORT PORTA
00641 #define ICP1_BIT 7
00642 #define OC0B_PORT PORTA
00643 #define OC0B_BIT 7
00644 #define ADC7_PORT PORTA
00645 #define ADC7_BIT 7
00646
00647 #define PCINT8_PORT PORTB
00648 #define PCINT8_BIT 0
00649 #define XTAL1_PORT PORTB
00650 #define XTAL1_BIT 0
00651
00652 #define PCINT9_PORT PORTB
00653 #define PCINT9_BIT 1
00654 #define XTAL2_PORT PORTB
00655 #define XTAL2_BIT 1
00656
00657 #define PCINT10_PORT PORTB
00658 #define PCINT10_BIT 2
00659 #define INT0_PORT PORTB
00660 #define INT0_BIT 2
00661 #define OC0A_PORT PORTB
00662 #define OC0A_BIT 2
00663 #define CKOUT_PORT PORTB
00664 #define CKOUT_BIT 2
00665
00666 #define PCINT11_PORT PORTB
00667 #define PCINT11_BIT 3
00668 #define RESET_PORT PORTB
00669 #define RESET_BIT 3
00670 #define dW_PORT PORTB
00671 #define dW_BIT 3
00672
00673