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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067
00068
00069 #define SIG_OVERFLOW_TOTAL_NUM 0
00070
00071
00072 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
00073
00074
00075 #define PWM_TOTAL_NUM 0
00076
00077
00078 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
00079
00080
00081
00082 #define CLKPS0_REG CLKPR
00083 #define CLKPS1_REG CLKPR
00084 #define CLKPS2_REG CLKPR
00085 #define CLKPS3_REG CLKPR
00086 #define CLKPCE_REG CLKPR
00087
00088
00089 #define ACIS0_REG ACSR
00090 #define ACIS1_REG ACSR
00091 #define ACIE_REG ACSR
00092 #define ACI_REG ACSR
00093 #define ACO_REG ACSR
00094 #define ACBG_REG ACSR
00095 #define ACD_REG ACSR
00096
00097
00098 #define PCIE0_REG GIMSK
00099 #define PCIE1_REG GIMSK
00100 #define INT0_REG GIMSK
00101
00102
00103 #define ADC0D_REG DIDR0
00104 #define ADC1D_REG DIDR0
00105 #define ADC2D_REG DIDR0
00106 #define ADC3D_REG DIDR0
00107 #define AIN0D_REG DIDR0
00108 #define AIN1D_REG DIDR0
00109
00110
00111 #define MUX0_REG ADMUX
00112 #define MUX1_REG ADMUX
00113 #define MUX2_REG ADMUX
00114 #define REFS_REG ADMUX
00115
00116
00117 #define C_REG SREG
00118 #define Z_REG SREG
00119 #define N_REG SREG
00120 #define V_REG SREG
00121 #define S_REG SREG
00122 #define H_REG SREG
00123 #define T_REG SREG
00124 #define I_REG SREG
00125
00126
00127 #define DDB0_REG DDRB
00128 #define DDB1_REG DDRB
00129 #define DDB2_REG DDRB
00130 #define DDB3_REG DDRB
00131 #define DDB4_REG DDRB
00132 #define DDB5_REG DDRB
00133 #define DDB6_REG DDRB
00134 #define DDB7_REG DDRB
00135
00136
00137 #define WDP0_REG WDTCSR
00138 #define WDP1_REG WDTCSR
00139 #define WDP2_REG WDTCSR
00140 #define WDE_REG WDTCSR
00141 #define WDCE_REG WDTCSR
00142 #define WDP3_REG WDTCSR
00143 #define WDIE_REG WDTCSR
00144 #define WDIF_REG WDTCSR
00145
00146
00147 #define EEDR0_REG EEDR
00148 #define EEDR1_REG EEDR
00149 #define EEDR2_REG EEDR
00150 #define EEDR3_REG EEDR
00151 #define EEDR4_REG EEDR
00152 #define EEDR5_REG EEDR
00153 #define EEDR6_REG EEDR
00154 #define EEDR7_REG EEDR
00155
00156
00157
00158
00159
00160
00161
00162
00163
00164
00165
00166
00167 #define WGM10_REG TCCR1A
00168 #define WGM11_REG TCCR1A
00169 #define COM1B0_REG TCCR1A
00170 #define COM1B1_REG TCCR1A
00171 #define COM1A0_REG TCCR1A
00172 #define COM1A1_REG TCCR1A
00173
00174
00175 #define PSR10_REG GTCCR
00176 #define TSM_REG GTCCR
00177
00178
00179 #define CS10_REG TCCR1B
00180 #define CS11_REG TCCR1B
00181 #define CS12_REG TCCR1B
00182 #define WGM12_REG TCCR1B
00183 #define FOC1B_REG TCCR1B
00184 #define FOC1A_REG TCCR1B
00185
00186
00187 #define PCIF0_REG GIFR
00188 #define PCIF1_REG GIFR
00189 #define INTF0_REG GIFR
00190
00191
00192 #define CAL0_REG OSCCAL
00193 #define CAL1_REG OSCCAL
00194 #define CAL2_REG OSCCAL
00195 #define CAL3_REG OSCCAL
00196 #define CAL4_REG OSCCAL
00197 #define CAL5_REG OSCCAL
00198 #define CAL6_REG OSCCAL
00199 #define CAL7_REG OSCCAL
00200
00201
00202 #define DDA0_REG DDRA
00203 #define DDA1_REG DDRA
00204 #define DDA2_REG DDRA
00205 #define DDA3_REG DDRA
00206 #define DDA4_REG DDRA
00207 #define DDA5_REG DDRA
00208 #define DDA6_REG DDRA
00209 #define DDA7_REG DDRA
00210
00211
00212 #define ADPS0_REG ADCSRA
00213 #define ADPS1_REG ADCSRA
00214 #define ADPS2_REG ADCSRA
00215 #define ADIE_REG ADCSRA
00216 #define ADIF_REG ADCSRA
00217 #define ADATE_REG ADCSRA
00218 #define ADSC_REG ADCSRA
00219 #define ADEN_REG ADCSRA
00220
00221
00222 #define ACME_REG ADCSRB
00223 #define ADTS0_REG ADCSRB
00224 #define ADTS1_REG ADCSRB
00225 #define ADTS2_REG ADCSRB
00226 #define ADLAR_REG ADCSRB
00227 #define BVRON_REG ADCSRB
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
00238
00239
00240
00241
00242
00243
00244
00245
00246
00247
00248
00249
00250 #define SP8_REG SPH
00251
00252
00253 #define SP0_REG SPL
00254 #define SP1_REG SPL
00255 #define SP2_REG SPL
00256 #define SP3_REG SPL
00257 #define SP4_REG SPL
00258 #define SP5_REG SPL
00259 #define SP6_REG SPL
00260 #define SP7_REG SPL
00261
00262
00263 #define PRADC_REG PRR
00264 #define PRUSI_REG PRR
00265 #define PRTIM0_REG PRR
00266 #define PRTIM1_REG PRR
00267
00268
00269 #define GPIOR10_REG GPIOR1
00270 #define GPIOR11_REG GPIOR1
00271 #define GPIOR12_REG GPIOR1
00272 #define GPIOR13_REG GPIOR1
00273 #define GPIOR14_REG GPIOR1
00274 #define GPIOR15_REG GPIOR1
00275 #define GPIOR16_REG GPIOR1
00276 #define GPIOR17_REG GPIOR1
00277
00278
00279 #define GPIOR00_REG GPIOR0
00280 #define GPIOR01_REG GPIOR0
00281 #define GPIOR02_REG GPIOR0
00282 #define GPIOR03_REG GPIOR0
00283 #define GPIOR04_REG GPIOR0
00284 #define GPIOR05_REG GPIOR0
00285 #define GPIOR06_REG GPIOR0
00286 #define GPIOR07_REG GPIOR0
00287
00288
00289 #define GPIOR20_REG GPIOR2
00290 #define GPIOR21_REG GPIOR2
00291 #define GPIOR22_REG GPIOR2
00292 #define GPIOR23_REG GPIOR2
00293 #define GPIOR24_REG GPIOR2
00294 #define GPIOR25_REG GPIOR2
00295 #define GPIOR26_REG GPIOR2
00296 #define GPIOR27_REG GPIOR2
00297
00298
00299 #define PORF_REG MCUSR
00300 #define EXTRF_REG MCUSR
00301 #define BORF_REG MCUSR
00302 #define WDRF_REG MCUSR
00303
00304
00305 #define EERE_REG EECR
00306 #define EEPE_REG EECR
00307 #define EEMPE_REG EECR
00308 #define EERIE_REG EECR
00309 #define EEPM0_REG EECR
00310 #define EEPM1_REG EECR
00311
00312
00313 #define USICNT0_REG USISR
00314 #define USICNT1_REG USISR
00315 #define USICNT2_REG USISR
00316 #define USICNT3_REG USISR
00317 #define USIDC_REG USISR
00318 #define USIPF_REG USISR
00319 #define USIOIF_REG USISR
00320 #define USISIF_REG USISR
00321
00322
00323 #define SPMEN_REG SPMCSR
00324 #define PGERS_REG SPMCSR
00325 #define PGWRT_REG SPMCSR
00326 #define RFLB_REG SPMCSR
00327 #define CTPB_REG SPMCSR
00328
00329
00330 #define ADCL0_REG ADCL
00331 #define ADCL1_REG ADCL
00332 #define ADCL2_REG ADCL
00333 #define ADCL3_REG ADCL
00334 #define ADCL4_REG ADCL
00335 #define ADCL5_REG ADCL
00336 #define ADCL6_REG ADCL
00337 #define ADCL7_REG ADCL
00338
00339
00340 #define EEAR0_REG EEAR
00341 #define EEAR1_REG EEAR
00342 #define EEAR2_REG EEAR
00343 #define EEAR3_REG EEAR
00344 #define EEAR4_REG EEAR
00345 #define EEAR5_REG EEAR
00346
00347
00348 #define PORTB0_REG PORTB
00349 #define PORTB1_REG PORTB
00350 #define PORTB2_REG PORTB
00351 #define PORTB3_REG PORTB
00352 #define PORTB4_REG PORTB
00353 #define PORTB5_REG PORTB
00354 #define PORTB6_REG PORTB
00355 #define PORTB7_REG PORTB
00356
00357
00358 #define ADCH0_REG ADCH
00359 #define ADCH1_REG ADCH
00360 #define ADCH2_REG ADCH
00361 #define ADCH3_REG ADCH
00362 #define ADCH4_REG ADCH
00363 #define ADCH5_REG ADCH
00364 #define ADCH6_REG ADCH
00365 #define ADCH7_REG ADCH
00366
00367
00368 #define PORTA0_REG PORTA
00369 #define PORTA1_REG PORTA
00370 #define PORTA2_REG PORTA
00371 #define PORTA3_REG PORTA
00372 #define PORTA4_REG PORTA
00373 #define PORTA5_REG PORTA
00374 #define PORTA6_REG PORTA
00375 #define PORTA7_REG PORTA
00376
00377
00378 #define TCNT0_0_REG TCNT0
00379 #define TCNT0_1_REG TCNT0
00380 #define TCNT0_2_REG TCNT0
00381 #define TCNT0_3_REG TCNT0
00382 #define TCNT0_4_REG TCNT0
00383 #define TCNT0_5_REG TCNT0
00384 #define TCNT0_6_REG TCNT0
00385 #define TCNT0_7_REG TCNT0
00386
00387
00388 #define TCNT1_0_REG TCNT1
00389 #define TCNT1_1_REG TCNT1
00390 #define TCNT1_2_REG TCNT1
00391 #define TCNT1_3_REG TCNT1
00392 #define TCNT1_4_REG TCNT1
00393 #define TCNT1_5_REG TCNT1
00394 #define TCNT1_6_REG TCNT1
00395 #define TCNT1_7_REG TCNT1
00396
00397
00398 #define TOIE0_REG TIMSK0
00399 #define OCIE0A_REG TIMSK0
00400 #define OCIE0B_REG TIMSK0
00401
00402
00403 #define TOIE1_REG TIMSK1
00404 #define OCIE1A_REG TIMSK1
00405 #define OCIE1B_REG TIMSK1
00406
00407
00408 #define CS00_REG TCCR0B
00409 #define CS01_REG TCCR0B
00410 #define CS02_REG TCCR0B
00411 #define WGM02_REG TCCR0B
00412 #define FOC0B_REG TCCR0B
00413 #define FOC0A_REG TCCR0B
00414
00415
00416 #define WGM00_REG TCCR0A
00417 #define WGM01_REG TCCR0A
00418 #define COM0B0_REG TCCR0A
00419 #define COM0B1_REG TCCR0A
00420 #define COM0A0_REG TCCR0A
00421 #define COM0A1_REG TCCR0A
00422
00423
00424 #define USITC_REG USICR
00425 #define USICLK_REG USICR
00426 #define USICS0_REG USICR
00427 #define USICS1_REG USICR
00428 #define USIWM0_REG USICR
00429 #define USIWM1_REG USICR
00430 #define USIOIE_REG USICR
00431 #define USISIE_REG USICR
00432
00433
00434 #define PCINT0_REG PCMSK0
00435 #define PCINT1_REG PCMSK0
00436 #define PCINT2_REG PCMSK0
00437 #define PCINT3_REG PCMSK0
00438 #define PCINT4_REG PCMSK0
00439 #define PCINT5_REG PCMSK0
00440 #define PCINT6_REG PCMSK0
00441 #define PCINT7_REG PCMSK0
00442
00443
00444 #define PCINT8_REG PCMSK1
00445 #define PCINT9_REG PCMSK1
00446 #define PCINT10_REG PCMSK1
00447 #define PCINT11_REG PCMSK1
00448 #define PCINT12_REG PCMSK1
00449 #define PCINT13_REG PCMSK1
00450 #define PCINT14_REG PCMSK1
00451 #define PCINT15_REG PCMSK1
00452
00453
00454 #define PINB0_REG PINB
00455 #define PINB1_REG PINB
00456 #define PINB2_REG PINB
00457 #define PINB3_REG PINB
00458 #define PINB4_REG PINB
00459 #define PINB5_REG PINB
00460 #define PINB6_REG PINB
00461 #define PINB7_REG PINB
00462
00463
00464 #define PINA0_REG PINA
00465 #define PINA1_REG PINA
00466 #define PINA2_REG PINA
00467 #define PINA3_REG PINA
00468 #define PINA4_REG PINA
00469 #define PINA5_REG PINA
00470 #define PINA6_REG PINA
00471 #define PINA7_REG PINA
00472
00473
00474
00475
00476
00477
00478
00479
00480
00481
00482
00483
00484 #define ISC00_REG MCUCR
00485 #define ISC01_REG MCUCR
00486 #define BODSE_REG MCUCR
00487 #define SM0_REG MCUCR
00488 #define SM1_REG MCUCR
00489 #define SE_REG MCUCR
00490 #define PUD_REG MCUCR
00491 #define BODS_REG MCUCR
00492
00493
00494 #define USIDR0_REG USIDR
00495 #define USIDR1_REG USIDR
00496 #define USIDR2_REG USIDR
00497 #define USIDR3_REG USIDR
00498 #define USIDR4_REG USIDR
00499 #define USIDR5_REG USIDR
00500 #define USIDR6_REG USIDR
00501 #define USIDR7_REG USIDR
00502
00503
00504 #define USIBR0_REG USIBR
00505 #define USIBR1_REG USIBR
00506 #define USIBR2_REG USIBR
00507 #define USIBR3_REG USIBR
00508 #define USIBR4_REG USIBR
00509 #define USIBR5_REG USIBR
00510 #define USIBR6_REG USIBR
00511 #define USIBR7_REG USIBR
00512
00513
00514 #define TOV0_REG TIFR0
00515 #define OCF0A_REG TIFR0
00516 #define OCF0B_REG TIFR0
00517
00518
00519 #define TOV1_REG TIFR1
00520 #define OCF1A_REG TIFR1
00521 #define OCF1B_REG TIFR1
00522
00523
00524