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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_2 2
00050 #define TIMER1_PRESCALER_DIV_4 3
00051 #define TIMER1_PRESCALER_DIV_8 4
00052 #define TIMER1_PRESCALER_DIV_16 5
00053 #define TIMER1_PRESCALER_DIV_32 6
00054 #define TIMER1_PRESCALER_DIV_64 7
00055 #define TIMER1_PRESCALER_DIV_128 8
00056 #define TIMER1_PRESCALER_DIV_256 9
00057 #define TIMER1_PRESCALER_DIV_512 10
00058 #define TIMER1_PRESCALER_DIV_1024 11
00059 #define TIMER1_PRESCALER_DIV_2048 12
00060 #define TIMER1_PRESCALER_DIV_4096 13
00061 #define TIMER1_PRESCALER_DIV_8192 14
00062 #define TIMER1_PRESCALER_DIV_16384 15
00063
00064 #define TIMER1_PRESCALER_REG_0 0
00065 #define TIMER1_PRESCALER_REG_1 1
00066 #define TIMER1_PRESCALER_REG_2 2
00067 #define TIMER1_PRESCALER_REG_3 4
00068 #define TIMER1_PRESCALER_REG_4 8
00069 #define TIMER1_PRESCALER_REG_5 16
00070 #define TIMER1_PRESCALER_REG_6 32
00071 #define TIMER1_PRESCALER_REG_7 64
00072 #define TIMER1_PRESCALER_REG_8 128
00073 #define TIMER1_PRESCALER_REG_9 256
00074 #define TIMER1_PRESCALER_REG_10 512
00075 #define TIMER1_PRESCALER_REG_11 1024
00076 #define TIMER1_PRESCALER_REG_12 2048
00077 #define TIMER1_PRESCALER_REG_13 4096
00078 #define TIMER1_PRESCALER_REG_14 8192
00079 #define TIMER1_PRESCALER_REG_15 16384
00080
00081
00082
00083 #define TIMER0_AVAILABLE
00084 #define TIMER1_AVAILABLE
00085
00086
00087 #define SIG_OVERFLOW0_NUM 0
00088 #define SIG_OVERFLOW1_NUM 1
00089 #define SIG_OVERFLOW_TOTAL_NUM 2
00090
00091
00092 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
00093
00094
00095 #define PWM_TOTAL_NUM 0
00096
00097
00098 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
00099
00100
00101
00102 #define WDP0_REG WDTCR
00103 #define WDP1_REG WDTCR
00104 #define WDP2_REG WDTCR
00105 #define WDE_REG WDTCR
00106 #define WDCE_REG WDTCR
00107
00108
00109 #define PCIE0_REG GIMSK
00110 #define PCIE1_REG GIMSK
00111 #define INT0_REG GIMSK
00112
00113
00114 #define MUX0_REG ADMUX
00115 #define MUX1_REG ADMUX
00116 #define MUX2_REG ADMUX
00117 #define MUX3_REG ADMUX
00118 #define MUX4_REG ADMUX
00119 #define ADLAR_REG ADMUX
00120 #define REFS0_REG ADMUX
00121 #define REFS1_REG ADMUX
00122
00123
00124 #define CS00_REG TCCR0
00125 #define CS01_REG TCCR0
00126 #define CS02_REG TCCR0
00127 #define PSR0_REG TCCR0
00128
00129
00130 #define C_REG SREG
00131 #define Z_REG SREG
00132 #define N_REG SREG
00133 #define V_REG SREG
00134 #define S_REG SREG
00135 #define H_REG SREG
00136 #define T_REG SREG
00137 #define I_REG SREG
00138
00139
00140 #define DDB0_REG DDRB
00141 #define DDB1_REG DDRB
00142 #define DDB2_REG DDRB
00143 #define DDB3_REG DDRB
00144 #define DDB4_REG DDRB
00145 #define DDB5_REG DDRB
00146 #define DDB6_REG DDRB
00147 #define DDB7_REG DDRB
00148
00149
00150 #define EEDR0_REG EEDR
00151 #define EEDR1_REG EEDR
00152 #define EEDR2_REG EEDR
00153 #define EEDR3_REG EEDR
00154 #define EEDR4_REG EEDR
00155 #define EEDR5_REG EEDR
00156 #define EEDR6_REG EEDR
00157 #define EEDR7_REG EEDR
00158
00159
00160 #define ISC00_REG MCUCR
00161 #define ISC01_REG MCUCR
00162 #define SM0_REG MCUCR
00163 #define SM1_REG MCUCR
00164 #define SE_REG MCUCR
00165 #define PUD_REG MCUCR
00166
00167
00168 #define PWM1B_REG TCCR1A
00169 #define PWM1A_REG TCCR1A
00170 #define FOC1B_REG TCCR1A
00171 #define FOC1A_REG TCCR1A
00172 #define COM1B0_REG TCCR1A
00173 #define COM1B1_REG TCCR1A
00174 #define COM1A0_REG TCCR1A
00175 #define COM1A1_REG TCCR1A
00176
00177
00178 #define CS10_REG TCCR1B
00179 #define CS11_REG TCCR1B
00180 #define CS12_REG TCCR1B
00181 #define CS13_REG TCCR1B
00182 #define PSR1_REG TCCR1B
00183 #define CTC1_REG TCCR1B
00184
00185
00186 #define PCIF_REG GIFR
00187 #define INTF0_REG GIFR
00188
00189
00190 #define TOIE0_REG TIMSK
00191 #define TOIE1_REG TIMSK
00192 #define OCIE1B_REG TIMSK
00193 #define OCIE1A_REG TIMSK
00194
00195
00196 #define DDA0_REG DDRA
00197 #define DDA1_REG DDRA
00198 #define DDA2_REG DDRA
00199 #define DDA3_REG DDRA
00200 #define DDA4_REG DDRA
00201 #define DDA5_REG DDRA
00202 #define DDA6_REG DDRA
00203 #define DDA7_REG DDRA
00204
00205
00206 #define ACIS0_REG ACSR
00207 #define ACIS1_REG ACSR
00208 #define ACME_REG ACSR
00209 #define ACIE_REG ACSR
00210 #define ACI_REG ACSR
00211 #define ACO_REG ACSR
00212 #define ACBG_REG ACSR
00213 #define ACD_REG ACSR
00214
00215
00216 #define USITC_REG USICR
00217 #define USICLK_REG USICR
00218 #define USICS0_REG USICR
00219 #define USICS1_REG USICR
00220 #define USIWM0_REG USICR
00221 #define USIWM1_REG USICR
00222 #define USIOIE_REG USICR
00223 #define USISIE_REG USICR
00224
00225
00226 #define PORF_REG MCUSR
00227 #define EXTRF_REG MCUSR
00228 #define BORF_REG MCUSR
00229 #define WDRF_REG MCUSR
00230
00231
00232 #define EERE_REG EECR
00233 #define EEWE_REG EECR
00234 #define EEMWE_REG EECR
00235 #define EERIE_REG EECR
00236
00237
00238 #define USICNT0_REG USISR
00239 #define USICNT1_REG USISR
00240 #define USICNT2_REG USISR
00241 #define USICNT3_REG USISR
00242 #define USIDC_REG USISR
00243 #define USIPF_REG USISR
00244 #define USIOIF_REG USISR
00245 #define USISIF_REG USISR
00246
00247
00248 #define CAL0_REG OSCCAL
00249 #define CAL1_REG OSCCAL
00250 #define CAL2_REG OSCCAL
00251 #define CAL3_REG OSCCAL
00252 #define CAL4_REG OSCCAL
00253 #define CAL5_REG OSCCAL
00254 #define CAL6_REG OSCCAL
00255 #define CAL7_REG OSCCAL
00256
00257
00258 #define ADCL0_REG ADCL
00259 #define ADCL1_REG ADCL
00260 #define ADCL2_REG ADCL
00261 #define ADCL3_REG ADCL
00262 #define ADCL4_REG ADCL
00263 #define ADCL5_REG ADCL
00264 #define ADCL6_REG ADCL
00265 #define ADCL7_REG ADCL
00266
00267
00268 #define EEAR0_REG EEAR
00269 #define EEAR1_REG EEAR
00270 #define EEAR2_REG EEAR
00271 #define EEAR3_REG EEAR
00272 #define EEAR4_REG EEAR
00273 #define EEAR5_REG EEAR
00274 #define EEAR6_REG EEAR
00275
00276
00277 #define PORTB0_REG PORTB
00278 #define PORTB1_REG PORTB
00279 #define PORTB2_REG PORTB
00280 #define PORTB3_REG PORTB
00281 #define PORTB4_REG PORTB
00282 #define PORTB5_REG PORTB
00283 #define PORTB6_REG PORTB
00284 #define PORTB7_REG PORTB
00285
00286
00287 #define ADCH0_REG ADCH
00288 #define ADCH1_REG ADCH
00289 #define ADCH2_REG ADCH
00290 #define ADCH3_REG ADCH
00291 #define ADCH4_REG ADCH
00292 #define ADCH5_REG ADCH
00293 #define ADCH6_REG ADCH
00294 #define ADCH7_REG ADCH
00295
00296
00297 #define PORTA0_REG PORTA
00298 #define PORTA1_REG PORTA
00299 #define PORTA2_REG PORTA
00300 #define PORTA3_REG PORTA
00301 #define PORTA4_REG PORTA
00302 #define PORTA5_REG PORTA
00303 #define PORTA6_REG PORTA
00304 #define PORTA7_REG PORTA
00305
00306
00307 #define TCNT00_REG TCNT0
00308 #define TCNT01_REG TCNT0
00309 #define TCNT02_REG TCNT0
00310 #define TCNT03_REG TCNT0
00311 #define TCNT04_REG TCNT0
00312 #define TCNT05_REG TCNT0
00313 #define TCNT06_REG TCNT0
00314 #define TCNT07_REG TCNT0
00315
00316
00317 #define TCNT1_0_REG TCNT1
00318 #define TCNT1_1_REG TCNT1
00319 #define TCNT1_2_REG TCNT1
00320 #define TCNT1_3_REG TCNT1
00321 #define TCNT1_4_REG TCNT1
00322 #define TCNT1_5_REG TCNT1
00323 #define TCNT1_6_REG TCNT1
00324 #define TCNT1_7_REG TCNT1
00325
00326
00327 #define TOV0_REG TIFR
00328 #define TOV1_REG TIFR
00329 #define OCF1B_REG TIFR
00330 #define OCF1A_REG TIFR
00331
00332
00333 #define PLOCK_REG PLLCSR
00334 #define PLLE_REG PLLCSR
00335 #define PCKE_REG PLLCSR
00336
00337
00338 #define ADPS0_REG ADCSR
00339 #define ADPS1_REG ADCSR
00340 #define ADPS2_REG ADCSR
00341 #define ADIE_REG ADCSR
00342 #define ADIF_REG ADCSR
00343 #define ADFR_REG ADCSR
00344 #define ADSC_REG ADCSR
00345 #define ADEN_REG ADCSR
00346
00347
00348 #define PINB0_REG PINB
00349 #define PINB1_REG PINB
00350 #define PINB2_REG PINB
00351 #define PINB3_REG PINB
00352 #define PINB4_REG PINB
00353 #define PINB5_REG PINB
00354 #define PINB6_REG PINB
00355 #define PINB7_REG PINB
00356
00357
00358 #define PINA0_REG PINA
00359 #define PINA1_REG PINA
00360 #define PINA2_REG PINA
00361 #define PINA3_REG PINA
00362 #define PINA4_REG PINA
00363 #define PINA5_REG PINA
00364 #define PINA6_REG PINA
00365 #define PINA7_REG PINA
00366
00367
00368 #define SP0_REG SP
00369 #define SP1_REG SP
00370 #define SP2_REG SP
00371 #define SP3_REG SP
00372 #define SP4_REG SP
00373 #define SP5_REG SP
00374 #define SP6_REG SP
00375 #define SP7_REG SP
00376
00377
00378 #define OCR1B0_REG OCR1B
00379 #define OCR1B1_REG OCR1B
00380 #define OCR1B2_REG OCR1B
00381 #define OCR1B3_REG OCR1B
00382 #define OCR1B4_REG OCR1B
00383 #define OCR1B5_REG OCR1B
00384 #define OCR1B6_REG OCR1B
00385 #define OCR1B7_REG OCR1B
00386
00387
00388 #define OCR1C0_REG OCR1C
00389 #define OCR1C1_REG OCR1C
00390 #define OCR1C2_REG OCR1C
00391 #define OCR1C3_REG OCR1C
00392 #define OCR1C4_REG OCR1C
00393 #define OCR1C5_REG OCR1C
00394 #define OCR1C6_REG OCR1C
00395 #define OCR1C7_REG OCR1C
00396
00397
00398 #define OCR1A0_REG OCR1A
00399 #define OCR1A1_REG OCR1A
00400 #define OCR1A2_REG OCR1A
00401 #define OCR1A3_REG OCR1A
00402 #define OCR1A4_REG OCR1A
00403 #define OCR1A5_REG OCR1A
00404 #define OCR1A6_REG OCR1A
00405 #define OCR1A7_REG OCR1A
00406
00407
00408 #define USIDR0_REG USIDR
00409 #define USIDR1_REG USIDR
00410 #define USIDR2_REG USIDR
00411 #define USIDR3_REG USIDR
00412 #define USIDR4_REG USIDR
00413 #define USIDR5_REG USIDR
00414 #define USIDR6_REG USIDR
00415 #define USIDR7_REG USIDR
00416
00417
00418