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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067
00068
00069 #define SIG_OVERFLOW_TOTAL_NUM 0
00070
00071
00072 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
00073
00074
00075 #define PWM_TOTAL_NUM 0
00076
00077
00078 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
00079
00080
00081
00082 #define CLKPS0_REG CLKPR
00083 #define CLKPS1_REG CLKPR
00084 #define CLKPS2_REG CLKPR
00085 #define CLKPS3_REG CLKPR
00086 #define CLKPCE_REG CLKPR
00087
00088
00089 #define ACIS0_REG ACSR
00090 #define ACIS1_REG ACSR
00091 #define ACIC_REG ACSR
00092 #define ACIE_REG ACSR
00093 #define ACI_REG ACSR
00094 #define ACO_REG ACSR
00095 #define ACBG_REG ACSR
00096 #define ACD_REG ACSR
00097
00098
00099 #define PCIE0_REG GIMSK
00100 #define PCIE1_REG GIMSK
00101 #define INT0_REG GIMSK
00102
00103
00104 #define MUX0_REG ADMUX
00105 #define MUX1_REG ADMUX
00106 #define MUX2_REG ADMUX
00107 #define MUX3_REG ADMUX
00108 #define MUX4_REG ADMUX
00109 #define MUX5_REG ADMUX
00110 #define REFS0_REG ADMUX
00111 #define REFS1_REG ADMUX
00112
00113
00114 #define C_REG SREG
00115 #define Z_REG SREG
00116 #define N_REG SREG
00117 #define V_REG SREG
00118 #define S_REG SREG
00119 #define H_REG SREG
00120 #define T_REG SREG
00121 #define I_REG SREG
00122
00123
00124 #define DDB0_REG DDRB
00125 #define DDB1_REG DDRB
00126 #define DDB2_REG DDRB
00127 #define DDB3_REG DDRB
00128
00129
00130 #define WDP0_REG WDTCSR
00131 #define WDP1_REG WDTCSR
00132 #define WDP2_REG WDTCSR
00133 #define WDE_REG WDTCSR
00134 #define WDCE_REG WDTCSR
00135 #define WDP3_REG WDTCSR
00136 #define WDIE_REG WDTCSR
00137 #define WDIF_REG WDTCSR
00138
00139
00140 #define EEDR0_REG EEDR
00141 #define EEDR1_REG EEDR
00142 #define EEDR2_REG EEDR
00143 #define EEDR3_REG EEDR
00144 #define EEDR4_REG EEDR
00145 #define EEDR5_REG EEDR
00146 #define EEDR6_REG EEDR
00147 #define EEDR7_REG EEDR
00148
00149
00150 #define DDA0_REG DDRA
00151 #define DDA1_REG DDRA
00152 #define DDA2_REG DDRA
00153 #define DDA3_REG DDRA
00154 #define DDA4_REG DDRA
00155 #define DDA5_REG DDRA
00156 #define DDA6_REG DDRA
00157 #define DDA7_REG DDRA
00158
00159
00160 #define WGM10_REG TCCR1A
00161 #define WGM11_REG TCCR1A
00162 #define COM1B0_REG TCCR1A
00163 #define COM1B1_REG TCCR1A
00164 #define COM1A0_REG TCCR1A
00165 #define COM1A1_REG TCCR1A
00166
00167
00168 #define PSR10_REG GTCCR
00169 #define TSM_REG GTCCR
00170
00171
00172 #define CS10_REG TCCR1B
00173 #define CS11_REG TCCR1B
00174 #define CS12_REG TCCR1B
00175 #define WGM12_REG TCCR1B
00176 #define WGM13_REG TCCR1B
00177 #define ICES1_REG TCCR1B
00178 #define ICNC1_REG TCCR1B
00179
00180
00181 #define PCIF0_REG GIFR
00182 #define PCIF1_REG GIFR
00183 #define INTF0_REG GIFR
00184
00185
00186 #define CAL0_REG OSCCAL
00187 #define CAL1_REG OSCCAL
00188 #define CAL2_REG OSCCAL
00189 #define CAL3_REG OSCCAL
00190 #define CAL4_REG OSCCAL
00191 #define CAL5_REG OSCCAL
00192 #define CAL6_REG OSCCAL
00193 #define CAL7_REG OSCCAL
00194
00195
00196 #define ADPS0_REG ADCSRA
00197 #define ADPS1_REG ADCSRA
00198 #define ADPS2_REG ADCSRA
00199 #define ADIE_REG ADCSRA
00200 #define ADIF_REG ADCSRA
00201 #define ADATE_REG ADCSRA
00202 #define ADSC_REG ADCSRA
00203 #define ADEN_REG ADCSRA
00204
00205
00206 #define ACME_REG ADCSRB
00207 #define ADTS0_REG ADCSRB
00208 #define ADTS1_REG ADCSRB
00209 #define ADTS2_REG ADCSRB
00210 #define ADLAR_REG ADCSRB
00211 #define BIN_REG ADCSRB
00212
00213
00214
00215
00216
00217
00218
00219
00220
00221
00222
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234 #define ICR1H0_REG ICR1H
00235 #define ICR1H1_REG ICR1H
00236 #define ICR1H2_REG ICR1H
00237 #define ICR1H3_REG ICR1H
00238 #define ICR1H4_REG ICR1H
00239 #define ICR1H5_REG ICR1H
00240 #define ICR1H6_REG ICR1H
00241 #define ICR1H7_REG ICR1H
00242
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254 #define SP0_REG SPL
00255 #define SP1_REG SPL
00256 #define SP2_REG SPL
00257 #define SP3_REG SPL
00258 #define SP4_REG SPL
00259 #define SP5_REG SPL
00260 #define SP6_REG SPL
00261 #define SP7_REG SPL
00262
00263
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274 #define PRADC_REG PRR
00275 #define PRUSI_REG PRR
00276 #define PRTIM0_REG PRR
00277 #define PRTIM1_REG PRR
00278
00279
00280 #define GPIOR10_REG GPIOR1
00281 #define GPIOR11_REG GPIOR1
00282 #define GPIOR12_REG GPIOR1
00283 #define GPIOR13_REG GPIOR1
00284 #define GPIOR14_REG GPIOR1
00285 #define GPIOR15_REG GPIOR1
00286 #define GPIOR16_REG GPIOR1
00287 #define GPIOR17_REG GPIOR1
00288
00289
00290 #define ICR1L0_REG ICR1L
00291 #define ICR1L1_REG ICR1L
00292 #define ICR1L2_REG ICR1L
00293 #define ICR1L3_REG ICR1L
00294 #define ICR1L4_REG ICR1L
00295 #define ICR1L5_REG ICR1L
00296 #define ICR1L6_REG ICR1L
00297 #define ICR1L7_REG ICR1L
00298
00299
00300 #define GPIOR20_REG GPIOR2
00301 #define GPIOR21_REG GPIOR2
00302 #define GPIOR22_REG GPIOR2
00303 #define GPIOR23_REG GPIOR2
00304 #define GPIOR24_REG GPIOR2
00305 #define GPIOR25_REG GPIOR2
00306 #define GPIOR26_REG GPIOR2
00307 #define GPIOR27_REG GPIOR2
00308
00309
00310 #define PORF_REG MCUSR
00311 #define EXTRF_REG MCUSR
00312 #define BORF_REG MCUSR
00313 #define WDRF_REG MCUSR
00314
00315
00316 #define EERE_REG EECR
00317 #define EEPE_REG EECR
00318 #define EEMPE_REG EECR
00319 #define EERIE_REG EECR
00320 #define EEPM0_REG EECR
00321 #define EEPM1_REG EECR
00322
00323
00324 #define SPMEN_REG SPMCSR
00325 #define PGERS_REG SPMCSR
00326 #define PGWRT_REG SPMCSR
00327 #define RFLB_REG SPMCSR
00328 #define CTPB_REG SPMCSR
00329
00330
00331 #define TCNT1L0_REG TCNT1L
00332 #define TCNT1L1_REG TCNT1L
00333 #define TCNT1L2_REG TCNT1L
00334 #define TCNT1L3_REG TCNT1L
00335 #define TCNT1L4_REG TCNT1L
00336 #define TCNT1L5_REG TCNT1L
00337 #define TCNT1L6_REG TCNT1L
00338 #define TCNT1L7_REG TCNT1L
00339
00340
00341 #define PORTB0_REG PORTB
00342 #define PORTB1_REG PORTB
00343 #define PORTB2_REG PORTB
00344 #define PORTB3_REG PORTB
00345
00346
00347 #define ADCL0_REG ADCL
00348 #define ADCL1_REG ADCL
00349 #define ADCL2_REG ADCL
00350 #define ADCL3_REG ADCL
00351 #define ADCL4_REG ADCL
00352 #define ADCL5_REG ADCL
00353 #define ADCL6_REG ADCL
00354 #define ADCL7_REG ADCL
00355
00356
00357 #define USICNT0_REG USISR
00358 #define USICNT1_REG USISR
00359 #define USICNT2_REG USISR
00360 #define USICNT3_REG USISR
00361 #define USIDC_REG USISR
00362 #define USIPF_REG USISR
00363 #define USIOIF_REG USISR
00364 #define USISIF_REG USISR
00365
00366
00367 #define TCNT1H0_REG TCNT1H
00368 #define TCNT1H1_REG TCNT1H
00369 #define TCNT1H2_REG TCNT1H
00370 #define TCNT1H3_REG TCNT1H
00371 #define TCNT1H4_REG TCNT1H
00372 #define TCNT1H5_REG TCNT1H
00373 #define TCNT1H6_REG TCNT1H
00374 #define TCNT1H7_REG TCNT1H
00375
00376
00377 #define ADCH0_REG ADCH
00378 #define ADCH1_REG ADCH
00379 #define ADCH2_REG ADCH
00380 #define ADCH3_REG ADCH
00381 #define ADCH4_REG ADCH
00382 #define ADCH5_REG ADCH
00383 #define ADCH6_REG ADCH
00384 #define ADCH7_REG ADCH
00385
00386
00387 #define PORTA0_REG PORTA
00388 #define PORTA1_REG PORTA
00389 #define PORTA2_REG PORTA
00390 #define PORTA3_REG PORTA
00391 #define PORTA4_REG PORTA
00392 #define PORTA5_REG PORTA
00393 #define PORTA6_REG PORTA
00394 #define PORTA7_REG PORTA
00395
00396
00397 #define TCNT0_0_REG TCNT0
00398 #define TCNT0_1_REG TCNT0
00399 #define TCNT0_2_REG TCNT0
00400 #define TCNT0_3_REG TCNT0
00401 #define TCNT0_4_REG TCNT0
00402 #define TCNT0_5_REG TCNT0
00403 #define TCNT0_6_REG TCNT0
00404 #define TCNT0_7_REG TCNT0
00405
00406
00407 #define GPIOR00_REG GPIOR0
00408 #define GPIOR01_REG GPIOR0
00409 #define GPIOR02_REG GPIOR0
00410 #define GPIOR03_REG GPIOR0
00411 #define GPIOR04_REG GPIOR0
00412 #define GPIOR05_REG GPIOR0
00413 #define GPIOR06_REG GPIOR0
00414 #define GPIOR07_REG GPIOR0
00415
00416
00417 #define PCINT0_REG PCMSK0
00418 #define PCINT1_REG PCMSK0
00419 #define PCINT2_REG PCMSK0
00420 #define PCINT3_REG PCMSK0
00421 #define PCINT4_REG PCMSK0
00422 #define PCINT5_REG PCMSK0
00423 #define PCINT6_REG PCMSK0
00424 #define PCINT7_REG PCMSK0
00425
00426
00427 #define TOIE0_REG TIMSK0
00428 #define OCIE0A_REG TIMSK0
00429 #define OCIE0B_REG TIMSK0
00430
00431
00432 #define TOIE1_REG TIMSK1
00433 #define OCIE1A_REG TIMSK1
00434 #define OCIE1B_REG TIMSK1
00435 #define ICIE1_REG TIMSK1
00436
00437
00438 #define CS00_REG TCCR0B
00439 #define CS01_REG TCCR0B
00440 #define CS02_REG TCCR0B
00441 #define WGM02_REG TCCR0B
00442 #define FOC0B_REG TCCR0B
00443 #define FOC0A_REG TCCR0B
00444
00445
00446 #define FOC1B_REG TCCR1C
00447 #define FOC1A_REG TCCR1C
00448
00449
00450 #define WGM00_REG TCCR0A
00451 #define WGM01_REG TCCR0A
00452 #define COM0B0_REG TCCR0A
00453 #define COM0B1_REG TCCR0A
00454 #define COM0A0_REG TCCR0A
00455 #define COM0A1_REG TCCR0A
00456
00457
00458 #define EEAR8_REG EEARH
00459
00460
00461 #define USITC_REG USICR
00462 #define USICLK_REG USICR
00463 #define USICS0_REG USICR
00464 #define USICS1_REG USICR
00465 #define USIWM0_REG USICR
00466 #define USIWM1_REG USICR
00467 #define USIOIE_REG USICR
00468 #define USISIE_REG USICR
00469
00470
00471 #define EEAR0_REG EEARL
00472 #define EEAR1_REG EEARL
00473 #define EEAR2_REG EEARL
00474 #define EEAR3_REG EEARL
00475 #define EEAR4_REG EEARL
00476 #define EEAR5_REG EEARL
00477 #define EEAR6_REG EEARL
00478 #define EEAR7_REG EEARL
00479
00480
00481 #define PCINT8_REG PCMSK1
00482 #define PCINT9_REG PCMSK1
00483 #define PCINT10_REG PCMSK1
00484 #define PCINT11_REG PCMSK1
00485
00486
00487 #define PINB0_REG PINB
00488 #define PINB1_REG PINB
00489 #define PINB2_REG PINB
00490 #define PINB3_REG PINB
00491
00492
00493 #define PINA0_REG PINA
00494 #define PINA1_REG PINA
00495 #define PINA2_REG PINA
00496 #define PINA3_REG PINA
00497 #define PINA4_REG PINA
00498 #define PINA5_REG PINA
00499 #define PINA6_REG PINA
00500 #define PINA7_REG PINA
00501
00502
00503 #define ADC0D_REG DIDR0
00504 #define ADC1D_REG DIDR0
00505 #define ADC2D_REG DIDR0
00506 #define ADC3D_REG DIDR0
00507 #define ADC4D_REG DIDR0
00508 #define ADC5D_REG DIDR0
00509 #define ADC6D_REG DIDR0
00510 #define ADC7D_REG DIDR0
00511
00512
00513 #define ISC00_REG MCUCR
00514 #define ISC01_REG MCUCR
00515 #define SM0_REG MCUCR
00516 #define SM1_REG MCUCR
00517 #define SE_REG MCUCR
00518 #define PUD_REG MCUCR
00519
00520
00521
00522
00523
00524
00525
00526
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539
00540
00541 #define USIDR0_REG USIDR
00542 #define USIDR1_REG USIDR
00543 #define USIDR2_REG USIDR
00544 #define USIDR3_REG USIDR
00545 #define USIDR4_REG USIDR
00546 #define USIDR5_REG USIDR
00547 #define USIDR6_REG USIDR
00548 #define USIDR7_REG USIDR
00549
00550
00551 #define USIBR0_REG USIBR
00552 #define USIBR1_REG USIBR
00553 #define USIBR2_REG USIBR
00554 #define USIBR3_REG USIBR
00555 #define USIBR4_REG USIBR
00556 #define USIBR5_REG USIBR
00557 #define USIBR6_REG USIBR
00558 #define USIBR7_REG USIBR
00559
00560
00561 #define TOV0_REG TIFR0
00562 #define OCF0A_REG TIFR0
00563 #define OCF0B_REG TIFR0
00564
00565
00566 #define TOV1_REG TIFR1
00567 #define OCF1A_REG TIFR1
00568 #define OCF1B_REG TIFR1
00569 #define ICF1_REG TIFR1
00570
00571
00572 #define ADC0_PORT PORTA
00573 #define ADC0_BIT 0
00574 #define AREF_PORT PORTA
00575 #define AREF_BIT 0
00576 #define PCINT0_PORT PORTA
00577 #define PCINT0_BIT 0
00578
00579 #define ADC1_PORT PORTA
00580 #define ADC1_BIT 1
00581 #define AIN0_PORT PORTA
00582 #define AIN0_BIT 1
00583 #define PCINT1_PORT PORTA
00584 #define PCINT1_BIT 1
00585
00586 #define ADC2_PORT PORTA
00587 #define ADC2_BIT 2
00588 #define AIN1_PORT PORTA
00589 #define AIN1_BIT 2
00590 #define PCINT2_PORT PORTA
00591 #define PCINT2_BIT 2
00592
00593 #define ADC3_PORT PORTA
00594 #define ADC3_BIT 3
00595 #define T0_PORT PORTA
00596 #define T0_BIT 3
00597 #define PCINT3_PORT PORTA
00598 #define PCINT3_BIT 3
00599
00600 #define ADC4_PORT PORTA
00601 #define ADC4_BIT 4
00602 #define USCK_PORT PORTA
00603 #define USCK_BIT 4
00604 #define SCL_PORT PORTA
00605 #define SCL_BIT 4
00606 #define T1_PORT PORTA
00607 #define T1_BIT 4
00608 #define PCINT4_PORT PORTA
00609 #define PCINT4_BIT 4
00610
00611 #define ADC5_PORT PORTA
00612 #define ADC5_BIT 5
00613 #define DO_PORT PORTA
00614 #define DO_BIT 5
00615 #define MISO_PORT PORTA
00616 #define MISO_BIT 5
00617 #define OC1B_PORT PORTA
00618 #define OC1B_BIT 5
00619 #define PCINT5_PORT PORTA
00620 #define PCINT5_BIT 5
00621
00622 #define PCINT6_PORT PORTA
00623 #define PCINT6_BIT 6
00624 #define OC1A_PORT PORTA
00625 #define OC1A_BIT 6
00626 #define DI_PORT PORTA
00627 #define DI_BIT 6
00628 #define SDA_PORT PORTA
00629 #define SDA_BIT 6
00630 #define MOSI_PORT PORTA
00631 #define MOSI_BIT 6
00632 #define ADC6_PORT PORTA
00633 #define ADC6_BIT 6
00634
00635 #define PCINT7_PORT PORTA
00636 #define PCINT7_BIT 7
00637 #define ICP1_PORT PORTA
00638 #define ICP1_BIT 7
00639 #define OC0B_PORT PORTA
00640 #define OC0B_BIT 7
00641 #define ADC7_PORT PORTA
00642 #define ADC7_BIT 7
00643
00644 #define PCINT8_PORT PORTB
00645 #define PCINT8_BIT 0
00646 #define XTAL1_PORT PORTB
00647 #define XTAL1_BIT 0
00648
00649 #define PCINT9_PORT PORTB
00650 #define PCINT9_BIT 1
00651 #define XTAL2_PORT PORTB
00652 #define XTAL2_BIT 1
00653
00654 #define PCINT10_PORT PORTB
00655 #define PCINT10_BIT 2
00656 #define INT0_PORT PORTB
00657 #define INT0_BIT 2
00658 #define OC0A_PORT PORTB
00659 #define OC0A_BIT 2
00660 #define CKOUT_PORT PORTB
00661 #define CKOUT_BIT 2
00662
00663 #define PCINT11_PORT PORTB
00664 #define PCINT11_BIT 3
00665 #define RESET_PORT PORTB
00666 #define RESET_BIT 3
00667 #define dW_PORT PORTB
00668 #define dW_BIT 3
00669
00670