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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_32 3
00032 #define TIMER0_PRESCALER_DIV_64 4
00033 #define TIMER0_PRESCALER_DIV_128 5
00034 #define TIMER0_PRESCALER_DIV_256 6
00035 #define TIMER0_PRESCALER_DIV_1024 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 32
00041 #define TIMER0_PRESCALER_REG_4 64
00042 #define TIMER0_PRESCALER_REG_5 128
00043 #define TIMER0_PRESCALER_REG_6 256
00044 #define TIMER0_PRESCALER_REG_7 1024
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER0A_AVAILABLE
00069 #define TIMER1_AVAILABLE
00070 #define TIMER1A_AVAILABLE
00071 #define TIMER1B_AVAILABLE
00072
00073
00074 #define SIG_OVERFLOW0_NUM 0
00075 #define SIG_OVERFLOW1_NUM 1
00076 #define SIG_OVERFLOW_TOTAL_NUM 2
00077
00078
00079 #define SIG_OUTPUT_COMPARE0A_NUM 0
00080 #define SIG_OUTPUT_COMPARE1A_NUM 1
00081 #define SIG_OUTPUT_COMPARE1B_NUM 2
00082 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
00083
00084
00085 #define PWM0A_NUM 0
00086 #define PWM1A_NUM 1
00087 #define PWM1B_NUM 2
00088 #define PWM_TOTAL_NUM 3
00089
00090
00091 #define SIG_INPUT_CAPTURE1_NUM 0
00092 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00093
00094
00095
00096 #define PORTB0_REG PORTB
00097 #define PORTB1_REG PORTB
00098 #define PORTB2_REG PORTB
00099 #define PORTB3_REG PORTB
00100 #define PORTB4_REG PORTB
00101 #define PORTB5_REG PORTB
00102 #define PORTB6_REG PORTB
00103 #define PORTB7_REG PORTB
00104
00105
00106 #define LID0_REG LINIDR
00107 #define LID1_REG LINIDR
00108 #define LID2_REG LINIDR
00109 #define LID3_REG LINIDR
00110 #define LID4_REG LINIDR
00111 #define LID5_REG LINIDR
00112 #define LP0_REG LINIDR
00113 #define LP1_REG LINIDR
00114
00115
00116 #define CLKPS0_REG CLKPR
00117 #define CLKPS1_REG CLKPR
00118 #define CLKPS2_REG CLKPR
00119 #define CLKPS3_REG CLKPR
00120 #define CLKPCE_REG CLKPR
00121
00122
00123 #define SP8_REG SPH
00124 #define SP9_REG SPH
00125 #define SP10_REG SPH
00126
00127
00128 #define WDP0_REG WDTCR
00129 #define WDP1_REG WDTCR
00130 #define WDP2_REG WDTCR
00131 #define WDE_REG WDTCR
00132 #define WDCE_REG WDTCR
00133 #define WDP3_REG WDTCR
00134 #define WDIE_REG WDTCR
00135 #define WDIF_REG WDTCR
00136
00137
00138 #define PCIF0_REG PCIFR
00139 #define PCIF1_REG PCIFR
00140
00141
00142 #define LBT0_REG LINBTR
00143 #define LBT1_REG LINBTR
00144 #define LBT2_REG LINBTR
00145 #define LBT3_REG LINBTR
00146 #define LBT4_REG LINBTR
00147 #define LBT5_REG LINBTR
00148 #define LDISR_REG LINBTR
00149
00150
00151 #define MUX0_REG ADMUX
00152 #define MUX1_REG ADMUX
00153 #define MUX2_REG ADMUX
00154 #define MUX3_REG ADMUX
00155 #define MUX4_REG ADMUX
00156 #define ADLAR_REG ADMUX
00157 #define REFS0_REG ADMUX
00158 #define REFS1_REG ADMUX
00159
00160
00161 #define ISC00_REG EICRA
00162 #define ISC01_REG EICRA
00163 #define ISC10_REG EICRA
00164 #define ISC11_REG EICRA
00165
00166
00167 #define PUDA_REG PORTCR
00168 #define PUDB_REG PORTCR
00169 #define BBMA_REG PORTCR
00170 #define BBMB_REG PORTCR
00171
00172
00173 #define C_REG SREG
00174 #define Z_REG SREG
00175 #define N_REG SREG
00176 #define V_REG SREG
00177 #define S_REG SREG
00178 #define H_REG SREG
00179 #define T_REG SREG
00180 #define I_REG SREG
00181
00182
00183 #define DDB0_REG DDRB
00184 #define DDB1_REG DDRB
00185 #define DDB2_REG DDRB
00186 #define DDB3_REG DDRB
00187 #define DDB4_REG DDRB
00188 #define DDB5_REG DDRB
00189 #define DDB6_REG DDRB
00190 #define DDB7_REG DDRB
00191
00192
00193 #define XREFEN_REG AMISCR
00194 #define AREFEN_REG AMISCR
00195 #define ISRCEN_REG AMISCR
00196
00197
00198 #define CSEL0_REG CLKSELR
00199 #define CSEL1_REG CLKSELR
00200 #define CSEL2_REG CLKSELR
00201 #define CSEL3_REG CLKSELR
00202 #define CSUT0_REG CLKSELR
00203 #define CSUT1_REG CLKSELR
00204 #define COUT_REG CLKSELR
00205
00206
00207 #define EEDR0_REG EEDR
00208 #define EEDR1_REG EEDR
00209 #define EEDR2_REG EEDR
00210 #define EEDR3_REG EEDR
00211 #define EEDR4_REG EEDR
00212 #define EEDR5_REG EEDR
00213 #define EEDR6_REG EEDR
00214 #define EEDR7_REG EEDR
00215
00216
00217 #define OC1AU_REG TCCR1D
00218 #define OC1AV_REG TCCR1D
00219 #define OC1AW_REG TCCR1D
00220 #define OC1AX_REG TCCR1D
00221 #define OC1BU_REG TCCR1D
00222 #define OC1BV_REG TCCR1D
00223 #define OC1BW_REG TCCR1D
00224 #define OC1BX_REG TCCR1D
00225
00226
00227 #define DDA0_REG DDRA
00228 #define DDA1_REG DDRA
00229 #define DDA2_REG DDRA
00230 #define DDA3_REG DDRA
00231 #define DDA4_REG DDRA
00232 #define DDA5_REG DDRA
00233 #define DDA6_REG DDRA
00234 #define DDA7_REG DDRA
00235
00236
00237 #define WGM10_REG TCCR1A
00238 #define WGM11_REG TCCR1A
00239 #define COM1B0_REG TCCR1A
00240 #define COM1B1_REG TCCR1A
00241 #define COM1A0_REG TCCR1A
00242 #define COM1A1_REG TCCR1A
00243
00244
00245 #define LINDX0_REG LINSEL
00246 #define LINDX1_REG LINSEL
00247 #define LINDX2_REG LINSEL
00248 #define LAINC_REG LINSEL
00249
00250
00251 #define FOC1B_REG TCCR1C
00252 #define FOC1A_REG TCCR1C
00253
00254
00255 #define LCMD0_REG LINCR
00256 #define LCMD1_REG LINCR
00257 #define LCMD2_REG LINCR
00258 #define LENA_REG LINCR
00259 #define LCONF0_REG LINCR
00260 #define LCONF1_REG LINCR
00261 #define LIN13_REG LINCR
00262 #define LSWRES_REG LINCR
00263
00264
00265 #define TOV1_REG TIFR1
00266 #define OCF1A_REG TIFR1
00267 #define OCF1B_REG TIFR1
00268 #define ICF1_REG TIFR1
00269
00270
00271 #define ICR1H0_REG ICR1H
00272 #define ICR1H1_REG ICR1H
00273 #define ICR1H2_REG ICR1H
00274 #define ICR1H3_REG ICR1H
00275 #define ICR1H4_REG ICR1H
00276 #define ICR1H5_REG ICR1H
00277 #define ICR1H6_REG ICR1H
00278 #define ICR1H7_REG ICR1H
00279
00280
00281 #define PSR1_REG GTCCR
00282 #define PSR0_REG GTCCR
00283 #define TSM_REG GTCCR
00284
00285
00286 #define ADPS0_REG ADCSRA
00287 #define ADPS1_REG ADCSRA
00288 #define ADPS2_REG ADCSRA
00289 #define ADIE_REG ADCSRA
00290 #define ADIF_REG ADCSRA
00291 #define ADATE_REG ADCSRA
00292 #define ADSC_REG ADCSRA
00293 #define ADEN_REG ADCSRA
00294
00295
00296 #define ADTS0_REG ADCSRB
00297 #define ADTS1_REG ADCSRB
00298 #define ADTS2_REG ADCSRB
00299 #define BIN_REG ADCSRB
00300 #define ACIR0_REG ADCSRB
00301 #define ACIR1_REG ADCSRB
00302 #define ACME_REG ADCSRB
00303
00304
00305 #define SPDR0_REG SPDR
00306 #define SPDR1_REG SPDR
00307 #define SPDR2_REG SPDR
00308 #define SPDR3_REG SPDR
00309 #define SPDR4_REG SPDR
00310 #define SPDR5_REG SPDR
00311 #define SPDR6_REG SPDR
00312 #define SPDR7_REG SPDR
00313
00314
00315 #define OCR00_REG OCR0A
00316 #define OCR01_REG OCR0A
00317 #define OCR02_REG OCR0A
00318 #define OCR03_REG OCR0A
00319 #define OCR04_REG OCR0A
00320 #define OCR05_REG OCR0A
00321 #define OCR06_REG OCR0A
00322 #define OCR07_REG OCR0A
00323
00324
00325 #define SPI2X_REG SPSR
00326 #define WCOL_REG SPSR
00327 #define SPIF_REG SPSR
00328
00329
00330 #define ACIS0_REG ACSR
00331 #define ACIS1_REG ACSR
00332 #define ACIC_REG ACSR
00333 #define ACIE_REG ACSR
00334 #define ACI_REG ACSR
00335 #define ACO_REG ACSR
00336 #define ACIRS_REG ACSR
00337 #define ACD_REG ACSR
00338
00339
00340 #define USIPOS_REG USIPP
00341
00342
00343
00344
00345
00346
00347
00348
00349
00350
00351
00352
00353 #define ICR1L0_REG ICR1L
00354 #define ICR1L1_REG ICR1L
00355 #define ICR1L2_REG ICR1L
00356 #define ICR1L3_REG ICR1L
00357 #define ICR1L4_REG ICR1L
00358 #define ICR1L5_REG ICR1L
00359 #define ICR1L6_REG ICR1L
00360 #define ICR1L7_REG ICR1L
00361
00362
00363
00364
00365
00366
00367
00368
00369
00370
00371
00372
00373 #define PRADC_REG PRR
00374 #define PRUSI_REG PRR
00375 #define PRTIM0_REG PRR
00376 #define PRTIM1_REG PRR
00377 #define PRSPI_REG PRR
00378 #define PRLIN_REG PRR
00379
00380
00381 #define GPIOR10_REG GPIOR1
00382 #define GPIOR11_REG GPIOR1
00383 #define GPIOR12_REG GPIOR1
00384 #define GPIOR13_REG GPIOR1
00385 #define GPIOR14_REG GPIOR1
00386 #define GPIOR15_REG GPIOR1
00387 #define GPIOR16_REG GPIOR1
00388 #define GPIOR17_REG GPIOR1
00389
00390
00391 #define SP0_REG SPL
00392 #define SP1_REG SPL
00393 #define SP2_REG SPL
00394 #define SP3_REG SPL
00395 #define SP4_REG SPL
00396 #define SP5_REG SPL
00397 #define SP6_REG SPL
00398 #define SP7_REG SPL
00399
00400
00401 #define USITC_REG USICR
00402 #define USICLK_REG USICR
00403 #define USICS0_REG USICR
00404 #define USICS1_REG USICR
00405 #define USIWM0_REG USICR
00406 #define USIWM1_REG USICR
00407 #define USIOIE_REG USICR
00408 #define USISIE_REG USICR
00409
00410
00411 #define SPMEN_REG SPMCSR
00412 #define PGERS_REG SPMCSR
00413 #define PGWRT_REG SPMCSR
00414 #define RFLB_REG SPMCSR
00415 #define CTPB_REG SPMCSR
00416 #define SIGRD_REG SPMCSR
00417 #define RWWSB_REG SPMCSR
00418
00419
00420 #define ADCL0_REG ADCL
00421 #define ADCL1_REG ADCL
00422 #define ADCL2_REG ADCL
00423 #define ADCL3_REG ADCL
00424 #define ADCL4_REG ADCL
00425 #define ADCL5_REG ADCL
00426 #define ADCL6_REG ADCL
00427 #define ADCL7_REG ADCL
00428
00429
00430 #define PORF_REG MCUSR
00431 #define EXTRF_REG MCUSR
00432 #define BORF_REG MCUSR
00433 #define WDRF_REG MCUSR
00434
00435
00436 #define LDIV0_REG LINBRRL
00437 #define LDIV1_REG LINBRRL
00438 #define LDIV2_REG LINBRRL
00439 #define LDIV3_REG LINBRRL
00440 #define LDIV4_REG LINBRRL
00441 #define LDIV5_REG LINBRRL
00442 #define LDIV6_REG LINBRRL
00443 #define LDIV7_REG LINBRRL
00444
00445
00446 #define EERE_REG EECR
00447 #define EEPE_REG EECR
00448 #define EEMPE_REG EECR
00449 #define EERIE_REG EECR
00450 #define EEPM0_REG EECR
00451 #define EEPM1_REG EECR
00452
00453
00454 #define SE_REG SMCR
00455 #define SM0_REG SMCR
00456 #define SM1_REG SMCR
00457
00458
00459 #define LDIV8_REG LINBRRH
00460 #define LDIV9_REG LINBRRH
00461 #define LDIV10_REG LINBRRH
00462 #define LDIV11_REG LINBRRH
00463
00464
00465 #define LDATA0_REG LINDAT
00466 #define LDATA1_REG LINDAT
00467 #define LDATA2_REG LINDAT
00468 #define LDATA3_REG LINDAT
00469 #define LDATA4_REG LINDAT
00470 #define LDATA5_REG LINDAT
00471 #define LDATA6_REG LINDAT
00472 #define LDATA7_REG LINDAT
00473
00474
00475 #define CAL0_REG OSCCAL
00476 #define CAL1_REG OSCCAL
00477 #define CAL2_REG OSCCAL
00478 #define CAL3_REG OSCCAL
00479 #define CAL4_REG OSCCAL
00480 #define CAL5_REG OSCCAL
00481 #define CAL6_REG OSCCAL
00482 #define CAL7_REG OSCCAL
00483
00484
00485 #define TCNT1L0_REG TCNT1L
00486 #define TCNT1L1_REG TCNT1L
00487 #define TCNT1L2_REG TCNT1L
00488 #define TCNT1L3_REG TCNT1L
00489 #define TCNT1L4_REG TCNT1L
00490 #define TCNT1L5_REG TCNT1L
00491 #define TCNT1L6_REG TCNT1L
00492 #define TCNT1L7_REG TCNT1L
00493
00494
00495 #define TCNT1H0_REG TCNT1H
00496 #define TCNT1H1_REG TCNT1H
00497 #define TCNT1H2_REG TCNT1H
00498 #define TCNT1H3_REG TCNT1H
00499 #define TCNT1H4_REG TCNT1H
00500 #define TCNT1H5_REG TCNT1H
00501 #define TCNT1H6_REG TCNT1H
00502 #define TCNT1H7_REG TCNT1H
00503
00504
00505 #define LENRXOK_REG LINENIR
00506 #define LENTXOK_REG LINENIR
00507 #define LENIDOK_REG LINENIR
00508 #define LENERR_REG LINENIR
00509
00510
00511 #define USICNT0_REG USISR
00512 #define USICNT1_REG USISR
00513 #define USICNT2_REG USISR
00514 #define USICNT3_REG USISR
00515 #define USIDC_REG USISR
00516 #define USIPF_REG USISR
00517 #define USIOIF_REG USISR
00518 #define USISIF_REG USISR
00519
00520
00521 #define LBERR_REG LINERR
00522 #define LCERR_REG LINERR
00523 #define LPERR_REG LINERR
00524 #define LSERR_REG LINERR
00525 #define LFERR_REG LINERR
00526 #define LOVERR_REG LINERR
00527 #define LTOERR_REG LINERR
00528 #define LABORT_REG LINERR
00529
00530
00531 #define ADCH0_REG ADCH
00532 #define ADCH1_REG ADCH
00533 #define ADCH2_REG ADCH
00534 #define ADCH3_REG ADCH
00535 #define ADCH4_REG ADCH
00536 #define ADCH5_REG ADCH
00537 #define ADCH6_REG ADCH
00538 #define ADCH7_REG ADCH
00539
00540
00541 #define PORTA0_REG PORTA
00542 #define PORTA1_REG PORTA
00543 #define PORTA2_REG PORTA
00544 #define PORTA3_REG PORTA
00545 #define PORTA4_REG PORTA
00546 #define PORTA5_REG PORTA
00547 #define PORTA6_REG PORTA
00548 #define PORTA7_REG PORTA
00549
00550
00551 #define TOV0_REG TIFR0
00552 #define OCF0A_REG TIFR0
00553
00554
00555 #define TCNT00_REG TCNT0
00556 #define TCNT01_REG TCNT0
00557 #define TCNT02_REG TCNT0
00558 #define TCNT03_REG TCNT0
00559 #define TCNT04_REG TCNT0
00560 #define TCNT05_REG TCNT0
00561 #define TCNT06_REG TCNT0
00562 #define TCNT07_REG TCNT0
00563
00564
00565 #define PCIE0_REG PCICR
00566 #define PCIE1_REG PCICR
00567
00568
00569 #define GPIOR00_REG GPIOR0
00570 #define GPIOR01_REG GPIOR0
00571 #define GPIOR02_REG GPIOR0
00572 #define GPIOR03_REG GPIOR0
00573 #define GPIOR04_REG GPIOR0
00574 #define GPIOR05_REG GPIOR0
00575 #define GPIOR06_REG GPIOR0
00576 #define GPIOR07_REG GPIOR0
00577
00578
00579 #define EEAR0_REG EEARL
00580 #define EEAR1_REG EEARL
00581 #define EEAR2_REG EEARL
00582 #define EEAR3_REG EEARL
00583 #define EEAR4_REG EEARL
00584 #define EEAR5_REG EEARL
00585 #define EEAR6_REG EEARL
00586 #define EEAR7_REG EEARL
00587
00588
00589 #define TOIE0_REG TIMSK0
00590 #define OCIE0A_REG TIMSK0
00591
00592
00593 #define TOIE1_REG TIMSK1
00594 #define OCIE1A_REG TIMSK1
00595 #define OCIE1B_REG TIMSK1
00596 #define ICIE1_REG TIMSK1
00597
00598
00599 #define CS00_REG TCCR0B
00600 #define CS01_REG TCCR0B
00601 #define CS02_REG TCCR0B
00602 #define FOC0A_REG TCCR0B
00603
00604
00605 #define WGM00_REG TCCR0A
00606 #define WGM01_REG TCCR0A
00607 #define COM0A0_REG TCCR0A
00608 #define COM0A1_REG TCCR0A
00609
00610
00611 #define EEAR8_REG EEARH
00612
00613
00614 #define GPIOR20_REG GPIOR2
00615 #define GPIOR21_REG GPIOR2
00616 #define GPIOR22_REG GPIOR2
00617 #define GPIOR23_REG GPIOR2
00618 #define GPIOR24_REG GPIOR2
00619 #define GPIOR25_REG GPIOR2
00620 #define GPIOR26_REG GPIOR2
00621 #define GPIOR27_REG GPIOR2
00622
00623
00624 #define PCINT0_REG PCMSK0
00625 #define PCINT1_REG PCMSK0
00626 #define PCINT2_REG PCMSK0
00627 #define PCINT3_REG PCMSK0
00628 #define PCINT4_REG PCMSK0
00629 #define PCINT5_REG PCMSK0
00630 #define PCINT6_REG PCMSK0
00631 #define PCINT7_REG PCMSK0
00632
00633
00634 #define PCINT8_REG PCMSK1
00635 #define PCINT9_REG PCMSK1
00636 #define PCINT10_REG PCMSK1
00637 #define PCINT11_REG PCMSK1
00638 #define PCINT12_REG PCMSK1
00639 #define PCINT13_REG PCMSK1
00640 #define PCINT14_REG PCMSK1
00641 #define PCINT15_REG PCMSK1
00642
00643
00644 #define LRXDL0_REG LINDLR
00645 #define LRXDL1_REG LINDLR
00646 #define LRXDL2_REG LINDLR
00647 #define LRXDL3_REG LINDLR
00648 #define LTXDL0_REG LINDLR
00649 #define LTXDL1_REG LINDLR
00650 #define LTXDL2_REG LINDLR
00651 #define LTXDL3_REG LINDLR
00652
00653
00654 #define DWDR0_REG DWDR
00655 #define DWDR1_REG DWDR
00656 #define DWDR2_REG DWDR
00657 #define DWDR3_REG DWDR
00658 #define DWDR4_REG DWDR
00659 #define DWDR5_REG DWDR
00660 #define DWDR6_REG DWDR
00661 #define DWDR7_REG DWDR
00662
00663
00664 #define INTF0_REG EIFR
00665 #define INTF1_REG EIFR
00666
00667
00668 #define LRXOK_REG LINSIR
00669 #define LTXOK_REG LINSIR
00670 #define LIDOK_REG LINSIR
00671 #define LERR_REG LINSIR
00672 #define LBUSY_REG LINSIR
00673 #define LIDST0_REG LINSIR
00674 #define LIDST1_REG LINSIR
00675 #define LIDST2_REG LINSIR
00676
00677
00678 #define ADC0D_REG DIDR0
00679 #define ADC1D_REG DIDR0
00680 #define ADC2D_REG DIDR0
00681 #define ADC3D_REG DIDR0
00682 #define ADC4D_REG DIDR0
00683 #define ADC5D_REG DIDR0
00684 #define ADC6D_REG DIDR0
00685 #define ADC7D_REG DIDR0
00686
00687
00688 #define ADC8D_REG DIDR1
00689 #define ADC9D_REG DIDR1
00690 #define ADC10D_REG DIDR1
00691
00692
00693 #define CLKC0_REG CLKCSR
00694 #define CLKC1_REG CLKCSR
00695 #define CLKC2_REG CLKCSR
00696 #define CLKC3_REG CLKCSR
00697 #define CLKRDY_REG CLKCSR
00698 #define CLKCCE_REG CLKCSR
00699
00700
00701 #define PUD_REG MCUCR
00702 #define BODS_REG MCUCR
00703 #define BODSE_REG MCUCR
00704
00705
00706
00707
00708
00709
00710
00711
00712
00713
00714
00715
00716
00717
00718
00719
00720
00721
00722
00723
00724
00725
00726 #define SPR0_REG SPCR
00727 #define SPR1_REG SPCR
00728 #define CPHA_REG SPCR
00729 #define CPOL_REG SPCR
00730 #define MSTR_REG SPCR
00731 #define DORD_REG SPCR
00732 #define SPE_REG SPCR
00733 #define SPIE_REG SPCR
00734
00735
00736 #define PINB0_REG PINB
00737 #define PINB1_REG PINB
00738 #define PINB2_REG PINB
00739 #define PINB3_REG PINB
00740 #define PINB4_REG PINB
00741 #define PINB5_REG PINB
00742 #define PINB6_REG PINB
00743 #define PINB7_REG PINB
00744
00745
00746 #define USIBR0_REG USIBR
00747 #define USIBR1_REG USIBR
00748 #define USIBR2_REG USIBR
00749 #define USIBR3_REG USIBR
00750 #define USIBR4_REG USIBR
00751 #define USIBR5_REG USIBR
00752 #define USIBR6_REG USIBR
00753 #define USIBR7_REG USIBR
00754
00755
00756 #define INT0_REG EIMSK
00757 #define INT1_REG EIMSK
00758
00759
00760 #define CS10_REG TCCR1B
00761 #define CS11_REG TCCR1B
00762 #define CS12_REG TCCR1B
00763 #define WGM12_REG TCCR1B
00764 #define WGM13_REG TCCR1B
00765 #define ICES1_REG TCCR1B
00766 #define ICNC1_REG TCCR1B
00767
00768
00769 #define PINA0_REG PINA
00770 #define PINA1_REG PINA
00771 #define PINA2_REG PINA
00772 #define PINA3_REG PINA
00773 #define PINA4_REG PINA
00774 #define PINA5_REG PINA
00775 #define PINA6_REG PINA
00776 #define PINA7_REG PINA
00777
00778
00779 #define USIDR0_REG USIDR
00780 #define USIDR1_REG USIDR
00781 #define USIDR2_REG USIDR
00782 #define USIDR3_REG USIDR
00783 #define USIDR4_REG USIDR
00784 #define USIDR5_REG USIDR
00785 #define USIDR6_REG USIDR
00786 #define USIDR7_REG USIDR
00787
00788
00789 #define TCR0BUB_REG ASSR
00790 #define TCR0AUB_REG ASSR
00791 #define OCR0AUB_REG ASSR
00792 #define TCN0UB_REG ASSR
00793 #define AS0_REG ASSR
00794 #define EXCLK_REG ASSR
00795
00796
00797