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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_32 3
00032 #define TIMER0_PRESCALER_DIV_64 4
00033 #define TIMER0_PRESCALER_DIV_128 5
00034 #define TIMER0_PRESCALER_DIV_256 6
00035 #define TIMER0_PRESCALER_DIV_1024 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 32
00041 #define TIMER0_PRESCALER_REG_4 64
00042 #define TIMER0_PRESCALER_REG_5 128
00043 #define TIMER0_PRESCALER_REG_6 256
00044 #define TIMER0_PRESCALER_REG_7 1024
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_64 3
00070 #define TIMER2_PRESCALER_DIV_256 4
00071 #define TIMER2_PRESCALER_DIV_1024 5
00072 #define TIMER2_PRESCALER_DIV_FALL 6
00073 #define TIMER2_PRESCALER_DIV_RISE 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 64
00079 #define TIMER2_PRESCALER_REG_4 256
00080 #define TIMER2_PRESCALER_REG_5 1024
00081 #define TIMER2_PRESCALER_REG_6 -1
00082 #define TIMER2_PRESCALER_REG_7 -2
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_FALL 6
00092 #define TIMER3_PRESCALER_DIV_RISE 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 -1
00101 #define TIMER3_PRESCALER_REG_7 -2
00102
00103
00104
00105 #define TIMER0_AVAILABLE
00106 #define TIMER1_AVAILABLE
00107 #define TIMER1A_AVAILABLE
00108 #define TIMER1B_AVAILABLE
00109 #define TIMER1C_AVAILABLE
00110 #define TIMER2_AVAILABLE
00111 #define TIMER3_AVAILABLE
00112 #define TIMER3A_AVAILABLE
00113 #define TIMER3B_AVAILABLE
00114 #define TIMER3C_AVAILABLE
00115
00116
00117 #define SIG_OVERFLOW0_NUM 0
00118 #define SIG_OVERFLOW1_NUM 1
00119 #define SIG_OVERFLOW2_NUM 2
00120 #define SIG_OVERFLOW3_NUM 3
00121 #define SIG_OVERFLOW_TOTAL_NUM 4
00122
00123
00124 #define SIG_OUTPUT_COMPARE0_NUM 0
00125 #define SIG_OUTPUT_COMPARE1A_NUM 1
00126 #define SIG_OUTPUT_COMPARE1B_NUM 2
00127 #define SIG_OUTPUT_COMPARE1C_NUM 3
00128 #define SIG_OUTPUT_COMPARE2_NUM 4
00129 #define SIG_OUTPUT_COMPARE3A_NUM 5
00130 #define SIG_OUTPUT_COMPARE3B_NUM 6
00131 #define SIG_OUTPUT_COMPARE3C_NUM 7
00132 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
00133
00134
00135 #define PWM0_NUM 0
00136 #define PWM1A_NUM 1
00137 #define PWM1B_NUM 2
00138 #define PWM1C_NUM 3
00139 #define PWM2_NUM 4
00140 #define PWM3A_NUM 5
00141 #define PWM3B_NUM 6
00142 #define PWM3C_NUM 7
00143 #define PWM_TOTAL_NUM 8
00144
00145
00146 #define SIG_INPUT_CAPTURE1_NUM 0
00147 #define SIG_INPUT_CAPTURE3_NUM 1
00148 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00149
00150
00151
00152 #define WDP0_REG WDTCR
00153 #define WDP1_REG WDTCR
00154 #define WDP2_REG WDTCR
00155 #define WDE_REG WDTCR
00156 #define WDCE_REG WDTCR
00157
00158
00159 #define MUX0_REG ADMUX
00160 #define MUX1_REG ADMUX
00161 #define MUX2_REG ADMUX
00162 #define MUX3_REG ADMUX
00163 #define MUX4_REG ADMUX
00164 #define ADLAR_REG ADMUX
00165 #define REFS0_REG ADMUX
00166 #define REFS1_REG ADMUX
00167
00168
00169 #define EEDR0_REG EEDR
00170 #define EEDR1_REG EEDR
00171 #define EEDR2_REG EEDR
00172 #define EEDR3_REG EEDR
00173 #define EEDR4_REG EEDR
00174 #define EEDR5_REG EEDR
00175 #define EEDR6_REG EEDR
00176 #define EEDR7_REG EEDR
00177
00178
00179 #define SPDR0_REG SPDR
00180 #define SPDR1_REG SPDR
00181 #define SPDR2_REG SPDR
00182 #define SPDR3_REG SPDR
00183 #define SPDR4_REG SPDR
00184 #define SPDR5_REG SPDR
00185 #define SPDR6_REG SPDR
00186 #define SPDR7_REG SPDR
00187
00188
00189 #define SPI2X_REG SPSR
00190 #define WCOL_REG SPSR
00191 #define SPIF_REG SPSR
00192
00193
00194 #define ICR1H0_REG ICR1H
00195 #define ICR1H1_REG ICR1H
00196 #define ICR1H2_REG ICR1H
00197 #define ICR1H3_REG ICR1H
00198 #define ICR1H4_REG ICR1H
00199 #define ICR1H5_REG ICR1H
00200 #define ICR1H6_REG ICR1H
00201 #define ICR1H7_REG ICR1H
00202
00203
00204 #define SP0_REG SPL
00205 #define SP1_REG SPL
00206 #define SP2_REG SPL
00207 #define SP3_REG SPL
00208 #define SP4_REG SPL
00209 #define SP5_REG SPL
00210 #define SP6_REG SPL
00211 #define SP7_REG SPL
00212
00213
00214 #define DDD0_REG DDRD
00215 #define DDD1_REG DDRD
00216 #define DDD2_REG DDRD
00217 #define DDD3_REG DDRD
00218 #define DDD4_REG DDRD
00219 #define DDD5_REG DDRD
00220 #define DDD6_REG DDRD
00221 #define DDD7_REG DDRD
00222
00223
00224 #define TWPS0_REG TWSR
00225 #define TWPS1_REG TWSR
00226 #define TWS3_REG TWSR
00227 #define TWS4_REG TWSR
00228 #define TWS5_REG TWSR
00229 #define TWS6_REG TWSR
00230 #define TWS7_REG TWSR
00231
00232
00233 #define TCNT1L0_REG TCNT1L
00234 #define TCNT1L1_REG TCNT1L
00235 #define TCNT1L2_REG TCNT1L
00236 #define TCNT1L3_REG TCNT1L
00237 #define TCNT1L4_REG TCNT1L
00238 #define TCNT1L5_REG TCNT1L
00239 #define TCNT1L6_REG TCNT1L
00240 #define TCNT1L7_REG TCNT1L
00241
00242
00243 #define PORTG0_REG PORTG
00244 #define PORTG1_REG PORTG
00245 #define PORTG2_REG PORTG
00246 #define PORTG3_REG PORTG
00247 #define PORTG4_REG PORTG
00248
00249
00250 #define UCPOL0_REG UCSR0C
00251 #define UCSZ00_REG UCSR0C
00252 #define UCSZ01_REG UCSR0C
00253 #define USBS0_REG UCSR0C
00254 #define UPM00_REG UCSR0C
00255 #define UPM01_REG UCSR0C
00256 #define UMSEL0_REG UCSR0C
00257
00258
00259 #define TXB80_REG UCSR0B
00260 #define RXB80_REG UCSR0B
00261 #define UCSZ02_REG UCSR0B
00262 #define TXEN0_REG UCSR0B
00263 #define RXEN0_REG UCSR0B
00264 #define UDRIE0_REG UCSR0B
00265 #define TXCIE0_REG UCSR0B
00266 #define RXCIE0_REG UCSR0B
00267
00268
00269 #define PORTB0_REG PORTB
00270 #define PORTB1_REG PORTB
00271 #define PORTB2_REG PORTB
00272 #define PORTB3_REG PORTB
00273 #define PORTB4_REG PORTB
00274 #define PORTB5_REG PORTB
00275 #define PORTB6_REG PORTB
00276 #define PORTB7_REG PORTB
00277
00278
00279 #define PORTC0_REG PORTC
00280 #define PORTC1_REG PORTC
00281 #define PORTC2_REG PORTC
00282 #define PORTC3_REG PORTC
00283 #define PORTC4_REG PORTC
00284 #define PORTC5_REG PORTC
00285 #define PORTC6_REG PORTC
00286 #define PORTC7_REG PORTC
00287
00288
00289 #define PORTA0_REG PORTA
00290 #define PORTA1_REG PORTA
00291 #define PORTA2_REG PORTA
00292 #define PORTA3_REG PORTA
00293 #define PORTA4_REG PORTA
00294 #define PORTA5_REG PORTA
00295 #define PORTA6_REG PORTA
00296 #define PORTA7_REG PORTA
00297
00298
00299 #define UDR10_REG UDR1
00300 #define UDR11_REG UDR1
00301 #define UDR12_REG UDR1
00302 #define UDR13_REG UDR1
00303 #define UDR14_REG UDR1
00304 #define UDR15_REG UDR1
00305 #define UDR16_REG UDR1
00306 #define UDR17_REG UDR1
00307
00308
00309 #define UDR00_REG UDR0
00310 #define UDR01_REG UDR0
00311 #define UDR02_REG UDR0
00312 #define UDR03_REG UDR0
00313 #define UDR04_REG UDR0
00314 #define UDR05_REG UDR0
00315 #define UDR06_REG UDR0
00316 #define UDR07_REG UDR0
00317
00318
00319 #define ISC40_REG EICRB
00320 #define ISC41_REG EICRB
00321 #define ISC50_REG EICRB
00322 #define ISC51_REG EICRB
00323 #define ISC60_REG EICRB
00324 #define ISC61_REG EICRB
00325 #define ISC70_REG EICRB
00326 #define ISC71_REG EICRB
00327
00328
00329 #define ISC00_REG EICRA
00330 #define ISC01_REG EICRA
00331 #define ISC10_REG EICRA
00332 #define ISC11_REG EICRA
00333 #define ISC20_REG EICRA
00334 #define ISC21_REG EICRA
00335 #define ISC30_REG EICRA
00336 #define ISC31_REG EICRA
00337
00338
00339 #define TCR0UB_REG ASSR
00340 #define OCR0UB_REG ASSR
00341 #define TCN0UB_REG ASSR
00342 #define AS0_REG ASSR
00343
00344
00345 #define C_REG SREG
00346 #define Z_REG SREG
00347 #define N_REG SREG
00348 #define V_REG SREG
00349 #define S_REG SREG
00350 #define H_REG SREG
00351 #define T_REG SREG
00352 #define I_REG SREG
00353
00354
00355
00356
00357
00358
00359
00360
00361
00362
00363
00364
00365 #define DDC0_REG DDRC
00366 #define DDC1_REG DDRC
00367 #define DDC2_REG DDRC
00368 #define DDC3_REG DDRC
00369 #define DDC4_REG DDRC
00370 #define DDC5_REG DDRC
00371 #define DDC6_REG DDRC
00372 #define DDC7_REG DDRC
00373
00374
00375 #define OCR3AL0_REG OCR3AL
00376 #define OCR3AL1_REG OCR3AL
00377 #define OCR3AL2_REG OCR3AL
00378 #define OCR3AL3_REG OCR3AL
00379 #define OCR3AL4_REG OCR3AL
00380 #define OCR3AL5_REG OCR3AL
00381 #define OCR3AL6_REG OCR3AL
00382 #define OCR3AL7_REG OCR3AL
00383
00384
00385 #define DDA0_REG DDRA
00386 #define DDA1_REG DDRA
00387 #define DDA2_REG DDRA
00388 #define DDA3_REG DDRA
00389 #define DDA4_REG DDRA
00390 #define DDA5_REG DDRA
00391 #define DDA6_REG DDRA
00392 #define DDA7_REG DDRA
00393
00394
00395 #define DDF0_REG DDRF
00396 #define DDF1_REG DDRF
00397 #define DDF2_REG DDRF
00398 #define DDF3_REG DDRF
00399 #define DDF4_REG DDRF
00400 #define DDF5_REG DDRF
00401 #define DDF6_REG DDRF
00402 #define DDF7_REG DDRF
00403
00404
00405 #define DDG0_REG DDRG
00406 #define DDG1_REG DDRG
00407 #define DDG2_REG DDRG
00408 #define DDG3_REG DDRG
00409 #define DDG4_REG DDRG
00410
00411
00412 #define OCR3AH0_REG OCR3AH
00413 #define OCR3AH1_REG OCR3AH
00414 #define OCR3AH2_REG OCR3AH
00415 #define OCR3AH3_REG OCR3AH
00416 #define OCR3AH4_REG OCR3AH
00417 #define OCR3AH5_REG OCR3AH
00418 #define OCR3AH6_REG OCR3AH
00419 #define OCR3AH7_REG OCR3AH
00420
00421
00422 #define CS10_REG TCCR1B
00423 #define CS11_REG TCCR1B
00424 #define CS12_REG TCCR1B
00425 #define WGM12_REG TCCR1B
00426 #define WGM13_REG TCCR1B
00427 #define ICES1_REG TCCR1B
00428 #define ICNC1_REG TCCR1B
00429
00430
00431 #define CAL0_REG OSCCAL
00432 #define CAL1_REG OSCCAL
00433 #define CAL2_REG OSCCAL
00434 #define CAL3_REG OSCCAL
00435 #define CAL4_REG OSCCAL
00436 #define CAL5_REG OSCCAL
00437 #define CAL6_REG OSCCAL
00438 #define CAL7_REG OSCCAL
00439
00440
00441 #define ACME_REG SFIOR
00442 #define PSR321_REG SFIOR
00443 #define PSR0_REG SFIOR
00444 #define PUD_REG SFIOR
00445 #define TSM_REG SFIOR
00446
00447
00448 #define TCNT2_0_REG TCNT2
00449 #define TCNT2_1_REG TCNT2
00450 #define TCNT2_2_REG TCNT2
00451 #define TCNT2_3_REG TCNT2
00452 #define TCNT2_4_REG TCNT2
00453 #define TCNT2_5_REG TCNT2
00454 #define TCNT2_6_REG TCNT2
00455 #define TCNT2_7_REG TCNT2
00456
00457
00458
00459
00460
00461
00462
00463
00464 #define TWGCE_REG TWAR
00465 #define TWA0_REG TWAR
00466 #define TWA1_REG TWAR
00467 #define TWA2_REG TWAR
00468 #define TWA3_REG TWAR
00469 #define TWA4_REG TWAR
00470 #define TWA5_REG TWAR
00471 #define TWA6_REG TWAR
00472
00473
00474 #define TOV0_REG TIFR
00475 #define OCF0_REG TIFR
00476 #define TOV1_REG TIFR
00477 #define OCF1B_REG TIFR
00478 #define OCF1A_REG TIFR
00479 #define ICF1_REG TIFR
00480 #define TOV2_REG TIFR
00481 #define OCF2_REG TIFR
00482
00483
00484 #define TCNT0_0_REG TCNT0
00485 #define TCNT0_1_REG TCNT0
00486 #define TCNT0_2_REG TCNT0
00487 #define TCNT0_3_REG TCNT0
00488 #define TCNT0_4_REG TCNT0
00489 #define TCNT0_5_REG TCNT0
00490 #define TCNT0_6_REG TCNT0
00491 #define TCNT0_7_REG TCNT0
00492
00493
00494 #define OCF1C_REG ETIFR
00495 #define OCF3C_REG ETIFR
00496 #define TOV3_REG ETIFR
00497 #define OCF3B_REG ETIFR
00498 #define OCF3A_REG ETIFR
00499 #define ICF3_REG ETIFR
00500
00501
00502 #define SPR0_REG SPCR
00503 #define SPR1_REG SPCR
00504 #define CPHA_REG SPCR
00505 #define CPOL_REG SPCR
00506 #define MSTR_REG SPCR
00507 #define DORD_REG SPCR
00508 #define SPE_REG SPCR
00509 #define SPIE_REG SPCR
00510
00511
00512 #define XDIV0_REG XDIV
00513 #define XDIV1_REG XDIV
00514 #define XDIV2_REG XDIV
00515 #define XDIV3_REG XDIV
00516 #define XDIV4_REG XDIV
00517 #define XDIV5_REG XDIV
00518 #define XDIV6_REG XDIV
00519 #define XDIVEN_REG XDIV
00520
00521
00522 #define OCR3CH0_REG OCR3CH
00523 #define OCR3CH1_REG OCR3CH
00524 #define OCR3CH2_REG OCR3CH
00525 #define OCR3CH3_REG OCR3CH
00526 #define OCR3CH4_REG OCR3CH
00527 #define OCR3CH5_REG OCR3CH
00528 #define OCR3CH6_REG OCR3CH
00529 #define OCR3CH7_REG OCR3CH
00530
00531
00532 #define OCIE1C_REG ETIMSK
00533 #define OCIE3C_REG ETIMSK
00534 #define TOIE3_REG ETIMSK
00535 #define OCIE3B_REG ETIMSK
00536 #define OCIE3A_REG ETIMSK
00537 #define TICIE3_REG ETIMSK
00538
00539
00540 #define OCR3CL0_REG OCR3CL
00541 #define OCR3CL1_REG OCR3CL
00542 #define OCR3CL2_REG OCR3CL
00543 #define OCR3CL3_REG OCR3CL
00544 #define OCR3CL4_REG OCR3CL
00545 #define OCR3CL5_REG OCR3CL
00546 #define OCR3CL6_REG OCR3CL
00547 #define OCR3CL7_REG OCR3CL
00548
00549
00550 #define TWBR0_REG TWBR
00551 #define TWBR1_REG TWBR
00552 #define TWBR2_REG TWBR
00553 #define TWBR3_REG TWBR
00554 #define TWBR4_REG TWBR
00555 #define TWBR5_REG TWBR
00556 #define TWBR6_REG TWBR
00557 #define TWBR7_REG TWBR
00558
00559
00560 #define SP8_REG SPH
00561 #define SP9_REG SPH
00562 #define SP10_REG SPH
00563 #define SP11_REG SPH
00564 #define SP12_REG SPH
00565 #define SP13_REG SPH
00566 #define SP14_REG SPH
00567 #define SP15_REG SPH
00568
00569
00570 #define FOC3C_REG TCCR3C
00571 #define FOC3B_REG TCCR3C
00572 #define FOC3A_REG TCCR3C
00573
00574
00575 #define CS30_REG TCCR3B
00576 #define CS31_REG TCCR3B
00577 #define CS32_REG TCCR3B
00578 #define WGM32_REG TCCR3B
00579 #define WGM33_REG TCCR3B
00580 #define ICES3_REG TCCR3B
00581 #define ICNC3_REG TCCR3B
00582
00583
00584 #define WGM30_REG TCCR3A
00585 #define WGM31_REG TCCR3A
00586 #define COM3C0_REG TCCR3A
00587 #define COM3C1_REG TCCR3A
00588 #define COM3B0_REG TCCR3A
00589 #define COM3B1_REG TCCR3A
00590 #define COM3A0_REG TCCR3A
00591 #define COM3A1_REG TCCR3A
00592
00593
00594 #define OCR1BL0_REG OCR1BL
00595 #define OCR1BL1_REG OCR1BL
00596 #define OCR1BL2_REG OCR1BL
00597 #define OCR1BL3_REG OCR1BL
00598 #define OCR1BL4_REG OCR1BL
00599 #define OCR1BL5_REG OCR1BL
00600 #define OCR1BL6_REG OCR1BL
00601 #define OCR1BL7_REG OCR1BL
00602
00603
00604 #define TCNT3H0_REG TCNT3H
00605 #define TCNT3H1_REG TCNT3H
00606 #define TCNT3H2_REG TCNT3H
00607 #define TCNT3H3_REG TCNT3H
00608 #define TCNT3H4_REG TCNT3H
00609 #define TCNT3H5_REG TCNT3H
00610 #define TCNT3H6_REG TCNT3H
00611 #define TCNT3H7_REG TCNT3H
00612
00613
00614 #define OCR1BH0_REG OCR1BH
00615 #define OCR1BH1_REG OCR1BH
00616 #define OCR1BH2_REG OCR1BH
00617 #define OCR1BH3_REG OCR1BH
00618 #define OCR1BH4_REG OCR1BH
00619 #define OCR1BH5_REG OCR1BH
00620 #define OCR1BH6_REG OCR1BH
00621 #define OCR1BH7_REG OCR1BH
00622
00623
00624 #define TCN3L0_REG TCNT3L
00625 #define TCN3L1_REG TCNT3L
00626 #define TCN3L2_REG TCNT3L
00627 #define TCN3L3_REG TCNT3L
00628 #define TCN3L4_REG TCNT3L
00629 #define TCN3L5_REG TCNT3L
00630 #define TCN3L6_REG TCNT3L
00631 #define TCN3L7_REG TCNT3L
00632
00633
00634 #define ICR1L0_REG ICR1L
00635 #define ICR1L1_REG ICR1L
00636 #define ICR1L2_REG ICR1L
00637 #define ICR1L3_REG ICR1L
00638 #define ICR1L4_REG ICR1L
00639 #define ICR1L5_REG ICR1L
00640 #define ICR1L6_REG ICR1L
00641 #define ICR1L7_REG ICR1L
00642
00643
00644 #define EERE_REG EECR
00645 #define EEWE_REG EECR
00646 #define EEMWE_REG EECR
00647 #define EERIE_REG EECR
00648
00649
00650 #define TWIE_REG TWCR
00651 #define TWEN_REG TWCR
00652 #define TWWC_REG TWCR
00653 #define TWSTO_REG TWCR
00654 #define TWSTA_REG TWCR
00655 #define TWEA_REG TWCR
00656 #define TWINT_REG TWCR
00657
00658
00659 #define PORF_REG MCUCSR
00660 #define EXTRF_REG MCUCSR
00661 #define BORF_REG MCUCSR
00662 #define WDRF_REG MCUCSR
00663 #define JTRF_REG MCUCSR
00664 #define JTD_REG MCUCSR
00665
00666
00667 #define MPCM0_REG UCSR0A
00668 #define U2X0_REG UCSR0A
00669 #define UPE0_REG UCSR0A
00670 #define DOR0_REG UCSR0A
00671 #define FE0_REG UCSR0A
00672 #define UDRE0_REG UCSR0A
00673 #define TXC0_REG UCSR0A
00674 #define RXC0_REG UCSR0A
00675
00676
00677
00678
00679
00680
00681
00682
00683
00684
00685
00686
00687
00688
00689
00690
00691
00692
00693 #define EEAR8_REG EEARH
00694 #define EEAR9_REG EEARH
00695 #define EEAR10_REG EEARH
00696
00697
00698 #define EEARL0_REG EEARL
00699 #define EEARL1_REG EEARL
00700 #define EEARL2_REG EEARL
00701 #define EEARL3_REG EEARL
00702 #define EEARL4_REG EEARL
00703 #define EEARL5_REG EEARL
00704 #define EEARL6_REG EEARL
00705 #define EEARL7_REG EEARL
00706
00707
00708 #define IVCE_REG MCUCR
00709 #define IVSEL_REG MCUCR
00710 #define SM2_REG MCUCR
00711 #define SM0_REG MCUCR
00712 #define SM1_REG MCUCR
00713 #define SE_REG MCUCR
00714 #define SRW10_REG MCUCR
00715 #define SRE_REG MCUCR
00716
00717
00718 #define OCR1CL0_REG OCR1CL
00719 #define OCR1CL1_REG OCR1CL
00720 #define OCR1CL2_REG OCR1CL
00721 #define OCR1CL3_REG OCR1CL
00722 #define OCR1CL4_REG OCR1CL
00723 #define OCR1CL5_REG OCR1CL
00724 #define OCR1CL6_REG OCR1CL
00725 #define OCR1CL7_REG OCR1CL
00726
00727
00728 #define OCR1CH0_REG OCR1CH
00729 #define OCR1CH1_REG OCR1CH
00730 #define OCR1CH2_REG OCR1CH
00731 #define OCR1CH3_REG OCR1CH
00732 #define OCR1CH4_REG OCR1CH
00733 #define OCR1CH5_REG OCR1CH
00734 #define OCR1CH6_REG OCR1CH
00735 #define OCR1CH7_REG OCR1CH
00736
00737
00738 #define OCDR0_REG OCDR
00739 #define OCDR1_REG OCDR
00740 #define OCDR2_REG OCDR
00741 #define OCDR3_REG OCDR
00742 #define OCDR4_REG OCDR
00743 #define OCDR5_REG OCDR
00744 #define OCDR6_REG OCDR
00745 #define OCDR7_REG OCDR
00746
00747
00748 #define INTF0_REG EIFR
00749 #define INTF1_REG EIFR
00750 #define INTF2_REG EIFR
00751 #define INTF3_REG EIFR
00752 #define INTF4_REG EIFR
00753 #define INTF5_REG EIFR
00754 #define INTF6_REG EIFR
00755 #define INTF7_REG EIFR
00756
00757
00758 #define TXB81_REG UCSR1B
00759 #define RXB81_REG UCSR1B
00760 #define UCSZ12_REG UCSR1B
00761 #define TXEN1_REG UCSR1B
00762 #define RXEN1_REG UCSR1B
00763 #define UDRIE1_REG UCSR1B
00764 #define TXCIE1_REG UCSR1B
00765 #define RXCIE1_REG UCSR1B
00766
00767
00768 #define UCPOL1_REG UCSR1C
00769 #define UCSZ10_REG UCSR1C
00770 #define UCSZ11_REG UCSR1C
00771 #define USBS1_REG UCSR1C
00772 #define UPM10_REG UCSR1C
00773 #define UPM11_REG UCSR1C
00774 #define UMSEL1_REG UCSR1C
00775
00776
00777 #define MPCM1_REG UCSR1A
00778 #define U2X1_REG UCSR1A
00779 #define UPE1_REG UCSR1A
00780 #define DOR1_REG UCSR1A
00781 #define FE1_REG UCSR1A
00782 #define UDRE1_REG UCSR1A
00783 #define TXC1_REG UCSR1A
00784 #define RXC1_REG UCSR1A
00785
00786
00787 #define CS00_REG TCCR0
00788 #define CS01_REG TCCR0
00789 #define CS02_REG TCCR0
00790 #define WGM01_REG TCCR0
00791 #define COM00_REG TCCR0
00792 #define COM01_REG TCCR0
00793 #define WGM00_REG TCCR0
00794 #define FOC0_REG TCCR0
00795
00796
00797 #define CS20_REG TCCR2
00798 #define CS21_REG TCCR2
00799 #define CS22_REG TCCR2
00800 #define WGM21_REG TCCR2
00801 #define COM20_REG TCCR2
00802 #define COM21_REG TCCR2
00803 #define WGM20_REG TCCR2
00804 #define FOC2_REG TCCR2
00805
00806
00807 #define DDB0_REG DDRB
00808 #define DDB1_REG DDRB
00809 #define DDB2_REG DDRB
00810 #define DDB3_REG DDRB
00811 #define DDB4_REG DDRB
00812 #define DDB5_REG DDRB
00813 #define DDB6_REG DDRB
00814 #define DDB7_REG DDRB
00815
00816
00817 #define TWD0_REG TWDR
00818 #define TWD1_REG TWDR
00819 #define TWD2_REG TWDR
00820 #define TWD3_REG TWDR
00821 #define TWD4_REG TWDR
00822 #define TWD5_REG TWDR
00823 #define TWD6_REG TWDR
00824 #define TWD7_REG TWDR
00825
00826
00827 #define TOIE0_REG TIMSK
00828 #define OCIE0_REG TIMSK
00829 #define TOIE1_REG TIMSK
00830 #define OCIE1B_REG TIMSK
00831 #define OCIE1A_REG TIMSK
00832 #define TICIE1_REG TIMSK
00833 #define TOIE2_REG TIMSK
00834 #define OCIE2_REG TIMSK
00835
00836
00837 #define INT0_REG EIMSK
00838 #define INT1_REG EIMSK
00839 #define INT2_REG EIMSK
00840 #define INT3_REG EIMSK
00841 #define INT4_REG EIMSK
00842 #define INT5_REG EIMSK
00843 #define INT6_REG EIMSK
00844 #define INT7_REG EIMSK
00845
00846
00847 #define ADTS0_REG ADCSRB
00848 #define ADTS1_REG ADCSRB
00849 #define ADTS2_REG ADCSRB
00850
00851
00852 #define WGM10_REG TCCR1A
00853 #define WGM11_REG TCCR1A
00854 #define COM1C0_REG TCCR1A
00855 #define COM1C1_REG TCCR1A
00856 #define COM1B0_REG TCCR1A
00857 #define COM1B1_REG TCCR1A
00858 #define COM1A0_REG TCCR1A
00859 #define COM1A1_REG TCCR1A
00860
00861
00862 #define ACIS0_REG ACSR
00863 #define ACIS1_REG ACSR
00864 #define ACIC_REG ACSR
00865 #define ACIE_REG ACSR
00866 #define ACI_REG ACSR
00867 #define ACO_REG ACSR
00868 #define ACBG_REG ACSR
00869 #define ACD_REG ACSR
00870
00871
00872 #define PORTF0_REG PORTF
00873 #define PORTF1_REG PORTF
00874 #define PORTF2_REG PORTF
00875 #define PORTF3_REG PORTF
00876 #define PORTF4_REG PORTF
00877 #define PORTF5_REG PORTF
00878 #define PORTF6_REG PORTF
00879 #define PORTF7_REG PORTF
00880
00881
00882 #define FOC1C_REG TCCR1C
00883 #define FOC1B_REG TCCR1C
00884 #define FOC1A_REG TCCR1C
00885
00886
00887 #define ICR3H0_REG ICR3H
00888 #define ICR3H1_REG ICR3H
00889 #define ICR3H2_REG ICR3H
00890 #define ICR3H3_REG ICR3H
00891 #define ICR3H4_REG ICR3H
00892 #define ICR3H5_REG ICR3H
00893 #define ICR3H6_REG ICR3H
00894 #define ICR3H7_REG ICR3H
00895
00896
00897 #define DDE0_REG DDRE
00898 #define DDE1_REG DDRE
00899 #define DDE2_REG DDRE
00900 #define DDE3_REG DDRE
00901 #define DDE4_REG DDRE
00902 #define DDE5_REG DDRE
00903 #define DDE6_REG DDRE
00904 #define DDE7_REG DDRE
00905
00906
00907 #define PORTD0_REG PORTD
00908 #define PORTD1_REG PORTD
00909 #define PORTD2_REG PORTD
00910 #define PORTD3_REG PORTD
00911 #define PORTD4_REG PORTD
00912 #define PORTD5_REG PORTD
00913 #define PORTD6_REG PORTD
00914 #define PORTD7_REG PORTD
00915
00916
00917 #define ICR3L0_REG ICR3L
00918 #define ICR3L1_REG ICR3L
00919 #define ICR3L2_REG ICR3L
00920 #define ICR3L3_REG ICR3L
00921 #define ICR3L4_REG ICR3L
00922 #define ICR3L5_REG ICR3L
00923 #define ICR3L6_REG ICR3L
00924 #define ICR3L7_REG ICR3L
00925
00926
00927 #define PORTE0_REG PORTE
00928 #define PORTE1_REG PORTE
00929 #define PORTE2_REG PORTE
00930 #define PORTE3_REG PORTE
00931 #define PORTE4_REG PORTE
00932 #define PORTE5_REG PORTE
00933 #define PORTE6_REG PORTE
00934 #define PORTE7_REG PORTE
00935
00936
00937 #define SPMEN_REG SPMCSR
00938 #define PGERS_REG SPMCSR
00939 #define PGWRT_REG SPMCSR
00940 #define BLBSET_REG SPMCSR
00941 #define RWWSRE_REG SPMCSR
00942 #define RWWSB_REG SPMCSR
00943 #define SPMIE_REG SPMCSR
00944
00945
00946 #define TCNT1H0_REG TCNT1H
00947 #define TCNT1H1_REG TCNT1H
00948 #define TCNT1H2_REG TCNT1H
00949 #define TCNT1H3_REG TCNT1H
00950 #define TCNT1H4_REG TCNT1H
00951 #define TCNT1H5_REG TCNT1H
00952 #define TCNT1H6_REG TCNT1H
00953 #define TCNT1H7_REG TCNT1H
00954
00955
00956 #define ADCL0_REG ADCL
00957 #define ADCL1_REG ADCL
00958 #define ADCL2_REG ADCL
00959 #define ADCL3_REG ADCL
00960 #define ADCL4_REG ADCL
00961 #define ADCL5_REG ADCL
00962 #define ADCL6_REG ADCL
00963 #define ADCL7_REG ADCL
00964
00965
00966 #define ADCH0_REG ADCH
00967 #define ADCH1_REG ADCH
00968 #define ADCH2_REG ADCH
00969 #define ADCH3_REG ADCH
00970 #define ADCH4_REG ADCH
00971 #define ADCH5_REG ADCH
00972 #define ADCH6_REG ADCH
00973 #define ADCH7_REG ADCH
00974
00975
00976 #define OCR3BL0_REG OCR3BL
00977 #define OCR3BL1_REG OCR3BL
00978 #define OCR3BL2_REG OCR3BL
00979 #define OCR3BL3_REG OCR3BL
00980 #define OCR3BL4_REG OCR3BL
00981 #define OCR3BL5_REG OCR3BL
00982 #define OCR3BL6_REG OCR3BL
00983 #define OCR3BL7_REG OCR3BL
00984
00985
00986 #define OCR3BH0_REG OCR3BH
00987 #define OCR3BH1_REG OCR3BH
00988 #define OCR3BH2_REG OCR3BH
00989 #define OCR3BH3_REG OCR3BH
00990 #define OCR3BH4_REG OCR3BH
00991 #define OCR3BH5_REG OCR3BH
00992 #define OCR3BH6_REG OCR3BH
00993 #define OCR3BH7_REG OCR3BH
00994
00995
00996 #define ADPS0_REG ADCSRA
00997 #define ADPS1_REG ADCSRA
00998 #define ADPS2_REG ADCSRA
00999 #define ADIE_REG ADCSRA
01000 #define ADIF_REG ADCSRA
01001 #define ADATE_REG ADCSRA
01002 #define ADSC_REG ADCSRA
01003 #define ADEN_REG ADCSRA
01004
01005
01006 #define XMM0_REG XMCRB
01007 #define XMM1_REG XMCRB
01008 #define XMM2_REG XMCRB
01009 #define XMBK_REG XMCRB
01010
01011
01012 #define SRW11_REG XMCRA
01013 #define SRW00_REG XMCRA
01014 #define SRW01_REG XMCRA
01015 #define SRL0_REG XMCRA
01016 #define SRL1_REG XMCRA
01017 #define SRL2_REG XMCRA
01018
01019
01020 #define PINC0_REG PINC
01021 #define PINC1_REG PINC
01022 #define PINC2_REG PINC
01023 #define PINC3_REG PINC
01024 #define PINC4_REG PINC
01025 #define PINC5_REG PINC
01026 #define PINC6_REG PINC
01027 #define PINC7_REG PINC
01028
01029
01030 #define PINB0_REG PINB
01031 #define PINB1_REG PINB
01032 #define PINB2_REG PINB
01033 #define PINB3_REG PINB
01034 #define PINB4_REG PINB
01035 #define PINB5_REG PINB
01036 #define PINB6_REG PINB
01037 #define PINB7_REG PINB
01038
01039
01040 #define PINA0_REG PINA
01041 #define PINA1_REG PINA
01042 #define PINA2_REG PINA
01043 #define PINA3_REG PINA
01044 #define PINA4_REG PINA
01045 #define PINA5_REG PINA
01046 #define PINA6_REG PINA
01047 #define PINA7_REG PINA
01048
01049
01050 #define PING0_REG PING
01051 #define PING1_REG PING
01052 #define PING2_REG PING
01053 #define PING3_REG PING
01054 #define PING4_REG PING
01055
01056
01057 #define PINF0_REG PINF
01058 #define PINF1_REG PINF
01059 #define PINF2_REG PINF
01060 #define PINF3_REG PINF
01061 #define PINF4_REG PINF
01062 #define PINF5_REG PINF
01063 #define PINF6_REG PINF
01064 #define PINF7_REG PINF
01065
01066
01067 #define PINE0_REG PINE
01068 #define PINE1_REG PINE
01069 #define PINE2_REG PINE
01070 #define PINE3_REG PINE
01071 #define PINE4_REG PINE
01072 #define PINE5_REG PINE
01073 #define PINE6_REG PINE
01074 #define PINE7_REG PINE
01075
01076
01077 #define PIND0_REG PIND
01078 #define PIND1_REG PIND
01079 #define PIND2_REG PIND
01080 #define PIND3_REG PIND
01081 #define PIND4_REG PIND
01082 #define PIND5_REG PIND
01083 #define PIND6_REG PIND
01084 #define PIND7_REG PIND
01085
01086
01087 #define OCR1AH0_REG OCR1AH
01088 #define OCR1AH1_REG OCR1AH
01089 #define OCR1AH2_REG OCR1AH
01090 #define OCR1AH3_REG OCR1AH
01091 #define OCR1AH4_REG OCR1AH
01092 #define OCR1AH5_REG OCR1AH
01093 #define OCR1AH6_REG OCR1AH
01094 #define OCR1AH7_REG OCR1AH
01095
01096
01097 #define OCR1AL0_REG OCR1AL
01098 #define OCR1AL1_REG OCR1AL
01099 #define OCR1AL2_REG OCR1AL
01100 #define OCR1AL3_REG OCR1AL
01101 #define OCR1AL4_REG OCR1AL
01102 #define OCR1AL5_REG OCR1AL
01103 #define OCR1AL6_REG OCR1AL
01104 #define OCR1AL7_REG OCR1AL
01105
01106
01107 #define OCR0_0_REG OCR0
01108 #define OCR0_1_REG OCR0
01109 #define OCR0_2_REG OCR0
01110 #define OCR0_3_REG OCR0
01111 #define OCR0_4_REG OCR0
01112 #define OCR0_5_REG OCR0
01113 #define OCR0_6_REG OCR0
01114 #define OCR0_7_REG OCR0
01115
01116
01117 #define OCR2_0_REG OCR2
01118 #define OCR2_1_REG OCR2
01119 #define OCR2_2_REG OCR2
01120 #define OCR2_3_REG OCR2
01121 #define OCR2_4_REG OCR2
01122 #define OCR2_5_REG OCR2
01123 #define OCR2_6_REG OCR2
01124 #define OCR2_7_REG OCR2
01125
01126
01127 #define AD0_PORT PORTA
01128 #define AD0_BIT 0
01129
01130 #define AD1_PORT PORTA
01131 #define AD1_BIT 1
01132
01133 #define AD2_PORT PORTA
01134 #define AD2_BIT 2
01135
01136 #define AD3_PORT PORTA
01137 #define AD3_BIT 3
01138
01139 #define AD4_PORT PORTA
01140 #define AD4_BIT 4
01141
01142 #define AD5_PORT PORTA
01143 #define AD5_BIT 5
01144
01145 #define AD6_PORT PORTA
01146 #define AD6_BIT 6
01147
01148 #define AD7_PORT PORTA
01149 #define AD7_BIT 7
01150
01151 #define SS_PORT PORTB
01152 #define SS_BIT 0
01153
01154 #define SCK_PORT PORTB
01155 #define SCK_BIT 1
01156
01157 #define MOSI_PORT PORTB
01158 #define MOSI_BIT 2
01159
01160 #define MISO_PORT PORTB
01161 #define MISO_BIT 3
01162
01163 #define OC0_PORT PORTB
01164 #define OC0_BIT 4
01165 #define PWM0_PORT PORTB
01166 #define PWM0_BIT 4
01167
01168 #define OC1A_PORT PORTB
01169 #define OC1A_BIT 5
01170 #define PWM1A_PORT PORTB
01171 #define PWM1A_BIT 5
01172
01173 #define OC1B_PORT PORTB
01174 #define OC1B_BIT 6
01175 #define PWM1B_PORT PORTB
01176 #define PWM1B_BIT 6
01177
01178 #define OC2_PORT PORTB
01179 #define OC2_BIT 7
01180 #define PWM2_PORT PORTB
01181 #define PWM2_BIT 7
01182 #define OC1C_PORT PORTB
01183 #define OC1C_BIT 7
01184
01185 #define A8_PORT PORTC
01186 #define A8_BIT 0
01187
01188 #define A9_PORT PORTC
01189 #define A9_BIT 1
01190
01191 #define A10_PORT PORTC
01192 #define A10_BIT 2
01193
01194 #define A11_PORT PORTC
01195 #define A11_BIT 3
01196
01197 #define A12_PORT PORTC
01198 #define A12_BIT 4
01199
01200 #define A13_PORT PORTC
01201 #define A13_BIT 5
01202
01203 #define A14_PORT PORTC
01204 #define A14_BIT 6
01205
01206 #define A15_PORT PORTC
01207 #define A15_BIT 7
01208
01209 #define SCL_PORT PORTD
01210 #define SCL_BIT 0
01211 #define INT0_PORT PORTD
01212 #define INT0_BIT 0
01213
01214 #define SDA_PORT PORTD
01215 #define SDA_BIT 1
01216 #define INT1_PORT PORTD
01217 #define INT1_BIT 1
01218
01219 #define RXD1_PORT PORTD
01220 #define RXD1_BIT 2
01221 #define INT2_PORT PORTD
01222 #define INT2_BIT 2
01223
01224 #define TXD1_PORT PORTD
01225 #define TXD1_BIT 3
01226 #define INT3_PORT PORTD
01227 #define INT3_BIT 3
01228
01229 #define IC1_PORT PORTD
01230 #define IC1_BIT 4
01231
01232 #define XCK1_PORT PORTD
01233 #define XCK1_BIT 5
01234
01235 #define T1_PORT PORTD
01236 #define T1_BIT 6
01237
01238 #define T2_PORT PORTD
01239 #define T2_BIT 7
01240
01241 #define RXD0_PORT PORTE
01242 #define RXD0_BIT 0
01243 #define PDI_PORT PORTE
01244 #define PDI_BIT 0
01245
01246 #define TXD0_PORT PORTE
01247 #define TXD0_BIT 1
01248 #define PDO_PORT PORTE
01249 #define PDO_BIT 1
01250
01251 #define XCK0_PORT PORTE
01252 #define XCK0_BIT 2
01253 #define AIN0_PORT PORTE
01254 #define AIN0_BIT 2
01255
01256 #define OC3A_PORT PORTE
01257 #define OC3A_BIT 3
01258 #define AIN1_PORT PORTE
01259 #define AIN1_BIT 3
01260
01261 #define OC3B_PORT PORTE
01262 #define OC3B_BIT 4
01263 #define INT4_PORT PORTE
01264 #define INT4_BIT 4
01265
01266 #define OC3C_PORT PORTE
01267 #define OC3C_BIT 5
01268 #define INT5_PORT PORTE
01269 #define INT5_BIT 5
01270
01271 #define T3_PORT PORTE
01272 #define T3_BIT 6
01273 #define INT6_PORT PORTE
01274 #define INT6_BIT 6
01275
01276 #define IC3_PORT PORTE
01277 #define IC3_BIT 7
01278 #define INT7_PORT PORTE
01279 #define INT7_BIT 7
01280
01281 #define ADC0_PORT PORTF
01282 #define ADC0_BIT 0
01283
01284 #define ADC1_PORT PORTF
01285 #define ADC1_BIT 1
01286
01287 #define ADC2_PORT PORTF
01288 #define ADC2_BIT 2
01289
01290 #define ADC3_PORT PORTF
01291 #define ADC3_BIT 3
01292
01293 #define ADC4_PORT PORTF
01294 #define ADC4_BIT 4
01295 #define TCK_PORT PORTF
01296 #define TCK_BIT 4
01297
01298 #define ADC5_PORT PORTF
01299 #define ADC5_BIT 5
01300 #define TMS_PORT PORTF
01301 #define TMS_BIT 5
01302
01303 #define ADC6_PORT PORTF
01304 #define ADC6_BIT 6
01305 #define TD0_PORT PORTF
01306 #define TD0_BIT 6
01307
01308 #define ADC7_PORT PORTF
01309 #define ADC7_BIT 7
01310 #define TDI_PORT PORTF
01311 #define TDI_BIT 7
01312
01313 #define WR_PORT PORTG
01314 #define WR_BIT 0
01315
01316 #define RD_PORT PORTG
01317 #define RD_BIT 1
01318
01319 #define ALE_PORT PORTG
01320 #define ALE_BIT 2
01321
01322 #define TOSC2_PORT PORTG
01323 #define TOSC2_BIT 3
01324
01325 #define TOSC1_PORT PORTG
01326 #define TOSC1_BIT 4
01327
01328