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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define WDP0_REG WDTCR
00119 #define WDP1_REG WDTCR
00120 #define WDP2_REG WDTCR
00121 #define WDE_REG WDTCR
00122 #define WDCE_REG WDTCR
00123
00124
00125 #define MUX0_REG ADMUX
00126 #define MUX1_REG ADMUX
00127 #define MUX2_REG ADMUX
00128 #define MUX3_REG ADMUX
00129 #define MUX4_REG ADMUX
00130 #define ADLAR_REG ADMUX
00131 #define REFS0_REG ADMUX
00132 #define REFS1_REG ADMUX
00133
00134
00135 #define EEDR0_REG EEDR
00136 #define EEDR1_REG EEDR
00137 #define EEDR2_REG EEDR
00138 #define EEDR3_REG EEDR
00139 #define EEDR4_REG EEDR
00140 #define EEDR5_REG EEDR
00141 #define EEDR6_REG EEDR
00142 #define EEDR7_REG EEDR
00143
00144
00145 #define OCR2A0_REG OCR2A
00146 #define OCR2A1_REG OCR2A
00147 #define OCR2A2_REG OCR2A
00148 #define OCR2A3_REG OCR2A
00149 #define OCR2A4_REG OCR2A
00150 #define OCR2A5_REG OCR2A
00151 #define OCR2A6_REG OCR2A
00152 #define OCR2A7_REG OCR2A
00153
00154
00155 #define SPDR0_REG SPDR
00156 #define SPDR1_REG SPDR
00157 #define SPDR2_REG SPDR
00158 #define SPDR3_REG SPDR
00159 #define SPDR4_REG SPDR
00160 #define SPDR5_REG SPDR
00161 #define SPDR6_REG SPDR
00162 #define SPDR7_REG SPDR
00163
00164
00165 #define SPI2X_REG SPSR
00166 #define WCOL_REG SPSR
00167 #define SPIF_REG SPSR
00168
00169
00170 #define SP8_REG SPH
00171 #define SP9_REG SPH
00172 #define SP10_REG SPH
00173 #define SP11_REG SPH
00174 #define SP12_REG SPH
00175 #define SP13_REG SPH
00176 #define SP14_REG SPH
00177 #define SP15_REG SPH
00178
00179
00180 #define ICR1L0_REG ICR1L
00181 #define ICR1L1_REG ICR1L
00182 #define ICR1L2_REG ICR1L
00183 #define ICR1L3_REG ICR1L
00184 #define ICR1L4_REG ICR1L
00185 #define ICR1L5_REG ICR1L
00186 #define ICR1L6_REG ICR1L
00187 #define ICR1L7_REG ICR1L
00188
00189
00190 #define PRADC_REG PRR
00191 #define PRUSART0_REG PRR
00192 #define PRSPI_REG PRR
00193 #define PRTIM1_REG PRR
00194 #define PRLCD_REG PRR
00195
00196
00197 #define PORTJ0_REG PORTJ
00198 #define PORTJ1_REG PORTJ
00199 #define PORTJ2_REG PORTJ
00200 #define PORTJ3_REG PORTJ
00201 #define PORTJ4_REG PORTJ
00202 #define PORTJ5_REG PORTJ
00203 #define PORTJ6_REG PORTJ
00204
00205
00206 #define PORTH0_REG PORTH
00207 #define PORTH1_REG PORTH
00208 #define PORTH2_REG PORTH
00209 #define PORTH3_REG PORTH
00210 #define PORTH4_REG PORTH
00211 #define PORTH5_REG PORTH
00212 #define PORTH6_REG PORTH
00213 #define PORTH7_REG PORTH
00214
00215
00216 #define MPCM0_REG UCSR0A
00217 #define U2X0_REG UCSR0A
00218 #define UPE0_REG UCSR0A
00219 #define DOR0_REG UCSR0A
00220 #define FE0_REG UCSR0A
00221 #define UDRE0_REG UCSR0A
00222 #define TXC0_REG UCSR0A
00223 #define RXC0_REG UCSR0A
00224
00225
00226 #define PORTG0_REG PORTG
00227 #define PORTG1_REG PORTG
00228 #define PORTG2_REG PORTG
00229 #define PORTG3_REG PORTG
00230 #define PORTG4_REG PORTG
00231
00232
00233 #define UCPOL0_REG UCSR0C
00234 #define UCSZ00_REG UCSR0C
00235 #define UCSZ01_REG UCSR0C
00236 #define USBS0_REG UCSR0C
00237 #define UPM00_REG UCSR0C
00238 #define UPM01_REG UCSR0C
00239 #define UMSEL0_REG UCSR0C
00240
00241
00242 #define USICNT0_REG USISR
00243 #define USICNT1_REG USISR
00244 #define USICNT2_REG USISR
00245 #define USICNT3_REG USISR
00246 #define USIDC_REG USISR
00247 #define USIPF_REG USISR
00248 #define USIOIF_REG USISR
00249 #define USISIF_REG USISR
00250
00251
00252 #define TCNT1H0_REG TCNT1H
00253 #define TCNT1H1_REG TCNT1H
00254 #define TCNT1H2_REG TCNT1H
00255 #define TCNT1H3_REG TCNT1H
00256 #define TCNT1H4_REG TCNT1H
00257 #define TCNT1H5_REG TCNT1H
00258 #define TCNT1H6_REG TCNT1H
00259 #define TCNT1H7_REG TCNT1H
00260
00261
00262 #define PORTC0_REG PORTC
00263 #define PORTC1_REG PORTC
00264 #define PORTC2_REG PORTC
00265 #define PORTC3_REG PORTC
00266 #define PORTC4_REG PORTC
00267 #define PORTC5_REG PORTC
00268 #define PORTC6_REG PORTC
00269 #define PORTC7_REG PORTC
00270
00271
00272 #define PORTA0_REG PORTA
00273 #define PORTA1_REG PORTA
00274 #define PORTA2_REG PORTA
00275 #define PORTA3_REG PORTA
00276 #define PORTA4_REG PORTA
00277 #define PORTA5_REG PORTA
00278 #define PORTA6_REG PORTA
00279 #define PORTA7_REG PORTA
00280
00281
00282 #define UDR00_REG UDR0
00283 #define UDR01_REG UDR0
00284 #define UDR02_REG UDR0
00285 #define UDR03_REG UDR0
00286 #define UDR04_REG UDR0
00287 #define UDR05_REG UDR0
00288 #define UDR06_REG UDR0
00289 #define UDR07_REG UDR0
00290
00291
00292 #define GPIOR20_REG GPIOR2
00293 #define GPIOR21_REG GPIOR2
00294 #define GPIOR22_REG GPIOR2
00295 #define GPIOR23_REG GPIOR2
00296 #define GPIOR24_REG GPIOR2
00297 #define GPIOR25_REG GPIOR2
00298 #define GPIOR26_REG GPIOR2
00299 #define GPIOR27_REG GPIOR2
00300
00301
00302 #define ISC00_REG EICRA
00303 #define ISC01_REG EICRA
00304
00305
00306 #define ADC0D_REG DIDR0
00307 #define ADC1D_REG DIDR0
00308 #define ADC2D_REG DIDR0
00309 #define ADC3D_REG DIDR0
00310 #define ADC4D_REG DIDR0
00311 #define ADC5D_REG DIDR0
00312 #define ADC6D_REG DIDR0
00313 #define ADC7D_REG DIDR0
00314
00315
00316 #define AIN0D_REG DIDR1
00317 #define AIN1D_REG DIDR1
00318
00319
00320 #define TCR2UB_REG ASSR
00321 #define OCR2UB_REG ASSR
00322 #define TCN2UB_REG ASSR
00323 #define AS2_REG ASSR
00324 #define EXCLK_REG ASSR
00325
00326
00327 #define CLKPS0_REG CLKPR
00328 #define CLKPS1_REG CLKPR
00329 #define CLKPS2_REG CLKPR
00330 #define CLKPS3_REG CLKPR
00331 #define CLKPCE_REG CLKPR
00332
00333
00334 #define C_REG SREG
00335 #define Z_REG SREG
00336 #define N_REG SREG
00337 #define V_REG SREG
00338 #define S_REG SREG
00339 #define H_REG SREG
00340 #define T_REG SREG
00341 #define I_REG SREG
00342
00343
00344 #define DDJ0_REG DDRJ
00345 #define DDJ1_REG DDRJ
00346 #define DDJ2_REG DDRJ
00347 #define DDJ3_REG DDRJ
00348 #define DDJ4_REG DDRJ
00349 #define DDJ5_REG DDRJ
00350 #define DDJ6_REG DDRJ
00351
00352
00353 #define DDH0_REG DDRH
00354 #define DDH1_REG DDRH
00355 #define DDH2_REG DDRH
00356 #define DDH3_REG DDRH
00357 #define DDH4_REG DDRH
00358 #define DDH5_REG DDRH
00359 #define DDH6_REG DDRH
00360 #define DDH7_REG DDRH
00361
00362
00363 #define DDB0_REG DDRB
00364 #define DDB1_REG DDRB
00365 #define DDB2_REG DDRB
00366 #define DDB3_REG DDRB
00367 #define DDB4_REG DDRB
00368 #define DDB5_REG DDRB
00369 #define DDB6_REG DDRB
00370 #define DDB7_REG DDRB
00371
00372
00373 #define DDC0_REG DDRC
00374 #define DDC1_REG DDRC
00375 #define DDC2_REG DDRC
00376 #define DDC3_REG DDRC
00377 #define DDC4_REG DDRC
00378 #define DDC5_REG DDRC
00379 #define DDC6_REG DDRC
00380 #define DDC7_REG DDRC
00381
00382
00383 #define DDA0_REG DDRA
00384 #define DDA1_REG DDRA
00385 #define DDA2_REG DDRA
00386 #define DDA3_REG DDRA
00387 #define DDA4_REG DDRA
00388 #define DDA5_REG DDRA
00389 #define DDA6_REG DDRA
00390 #define DDA7_REG DDRA
00391
00392
00393 #define WGM10_REG TCCR1A
00394 #define WGM11_REG TCCR1A
00395 #define COM1B0_REG TCCR1A
00396 #define COM1B1_REG TCCR1A
00397 #define COM1A0_REG TCCR1A
00398 #define COM1A1_REG TCCR1A
00399
00400
00401 #define DDG0_REG DDRG
00402 #define DDG1_REG DDRG
00403 #define DDG2_REG DDRG
00404 #define DDG3_REG DDRG
00405 #define DDG4_REG DDRG
00406
00407
00408 #define FOC1B_REG TCCR1C
00409 #define FOC1A_REG TCCR1C
00410
00411
00412 #define CS10_REG TCCR1B
00413 #define CS11_REG TCCR1B
00414 #define CS12_REG TCCR1B
00415 #define WGM12_REG TCCR1B
00416 #define WGM13_REG TCCR1B
00417 #define ICES1_REG TCCR1B
00418 #define ICNC1_REG TCCR1B
00419
00420
00421 #define CAL0_REG OSCCAL
00422 #define CAL1_REG OSCCAL
00423 #define CAL2_REG OSCCAL
00424 #define CAL3_REG OSCCAL
00425 #define CAL4_REG OSCCAL
00426 #define CAL5_REG OSCCAL
00427 #define CAL6_REG OSCCAL
00428 #define CAL7_REG OSCCAL
00429
00430
00431 #define SEG024_REG LCDDR3
00432 #define SEG025_REG LCDDR3
00433 #define SEG026_REG LCDDR3
00434 #define SEG027_REG LCDDR3
00435 #define SEG028_REG LCDDR3
00436 #define SEG029_REG LCDDR3
00437 #define SEG030_REG LCDDR3
00438 #define SEG031_REG LCDDR3
00439
00440
00441 #define SEG016_REG LCDDR2
00442 #define SEG017_REG LCDDR2
00443 #define SEG018_REG LCDDR2
00444 #define SEG019_REG LCDDR2
00445 #define SEG020_REG LCDDR2
00446 #define SEG021_REG LCDDR2
00447 #define SEG022_REG LCDDR2
00448 #define SEG023_REG LCDDR2
00449
00450
00451 #define SEG008_REG LCDDR1
00452 #define SEG009_REG LCDDR1
00453 #define SEG010_REG LCDDR1
00454 #define SEG011_REG LCDDR1
00455 #define SEG012_REG LCDDR1
00456 #define SEG013_REG LCDDR1
00457 #define SEG014_REG LCDDR1
00458 #define SEG015_REG LCDDR1
00459
00460
00461 #define SEG000_REG LCDDR0
00462 #define SEG001_REG LCDDR0
00463 #define SEG002_REG LCDDR0
00464 #define SEG003_REG LCDDR0
00465 #define SEG004_REG LCDDR0
00466 #define SEG005_REG LCDDR0
00467 #define SEG006_REG LCDDR0
00468 #define SEG007_REG LCDDR0
00469
00470
00471 #define SEG116_REG LCDDR7
00472 #define SEG117_REG LCDDR7
00473 #define SEG118_REG LCDDR7
00474 #define SEG119_REG LCDDR7
00475 #define SEG120_REG LCDDR7
00476 #define SEG121_REG LCDDR7
00477 #define SEG122_REG LCDDR7
00478 #define SEG123_REG LCDDR7
00479
00480
00481 #define SEG108_REG LCDDR6
00482 #define SEG109_REG LCDDR6
00483 #define SEG110_REG LCDDR6
00484 #define SEG111_REG LCDDR6
00485 #define SEG112_REG LCDDR6
00486 #define SEG113_REG LCDDR6
00487 #define SEG114_REG LCDDR6
00488 #define SEG115_REG LCDDR6
00489
00490
00491 #define SEG100_REG LCDDR5
00492 #define SEG101_REG LCDDR5
00493 #define SEG102_REG LCDDR5
00494 #define SEG103_REG LCDDR5
00495 #define SEG104_REG LCDDR5
00496 #define SEG105_REG LCDDR5
00497 #define SEG106_REG LCDDR5
00498 #define SEG107_REG LCDDR5
00499
00500
00501 #define SEG032_REG LCDDR4
00502 #define SEG033_REG LCDDR4
00503 #define SEG034_REG LCDDR4
00504 #define SEG035_REG LCDDR4
00505 #define SEG036_REG LCDDR4
00506 #define SEG037_REG LCDDR4
00507 #define SEG038_REG LCDDR4
00508 #define SEG039_REG LCDDR4
00509
00510
00511 #define GPIOR10_REG GPIOR1
00512 #define GPIOR11_REG GPIOR1
00513 #define GPIOR12_REG GPIOR1
00514 #define GPIOR13_REG GPIOR1
00515 #define GPIOR14_REG GPIOR1
00516 #define GPIOR15_REG GPIOR1
00517 #define GPIOR16_REG GPIOR1
00518 #define GPIOR17_REG GPIOR1
00519
00520
00521 #define GPIOR00_REG GPIOR0
00522 #define GPIOR01_REG GPIOR0
00523 #define GPIOR02_REG GPIOR0
00524 #define GPIOR03_REG GPIOR0
00525 #define GPIOR04_REG GPIOR0
00526 #define GPIOR05_REG GPIOR0
00527 #define GPIOR06_REG GPIOR0
00528 #define GPIOR07_REG GPIOR0
00529
00530
00531 #define SEG132_REG LCDDR9
00532 #define SEG133_REG LCDDR9
00533 #define SEG134_REG LCDDR9
00534 #define SEG135_REG LCDDR9
00535 #define SEG136_REG LCDDR9
00536 #define SEG137_REG LCDDR9
00537 #define SEG138_REG LCDDR9
00538 #define SEG139_REG LCDDR9
00539
00540
00541 #define SEG124_REG LCDDR8
00542 #define SEG125_REG LCDDR8
00543 #define SEG126_REG LCDDR8
00544 #define SEG127_REG LCDDR8
00545 #define SEG128_REG LCDDR8
00546 #define SEG129_REG LCDDR8
00547 #define SEG130_REG LCDDR8
00548 #define SEG131_REG LCDDR8
00549
00550
00551 #define LCDBL_REG LCDCRA
00552 #define LCDIE_REG LCDCRA
00553 #define LCDIF_REG LCDCRA
00554 #define LCDAB_REG LCDCRA
00555 #define LCDEN_REG LCDCRA
00556
00557
00558 #define DDE0_REG DDRE
00559 #define DDE1_REG DDRE
00560 #define DDE2_REG DDRE
00561 #define DDE3_REG DDRE
00562 #define DDE4_REG DDRE
00563 #define DDE5_REG DDRE
00564 #define DDE6_REG DDRE
00565 #define DDE7_REG DDRE
00566
00567
00568 #define LCDPM0_REG LCDCRB
00569 #define LCDPM1_REG LCDCRB
00570 #define LCDPM2_REG LCDCRB
00571 #define LCDPM3_REG LCDCRB
00572 #define LCDMUX0_REG LCDCRB
00573 #define LCDMUX1_REG LCDCRB
00574 #define LCD2B_REG LCDCRB
00575 #define LCDCS_REG LCDCRB
00576
00577
00578 #define TCNT2_0_REG TCNT2
00579 #define TCNT2_1_REG TCNT2
00580 #define TCNT2_2_REG TCNT2
00581 #define TCNT2_3_REG TCNT2
00582 #define TCNT2_4_REG TCNT2
00583 #define TCNT2_5_REG TCNT2
00584 #define TCNT2_6_REG TCNT2
00585 #define TCNT2_7_REG TCNT2
00586
00587
00588 #define TCNT0_0_REG TCNT0
00589 #define TCNT0_1_REG TCNT0
00590 #define TCNT0_2_REG TCNT0
00591 #define TCNT0_3_REG TCNT0
00592 #define TCNT0_4_REG TCNT0
00593 #define TCNT0_5_REG TCNT0
00594 #define TCNT0_6_REG TCNT0
00595 #define TCNT0_7_REG TCNT0
00596
00597
00598 #define CS00_REG TCCR0A
00599 #define CS01_REG TCCR0A
00600 #define CS02_REG TCCR0A
00601 #define WGM01_REG TCCR0A
00602 #define COM0A0_REG TCCR0A
00603 #define COM0A1_REG TCCR0A
00604 #define WGM00_REG TCCR0A
00605 #define FOC0A_REG TCCR0A
00606
00607
00608 #define TOV2_REG TIFR2
00609 #define OCF2A_REG TIFR2
00610
00611
00612 #define SPR0_REG SPCR
00613 #define SPR1_REG SPCR
00614 #define CPHA_REG SPCR
00615 #define CPOL_REG SPCR
00616 #define MSTR_REG SPCR
00617 #define DORD_REG SPCR
00618 #define SPE_REG SPCR
00619 #define SPIE_REG SPCR
00620
00621
00622 #define TOV1_REG TIFR1
00623 #define OCF1A_REG TIFR1
00624 #define OCF1B_REG TIFR1
00625 #define ICF1_REG TIFR1
00626
00627
00628 #define PSR310_REG GTCCR
00629 #define TSM_REG GTCCR
00630 #define PSR2_REG GTCCR
00631
00632
00633 #define ICR1H0_REG ICR1H
00634 #define ICR1H1_REG ICR1H
00635 #define ICR1H2_REG ICR1H
00636 #define ICR1H3_REG ICR1H
00637 #define ICR1H4_REG ICR1H
00638 #define ICR1H5_REG ICR1H
00639 #define ICR1H6_REG ICR1H
00640 #define ICR1H7_REG ICR1H
00641
00642
00643 #define SEG332_REG LCDDR19
00644 #define SEG333_REG LCDDR19
00645 #define SEG334_REG LCDDR19
00646 #define SEG335_REG LCDDR19
00647 #define SEG336_REG LCDDR19
00648 #define SEG337_REG LCDDR19
00649 #define SEG338_REG LCDDR19
00650 #define SEG339_REG LCDDR19
00651
00652
00653 #define SEG324_REG LCDDR18
00654 #define SEG325_REG LCDDR18
00655 #define SEG326_REG LCDDR18
00656 #define SEG327_REG LCDDR18
00657 #define SEG328_REG LCDDR18
00658 #define SEG329_REG LCDDR18
00659 #define SEG330_REG LCDDR18
00660 #define SEG331_REG LCDDR18
00661
00662
00663 #define SEG224_REG LCDDR13
00664 #define SEG225_REG LCDDR13
00665 #define SEG226_REG LCDDR13
00666 #define SEG227_REG LCDDR13
00667 #define SEG228_REG LCDDR13
00668 #define SEG229_REG LCDDR13
00669 #define SEG230_REG LCDDR13
00670 #define SEG231_REG LCDDR13
00671
00672
00673 #define SEG216_REG LCDDR12
00674 #define SEG217_REG LCDDR12
00675 #define SEG218_REG LCDDR12
00676 #define SEG219_REG LCDDR12
00677 #define SEG220_REG LCDDR12
00678 #define SEG221_REG LCDDR12
00679 #define SEG222_REG LCDDR12
00680 #define SEG223_REG LCDDR12
00681
00682
00683 #define SEG208_REG LCDDR11
00684 #define SEG209_REG LCDDR11
00685 #define SEG210_REG LCDDR11
00686 #define SEG211_REG LCDDR11
00687 #define SEG212_REG LCDDR11
00688 #define SEG213_REG LCDDR11
00689 #define SEG214_REG LCDDR11
00690 #define SEG215_REG LCDDR11
00691
00692
00693 #define SEG200_REG LCDDR10
00694 #define SEG201_REG LCDDR10
00695 #define SEG202_REG LCDDR10
00696 #define SEG203_REG LCDDR10
00697 #define SEG204_REG LCDDR10
00698 #define SEG205_REG LCDDR10
00699 #define SEG206_REG LCDDR10
00700 #define SEG207_REG LCDDR10
00701
00702
00703 #define SEG316_REG LCDDR17
00704 #define SEG317_REG LCDDR17
00705 #define SEG318_REG LCDDR17
00706 #define SEG319_REG LCDDR17
00707 #define SEG320_REG LCDDR17
00708 #define SEG321_REG LCDDR17
00709 #define SEG322_REG LCDDR17
00710 #define SEG323_REG LCDDR17
00711
00712
00713 #define SEG308_REG LCDDR16
00714 #define SEG309_REG LCDDR16
00715 #define SEG310_REG LCDDR16
00716 #define SEG311_REG LCDDR16
00717 #define SEG312_REG LCDDR16
00718 #define SEG313_REG LCDDR16
00719 #define SEG314_REG LCDDR16
00720 #define SEG315_REG LCDDR16
00721
00722
00723 #define SEG300_REG LCDDR15
00724 #define SEG301_REG LCDDR15
00725 #define SEG302_REG LCDDR15
00726 #define SEG303_REG LCDDR15
00727 #define SEG304_REG LCDDR15
00728 #define SEG305_REG LCDDR15
00729 #define SEG306_REG LCDDR15
00730 #define SEG307_REG LCDDR15
00731
00732
00733 #define SEG232_REG LCDDR14
00734 #define SEG233_REG LCDDR14
00735 #define SEG234_REG LCDDR14
00736 #define SEG235_REG LCDDR14
00737 #define SEG236_REG LCDDR14
00738 #define SEG237_REG LCDDR14
00739 #define SEG238_REG LCDDR14
00740 #define SEG239_REG LCDDR14
00741
00742
00743 #define OCR1BL0_REG OCR1BL
00744 #define OCR1BL1_REG OCR1BL
00745 #define OCR1BL2_REG OCR1BL
00746 #define OCR1BL3_REG OCR1BL
00747 #define OCR1BL4_REG OCR1BL
00748 #define OCR1BL5_REG OCR1BL
00749 #define OCR1BL6_REG OCR1BL
00750 #define OCR1BL7_REG OCR1BL
00751
00752
00753 #define OCR1BH0_REG OCR1BH
00754 #define OCR1BH1_REG OCR1BH
00755 #define OCR1BH2_REG OCR1BH
00756 #define OCR1BH3_REG OCR1BH
00757 #define OCR1BH4_REG OCR1BH
00758 #define OCR1BH5_REG OCR1BH
00759 #define OCR1BH6_REG OCR1BH
00760 #define OCR1BH7_REG OCR1BH
00761
00762
00763 #define SP0_REG SPL
00764 #define SP1_REG SPL
00765 #define SP2_REG SPL
00766 #define SP3_REG SPL
00767 #define SP4_REG SPL
00768 #define SP5_REG SPL
00769 #define SP6_REG SPL
00770 #define SP7_REG SPL
00771
00772
00773 #define PORF_REG MCUSR
00774 #define EXTRF_REG MCUSR
00775 #define BORF_REG MCUSR
00776 #define WDRF_REG MCUSR
00777 #define JTRF_REG MCUSR
00778
00779
00780 #define EERE_REG EECR
00781 #define EEWE_REG EECR
00782 #define EEMWE_REG EECR
00783 #define EERIE_REG EECR
00784
00785
00786 #define SE_REG SMCR
00787 #define SM0_REG SMCR
00788 #define SM1_REG SMCR
00789 #define SM2_REG SMCR
00790
00791
00792 #define CS20_REG TCCR2A
00793 #define CS21_REG TCCR2A
00794 #define CS22_REG TCCR2A
00795 #define WGM21_REG TCCR2A
00796 #define COM2A0_REG TCCR2A
00797 #define COM2A1_REG TCCR2A
00798 #define WGM20_REG TCCR2A
00799 #define FOC2A_REG TCCR2A
00800
00801
00802 #define UBRR8_REG UBRR0H
00803 #define UBRR9_REG UBRR0H
00804 #define UBRR10_REG UBRR0H
00805 #define UBRR11_REG UBRR0H
00806
00807
00808 #define UBRR0_REG UBRR0L
00809 #define UBRR1_REG UBRR0L
00810 #define UBRR2_REG UBRR0L
00811 #define UBRR3_REG UBRR0L
00812 #define UBRR4_REG UBRR0L
00813 #define UBRR5_REG UBRR0L
00814 #define UBRR6_REG UBRR0L
00815 #define UBRR7_REG UBRR0L
00816
00817
00818 #define EEAR8_REG EEARH
00819 #define EEAR9_REG EEARH
00820 #define EEAR10_REG EEARH
00821
00822
00823 #define EEARL0_REG EEARL
00824 #define EEARL1_REG EEARL
00825 #define EEARL2_REG EEARL
00826 #define EEARL3_REG EEARL
00827 #define EEARL4_REG EEARL
00828 #define EEARL5_REG EEARL
00829 #define EEARL6_REG EEARL
00830 #define EEARL7_REG EEARL
00831
00832
00833 #define IVCE_REG MCUCR
00834 #define IVSEL_REG MCUCR
00835 #define PUD_REG MCUCR
00836 #define JTD_REG MCUCR
00837
00838
00839 #define OCDR0_REG OCDR
00840 #define OCDR1_REG OCDR
00841 #define OCDR2_REG OCDR
00842 #define OCDR3_REG OCDR
00843 #define OCDR4_REG OCDR
00844 #define OCDR5_REG OCDR
00845 #define OCDR6_REG OCDR
00846 #define OCDR7_REG OCDR
00847
00848
00849 #define PINA0_REG PINA
00850 #define PINA1_REG PINA
00851 #define PINA2_REG PINA
00852 #define PINA3_REG PINA
00853 #define PINA4_REG PINA
00854 #define PINA5_REG PINA
00855 #define PINA6_REG PINA
00856 #define PINA7_REG PINA
00857
00858
00859 #define PORTE0_REG PORTE
00860 #define PORTE1_REG PORTE
00861 #define PORTE2_REG PORTE
00862 #define PORTE3_REG PORTE
00863 #define PORTE4_REG PORTE
00864 #define PORTE5_REG PORTE
00865 #define PORTE6_REG PORTE
00866 #define PORTE7_REG PORTE
00867
00868
00869 #define LCDCC0_REG LCDCCR
00870 #define LCDCC1_REG LCDCCR
00871 #define LCDCC2_REG LCDCCR
00872 #define LCDCC3_REG LCDCCR
00873 #define LCDDC0_REG LCDCCR
00874 #define LCDDC1_REG LCDCCR
00875 #define LCDDC2_REG LCDCCR
00876
00877
00878 #define PINE0_REG PINE
00879 #define PINE1_REG PINE
00880 #define PINE2_REG PINE
00881 #define PINE3_REG PINE
00882 #define PINE4_REG PINE
00883 #define PINE5_REG PINE
00884 #define PINE6_REG PINE
00885 #define PINE7_REG PINE
00886
00887
00888 #define ADPS0_REG ADCSRA
00889 #define ADPS1_REG ADCSRA
00890 #define ADPS2_REG ADCSRA
00891 #define ADIE_REG ADCSRA
00892 #define ADIF_REG ADCSRA
00893 #define ADATE_REG ADCSRA
00894 #define ADSC_REG ADCSRA
00895 #define ADEN_REG ADCSRA
00896
00897
00898 #define ADTS0_REG ADCSRB
00899 #define ADTS1_REG ADCSRB
00900 #define ADTS2_REG ADCSRB
00901 #define ACME_REG ADCSRB
00902
00903
00904 #define DDF0_REG DDRF
00905 #define DDF1_REG DDRF
00906 #define DDF2_REG DDRF
00907 #define DDF3_REG DDRF
00908 #define DDF4_REG DDRF
00909 #define DDF5_REG DDRF
00910 #define DDF6_REG DDRF
00911 #define DDF7_REG DDRF
00912
00913
00914 #define OCR0A0_REG OCR0A
00915 #define OCR0A1_REG OCR0A
00916 #define OCR0A2_REG OCR0A
00917 #define OCR0A3_REG OCR0A
00918 #define OCR0A4_REG OCR0A
00919 #define OCR0A5_REG OCR0A
00920 #define OCR0A6_REG OCR0A
00921 #define OCR0A7_REG OCR0A
00922
00923
00924 #define ACIS0_REG ACSR
00925 #define ACIS1_REG ACSR
00926 #define ACIC_REG ACSR
00927 #define ACIE_REG ACSR
00928 #define ACI_REG ACSR
00929 #define ACO_REG ACSR
00930 #define ACBG_REG ACSR
00931 #define ACD_REG ACSR
00932
00933
00934 #define TCNT1L0_REG TCNT1L
00935 #define TCNT1L1_REG TCNT1L
00936 #define TCNT1L2_REG TCNT1L
00937 #define TCNT1L3_REG TCNT1L
00938 #define TCNT1L4_REG TCNT1L
00939 #define TCNT1L5_REG TCNT1L
00940 #define TCNT1L6_REG TCNT1L
00941 #define TCNT1L7_REG TCNT1L
00942
00943
00944 #define DDD0_REG DDRD
00945 #define DDD1_REG DDRD
00946 #define DDD2_REG DDRD
00947 #define DDD3_REG DDRD
00948 #define DDD4_REG DDRD
00949 #define DDD5_REG DDRD
00950 #define DDD6_REG DDRD
00951 #define DDD7_REG DDRD
00952
00953
00954 #define USITC_REG USICR
00955 #define USICLK_REG USICR
00956 #define USICS0_REG USICR
00957 #define USICS1_REG USICR
00958 #define USIWM0_REG USICR
00959 #define USIWM1_REG USICR
00960 #define USIOIE_REG USICR
00961 #define USISIE_REG USICR
00962
00963
00964 #define PORTD0_REG PORTD
00965 #define PORTD1_REG PORTD
00966 #define PORTD2_REG PORTD
00967 #define PORTD3_REG PORTD
00968 #define PORTD4_REG PORTD
00969 #define PORTD5_REG PORTD
00970 #define PORTD6_REG PORTD
00971 #define PORTD7_REG PORTD
00972
00973
00974 #define TXB80_REG UCSR0B
00975 #define RXB80_REG UCSR0B
00976 #define UCSZ02_REG UCSR0B
00977 #define TXEN0_REG UCSR0B
00978 #define RXEN0_REG UCSR0B
00979 #define UDRIE0_REG UCSR0B
00980 #define TXCIE0_REG UCSR0B
00981 #define RXCIE0_REG UCSR0B
00982
00983
00984 #define SPMEN_REG SPMCSR
00985 #define PGERS_REG SPMCSR
00986 #define PGWRT_REG SPMCSR
00987 #define BLBSET_REG SPMCSR
00988 #define RWWSRE_REG SPMCSR
00989 #define RWWSB_REG SPMCSR
00990 #define SPMIE_REG SPMCSR
00991
00992
00993 #define PORTB0_REG PORTB
00994 #define PORTB1_REG PORTB
00995 #define PORTB2_REG PORTB
00996 #define PORTB3_REG PORTB
00997 #define PORTB4_REG PORTB
00998 #define PORTB5_REG PORTB
00999 #define PORTB6_REG PORTB
01000 #define PORTB7_REG PORTB
01001
01002
01003 #define ADCL0_REG ADCL
01004 #define ADCL1_REG ADCL
01005 #define ADCL2_REG ADCL
01006 #define ADCL3_REG ADCL
01007 #define ADCL4_REG ADCL
01008 #define ADCL5_REG ADCL
01009 #define ADCL6_REG ADCL
01010 #define ADCL7_REG ADCL
01011
01012
01013 #define ADCH0_REG ADCH
01014 #define ADCH1_REG ADCH
01015 #define ADCH2_REG ADCH
01016 #define ADCH3_REG ADCH
01017 #define ADCH4_REG ADCH
01018 #define ADCH5_REG ADCH
01019 #define ADCH6_REG ADCH
01020 #define ADCH7_REG ADCH
01021
01022
01023 #define LCDCD0_REG LCDFRR
01024 #define LCDCD1_REG LCDFRR
01025 #define LCDCD2_REG LCDFRR
01026 #define LCDPS0_REG LCDFRR
01027 #define LCDPS1_REG LCDFRR
01028 #define LCDPS2_REG LCDFRR
01029
01030
01031 #define TOIE2_REG TIMSK2
01032 #define OCIE2A_REG TIMSK2
01033
01034
01035 #define INT0_REG EIMSK
01036 #define PCIE0_REG EIMSK
01037 #define PCIE1_REG EIMSK
01038 #define PCIE2_REG EIMSK
01039 #define PCIE3_REG EIMSK
01040
01041
01042 #define TOIE0_REG TIMSK0
01043 #define OCIE0A_REG TIMSK0
01044
01045
01046 #define TOIE1_REG TIMSK1
01047 #define OCIE1A_REG TIMSK1
01048 #define OCIE1B_REG TIMSK1
01049 #define ICIE1_REG TIMSK1
01050
01051
01052 #define PINJ0_REG PINJ
01053 #define PINJ1_REG PINJ
01054 #define PINJ2_REG PINJ
01055 #define PINJ3_REG PINJ
01056 #define PINJ4_REG PINJ
01057 #define PINJ5_REG PINJ
01058 #define PINJ6_REG PINJ
01059
01060
01061 #define PINH0_REG PINH
01062 #define PINH1_REG PINH
01063 #define PINH2_REG PINH
01064 #define PINH3_REG PINH
01065 #define PINH4_REG PINH
01066 #define PINH5_REG PINH
01067 #define PINH6_REG PINH
01068 #define PINH7_REG PINH
01069
01070
01071 #define PCINT0_REG PCMSK0
01072 #define PCINT1_REG PCMSK0
01073 #define PCINT2_REG PCMSK0
01074 #define PCINT3_REG PCMSK0
01075 #define PCINT4_REG PCMSK0
01076 #define PCINT5_REG PCMSK0
01077 #define PCINT6_REG PCMSK0
01078 #define PCINT7_REG PCMSK0
01079
01080
01081 #define PCINT8_REG PCMSK1
01082 #define PCINT9_REG PCMSK1
01083 #define PCINT10_REG PCMSK1
01084 #define PCINT11_REG PCMSK1
01085 #define PCINT12_REG PCMSK1
01086 #define PCINT13_REG PCMSK1
01087 #define PCINT14_REG PCMSK1
01088 #define PCINT15_REG PCMSK1
01089
01090
01091 #define PCINT16_REG PCMSK2
01092 #define PCINT17_REG PCMSK2
01093 #define PCINT18_REG PCMSK2
01094 #define PCINT19_REG PCMSK2
01095 #define PCINT20_REG PCMSK2
01096 #define PCINT21_REG PCMSK2
01097 #define PCINT22_REG PCMSK2
01098 #define PCINT23_REG PCMSK2
01099
01100
01101 #define PCINT24_REG PCMSK3
01102 #define PCINT25_REG PCMSK3
01103 #define PCINT26_REG PCMSK3
01104 #define PCINT27_REG PCMSK3
01105 #define PCINT28_REG PCMSK3
01106 #define PCINT29_REG PCMSK3
01107 #define PCINT30_REG PCMSK3
01108
01109
01110 #define PINC0_REG PINC
01111 #define PINC1_REG PINC
01112 #define PINC2_REG PINC
01113 #define PINC3_REG PINC
01114 #define PINC4_REG PINC
01115 #define PINC5_REG PINC
01116 #define PINC6_REG PINC
01117 #define PINC7_REG PINC
01118
01119
01120 #define PINB0_REG PINB
01121 #define PINB1_REG PINB
01122 #define PINB2_REG PINB
01123 #define PINB3_REG PINB
01124 #define PINB4_REG PINB
01125 #define PINB5_REG PINB
01126 #define PINB6_REG PINB
01127 #define PINB7_REG PINB
01128
01129
01130 #define INTF0_REG EIFR
01131 #define PCIF0_REG EIFR
01132 #define PCIF1_REG EIFR
01133 #define PCIF2_REG EIFR
01134 #define PCIF3_REG EIFR
01135
01136
01137 #define PING0_REG PING
01138 #define PING1_REG PING
01139 #define PING2_REG PING
01140 #define PING3_REG PING
01141 #define PING4_REG PING
01142 #define PING5_REG PING
01143
01144
01145 #define PINF0_REG PINF
01146 #define PINF1_REG PINF
01147 #define PINF2_REG PINF
01148 #define PINF3_REG PINF
01149 #define PINF4_REG PINF
01150 #define PINF5_REG PINF
01151 #define PINF6_REG PINF
01152 #define PINF7_REG PINF
01153
01154
01155 #define PORTF0_REG PORTF
01156 #define PORTF1_REG PORTF
01157 #define PORTF2_REG PORTF
01158 #define PORTF3_REG PORTF
01159 #define PORTF4_REG PORTF
01160 #define PORTF5_REG PORTF
01161 #define PORTF6_REG PORTF
01162 #define PORTF7_REG PORTF
01163
01164
01165 #define PIND0_REG PIND
01166 #define PIND1_REG PIND
01167 #define PIND2_REG PIND
01168 #define PIND3_REG PIND
01169 #define PIND4_REG PIND
01170 #define PIND5_REG PIND
01171 #define PIND6_REG PIND
01172 #define PIND7_REG PIND
01173
01174
01175 #define OCR1AH0_REG OCR1AH
01176 #define OCR1AH1_REG OCR1AH
01177 #define OCR1AH2_REG OCR1AH
01178 #define OCR1AH3_REG OCR1AH
01179 #define OCR1AH4_REG OCR1AH
01180 #define OCR1AH5_REG OCR1AH
01181 #define OCR1AH6_REG OCR1AH
01182 #define OCR1AH7_REG OCR1AH
01183
01184
01185 #define OCR1AL0_REG OCR1AL
01186 #define OCR1AL1_REG OCR1AL
01187 #define OCR1AL2_REG OCR1AL
01188 #define OCR1AL3_REG OCR1AL
01189 #define OCR1AL4_REG OCR1AL
01190 #define OCR1AL5_REG OCR1AL
01191 #define OCR1AL6_REG OCR1AL
01192 #define OCR1AL7_REG OCR1AL
01193
01194
01195 #define TOV0_REG TIFR0
01196 #define OCF0A_REG TIFR0
01197
01198
01199 #define USIDR0_REG USIDR
01200 #define USIDR1_REG USIDR
01201 #define USIDR2_REG USIDR
01202 #define USIDR3_REG USIDR
01203 #define USIDR4_REG USIDR
01204 #define USIDR5_REG USIDR
01205 #define USIDR6_REG USIDR
01206 #define USIDR7_REG USIDR
01207
01208
01209