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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define WDP0_REG WDTCR
00119 #define WDP1_REG WDTCR
00120 #define WDP2_REG WDTCR
00121 #define WDE_REG WDTCR
00122 #define WDCE_REG WDTCR
00123
00124
00125 #define MUX0_REG ADMUX
00126 #define MUX1_REG ADMUX
00127 #define MUX2_REG ADMUX
00128 #define MUX3_REG ADMUX
00129 #define MUX4_REG ADMUX
00130 #define ADLAR_REG ADMUX
00131 #define REFS0_REG ADMUX
00132 #define REFS1_REG ADMUX
00133
00134
00135 #define EEDR0_REG EEDR
00136 #define EEDR1_REG EEDR
00137 #define EEDR2_REG EEDR
00138 #define EEDR3_REG EEDR
00139 #define EEDR4_REG EEDR
00140 #define EEDR5_REG EEDR
00141 #define EEDR6_REG EEDR
00142 #define EEDR7_REG EEDR
00143
00144
00145 #define OCR2A0_REG OCR2A
00146 #define OCR2A1_REG OCR2A
00147 #define OCR2A2_REG OCR2A
00148 #define OCR2A3_REG OCR2A
00149 #define OCR2A4_REG OCR2A
00150 #define OCR2A5_REG OCR2A
00151 #define OCR2A6_REG OCR2A
00152 #define OCR2A7_REG OCR2A
00153
00154
00155 #define SPDR0_REG SPDR
00156 #define SPDR1_REG SPDR
00157 #define SPDR2_REG SPDR
00158 #define SPDR3_REG SPDR
00159 #define SPDR4_REG SPDR
00160 #define SPDR5_REG SPDR
00161 #define SPDR6_REG SPDR
00162 #define SPDR7_REG SPDR
00163
00164
00165 #define SPI2X_REG SPSR
00166 #define WCOL_REG SPSR
00167 #define SPIF_REG SPSR
00168
00169
00170 #define SP8_REG SPH
00171 #define SP9_REG SPH
00172 #define SP10_REG SPH
00173 #define SP11_REG SPH
00174 #define SP12_REG SPH
00175 #define SP13_REG SPH
00176 #define SP14_REG SPH
00177 #define SP15_REG SPH
00178
00179
00180 #define ICR1L0_REG ICR1L
00181 #define ICR1L1_REG ICR1L
00182 #define ICR1L2_REG ICR1L
00183 #define ICR1L3_REG ICR1L
00184 #define ICR1L4_REG ICR1L
00185 #define ICR1L5_REG ICR1L
00186 #define ICR1L6_REG ICR1L
00187 #define ICR1L7_REG ICR1L
00188
00189
00190 #define PRADC_REG PRR
00191 #define PRUSART0_REG PRR
00192 #define PRSPI_REG PRR
00193 #define PRTIM1_REG PRR
00194 #define PRLCD_REG PRR
00195
00196
00197 #define PORTF0_REG PORTF
00198 #define PORTF1_REG PORTF
00199 #define PORTF2_REG PORTF
00200 #define PORTF3_REG PORTF
00201 #define PORTF4_REG PORTF
00202 #define PORTF5_REG PORTF
00203 #define PORTF6_REG PORTF
00204 #define PORTF7_REG PORTF
00205
00206
00207 #define PORTG0_REG PORTG
00208 #define PORTG1_REG PORTG
00209 #define PORTG2_REG PORTG
00210 #define PORTG3_REG PORTG
00211 #define PORTG4_REG PORTG
00212
00213
00214 #define PORTD0_REG PORTD
00215 #define PORTD1_REG PORTD
00216 #define PORTD2_REG PORTD
00217 #define PORTD3_REG PORTD
00218 #define PORTD4_REG PORTD
00219 #define PORTD5_REG PORTD
00220 #define PORTD6_REG PORTD
00221 #define PORTD7_REG PORTD
00222
00223
00224 #define PORTE0_REG PORTE
00225 #define PORTE1_REG PORTE
00226 #define PORTE2_REG PORTE
00227 #define PORTE3_REG PORTE
00228 #define PORTE4_REG PORTE
00229 #define PORTE5_REG PORTE
00230 #define PORTE6_REG PORTE
00231 #define PORTE7_REG PORTE
00232
00233
00234 #define PORTB0_REG PORTB
00235 #define PORTB1_REG PORTB
00236 #define PORTB2_REG PORTB
00237 #define PORTB3_REG PORTB
00238 #define PORTB4_REG PORTB
00239 #define PORTB5_REG PORTB
00240 #define PORTB6_REG PORTB
00241 #define PORTB7_REG PORTB
00242
00243
00244 #define PORTC0_REG PORTC
00245 #define PORTC1_REG PORTC
00246 #define PORTC2_REG PORTC
00247 #define PORTC3_REG PORTC
00248 #define PORTC4_REG PORTC
00249 #define PORTC5_REG PORTC
00250 #define PORTC6_REG PORTC
00251 #define PORTC7_REG PORTC
00252
00253
00254 #define PORTA0_REG PORTA
00255 #define PORTA1_REG PORTA
00256 #define PORTA2_REG PORTA
00257 #define PORTA3_REG PORTA
00258 #define PORTA4_REG PORTA
00259 #define PORTA5_REG PORTA
00260 #define PORTA6_REG PORTA
00261 #define PORTA7_REG PORTA
00262
00263
00264 #define UDR00_REG UDR0
00265 #define UDR01_REG UDR0
00266 #define UDR02_REG UDR0
00267 #define UDR03_REG UDR0
00268 #define UDR04_REG UDR0
00269 #define UDR05_REG UDR0
00270 #define UDR06_REG UDR0
00271 #define UDR07_REG UDR0
00272
00273
00274 #define ISC00_REG EICRA
00275 #define ISC01_REG EICRA
00276
00277
00278 #define ADC0D_REG DIDR0
00279 #define ADC1D_REG DIDR0
00280 #define ADC2D_REG DIDR0
00281 #define ADC3D_REG DIDR0
00282 #define ADC4D_REG DIDR0
00283 #define ADC5D_REG DIDR0
00284 #define ADC6D_REG DIDR0
00285 #define ADC7D_REG DIDR0
00286
00287
00288 #define AIN0D_REG DIDR1
00289 #define AIN1D_REG DIDR1
00290
00291
00292 #define TCR2UB_REG ASSR
00293 #define OCR2UB_REG ASSR
00294 #define TCN2UB_REG ASSR
00295 #define AS2_REG ASSR
00296 #define EXCLK_REG ASSR
00297
00298
00299 #define CLKPS0_REG CLKPR
00300 #define CLKPS1_REG CLKPR
00301 #define CLKPS2_REG CLKPR
00302 #define CLKPS3_REG CLKPR
00303 #define CLKPCE_REG CLKPR
00304
00305
00306 #define C_REG SREG
00307 #define Z_REG SREG
00308 #define N_REG SREG
00309 #define V_REG SREG
00310 #define S_REG SREG
00311 #define H_REG SREG
00312 #define T_REG SREG
00313 #define I_REG SREG
00314
00315
00316 #define DDB0_REG DDRB
00317 #define DDB1_REG DDRB
00318 #define DDB2_REG DDRB
00319 #define DDB3_REG DDRB
00320 #define DDB4_REG DDRB
00321 #define DDB5_REG DDRB
00322 #define DDB6_REG DDRB
00323 #define DDB7_REG DDRB
00324
00325
00326 #define DDC0_REG DDRC
00327 #define DDC1_REG DDRC
00328 #define DDC2_REG DDRC
00329 #define DDC3_REG DDRC
00330 #define DDC4_REG DDRC
00331 #define DDC5_REG DDRC
00332 #define DDC6_REG DDRC
00333 #define DDC7_REG DDRC
00334
00335
00336 #define DDA0_REG DDRA
00337 #define DDA1_REG DDRA
00338 #define DDA2_REG DDRA
00339 #define DDA3_REG DDRA
00340 #define DDA4_REG DDRA
00341 #define DDA5_REG DDRA
00342 #define DDA6_REG DDRA
00343 #define DDA7_REG DDRA
00344
00345
00346 #define WGM10_REG TCCR1A
00347 #define WGM11_REG TCCR1A
00348 #define COM1B0_REG TCCR1A
00349 #define COM1B1_REG TCCR1A
00350 #define COM1A0_REG TCCR1A
00351 #define COM1A1_REG TCCR1A
00352
00353
00354 #define DDG0_REG DDRG
00355 #define DDG1_REG DDRG
00356 #define DDG2_REG DDRG
00357 #define DDG3_REG DDRG
00358 #define DDG4_REG DDRG
00359
00360
00361 #define FOC1B_REG TCCR1C
00362 #define FOC1A_REG TCCR1C
00363
00364
00365 #define CS10_REG TCCR1B
00366 #define CS11_REG TCCR1B
00367 #define CS12_REG TCCR1B
00368 #define WGM12_REG TCCR1B
00369 #define WGM13_REG TCCR1B
00370 #define ICES1_REG TCCR1B
00371 #define ICNC1_REG TCCR1B
00372
00373
00374 #define CAL0_REG OSCCAL
00375 #define CAL1_REG OSCCAL
00376 #define CAL2_REG OSCCAL
00377 #define CAL3_REG OSCCAL
00378 #define CAL4_REG OSCCAL
00379 #define CAL5_REG OSCCAL
00380 #define CAL6_REG OSCCAL
00381 #define CAL7_REG OSCCAL
00382
00383
00384 #define GPIOR10_REG GPIOR1
00385 #define GPIOR11_REG GPIOR1
00386 #define GPIOR12_REG GPIOR1
00387 #define GPIOR13_REG GPIOR1
00388 #define GPIOR14_REG GPIOR1
00389 #define GPIOR15_REG GPIOR1
00390 #define GPIOR16_REG GPIOR1
00391 #define GPIOR17_REG GPIOR1
00392
00393
00394 #define GPIOR00_REG GPIOR0
00395 #define GPIOR01_REG GPIOR0
00396 #define GPIOR02_REG GPIOR0
00397 #define GPIOR03_REG GPIOR0
00398 #define GPIOR04_REG GPIOR0
00399 #define GPIOR05_REG GPIOR0
00400 #define GPIOR06_REG GPIOR0
00401 #define GPIOR07_REG GPIOR0
00402
00403
00404 #define GPIOR20_REG GPIOR2
00405 #define GPIOR21_REG GPIOR2
00406 #define GPIOR22_REG GPIOR2
00407 #define GPIOR23_REG GPIOR2
00408 #define GPIOR24_REG GPIOR2
00409 #define GPIOR25_REG GPIOR2
00410 #define GPIOR26_REG GPIOR2
00411 #define GPIOR27_REG GPIOR2
00412
00413
00414 #define DDE0_REG DDRE
00415 #define DDE1_REG DDRE
00416 #define DDE2_REG DDRE
00417 #define DDE3_REG DDRE
00418 #define DDE4_REG DDRE
00419 #define DDE5_REG DDRE
00420 #define DDE6_REG DDRE
00421 #define DDE7_REG DDRE
00422
00423
00424 #define TCNT2_0_REG TCNT2
00425 #define TCNT2_1_REG TCNT2
00426 #define TCNT2_2_REG TCNT2
00427 #define TCNT2_3_REG TCNT2
00428 #define TCNT2_4_REG TCNT2
00429 #define TCNT2_5_REG TCNT2
00430 #define TCNT2_6_REG TCNT2
00431 #define TCNT2_7_REG TCNT2
00432
00433
00434 #define TCNT0_0_REG TCNT0
00435 #define TCNT0_1_REG TCNT0
00436 #define TCNT0_2_REG TCNT0
00437 #define TCNT0_3_REG TCNT0
00438 #define TCNT0_4_REG TCNT0
00439 #define TCNT0_5_REG TCNT0
00440 #define TCNT0_6_REG TCNT0
00441 #define TCNT0_7_REG TCNT0
00442
00443
00444 #define CS00_REG TCCR0A
00445 #define CS01_REG TCCR0A
00446 #define CS02_REG TCCR0A
00447 #define WGM01_REG TCCR0A
00448 #define COM0A0_REG TCCR0A
00449 #define COM0A1_REG TCCR0A
00450 #define WGM00_REG TCCR0A
00451 #define FOC0A_REG TCCR0A
00452
00453
00454 #define TOV2_REG TIFR2
00455 #define OCF2A_REG TIFR2
00456
00457
00458 #define TOV0_REG TIFR0
00459 #define OCF0A_REG TIFR0
00460
00461
00462 #define TOV1_REG TIFR1
00463 #define OCF1A_REG TIFR1
00464 #define OCF1B_REG TIFR1
00465 #define ICF1_REG TIFR1
00466
00467
00468 #define PSR310_REG GTCCR
00469 #define TSM_REG GTCCR
00470 #define PSR2_REG GTCCR
00471
00472
00473 #define ICR1H0_REG ICR1H
00474 #define ICR1H1_REG ICR1H
00475 #define ICR1H2_REG ICR1H
00476 #define ICR1H3_REG ICR1H
00477 #define ICR1H4_REG ICR1H
00478 #define ICR1H5_REG ICR1H
00479 #define ICR1H6_REG ICR1H
00480 #define ICR1H7_REG ICR1H
00481
00482
00483 #define OCR1BL0_REG OCR1BL
00484 #define OCR1BL1_REG OCR1BL
00485 #define OCR1BL2_REG OCR1BL
00486 #define OCR1BL3_REG OCR1BL
00487 #define OCR1BL4_REG OCR1BL
00488 #define OCR1BL5_REG OCR1BL
00489 #define OCR1BL6_REG OCR1BL
00490 #define OCR1BL7_REG OCR1BL
00491
00492
00493 #define OCR1BH0_REG OCR1BH
00494 #define OCR1BH1_REG OCR1BH
00495 #define OCR1BH2_REG OCR1BH
00496 #define OCR1BH3_REG OCR1BH
00497 #define OCR1BH4_REG OCR1BH
00498 #define OCR1BH5_REG OCR1BH
00499 #define OCR1BH6_REG OCR1BH
00500 #define OCR1BH7_REG OCR1BH
00501
00502
00503 #define SP0_REG SPL
00504 #define SP1_REG SPL
00505 #define SP2_REG SPL
00506 #define SP3_REG SPL
00507 #define SP4_REG SPL
00508 #define SP5_REG SPL
00509 #define SP6_REG SPL
00510 #define SP7_REG SPL
00511
00512
00513 #define PORF_REG MCUSR
00514 #define EXTRF_REG MCUSR
00515 #define BORF_REG MCUSR
00516 #define WDRF_REG MCUSR
00517 #define JTRF_REG MCUSR
00518
00519
00520 #define EERE_REG EECR
00521 #define EEWE_REG EECR
00522 #define EEMWE_REG EECR
00523 #define EERIE_REG EECR
00524
00525
00526 #define SE_REG SMCR
00527 #define SM0_REG SMCR
00528 #define SM1_REG SMCR
00529 #define SM2_REG SMCR
00530
00531
00532 #define CS20_REG TCCR2A
00533 #define CS21_REG TCCR2A
00534 #define CS22_REG TCCR2A
00535 #define WGM21_REG TCCR2A
00536 #define COM2A0_REG TCCR2A
00537 #define COM2A1_REG TCCR2A
00538 #define WGM20_REG TCCR2A
00539 #define FOC2A_REG TCCR2A
00540
00541
00542 #define UBRR8_REG UBRR0H
00543 #define UBRR9_REG UBRR0H
00544 #define UBRR10_REG UBRR0H
00545 #define UBRR11_REG UBRR0H
00546
00547
00548 #define UBRR0_REG UBRR0L
00549 #define UBRR1_REG UBRR0L
00550 #define UBRR2_REG UBRR0L
00551 #define UBRR3_REG UBRR0L
00552 #define UBRR4_REG UBRR0L
00553 #define UBRR5_REG UBRR0L
00554 #define UBRR6_REG UBRR0L
00555 #define UBRR7_REG UBRR0L
00556
00557
00558 #define EEAR8_REG EEARH
00559 #define EEAR9_REG EEARH
00560 #define EEAR10_REG EEARH
00561
00562
00563 #define EEARL0_REG EEARL
00564 #define EEARL1_REG EEARL
00565 #define EEARL2_REG EEARL
00566 #define EEARL3_REG EEARL
00567 #define EEARL4_REG EEARL
00568 #define EEARL5_REG EEARL
00569 #define EEARL6_REG EEARL
00570 #define EEARL7_REG EEARL
00571
00572
00573 #define IVCE_REG MCUCR
00574 #define IVSEL_REG MCUCR
00575 #define PUD_REG MCUCR
00576 #define JTD_REG MCUCR
00577
00578
00579 #define PINC0_REG PINC
00580 #define PINC1_REG PINC
00581 #define PINC2_REG PINC
00582 #define PINC3_REG PINC
00583 #define PINC4_REG PINC
00584 #define PINC5_REG PINC
00585 #define PINC6_REG PINC
00586 #define PINC7_REG PINC
00587
00588
00589 #define OCDR0_REG OCDR
00590 #define OCDR1_REG OCDR
00591 #define OCDR2_REG OCDR
00592 #define OCDR3_REG OCDR
00593 #define OCDR4_REG OCDR
00594 #define OCDR5_REG OCDR
00595 #define OCDR6_REG OCDR
00596 #define OCDR7_REG OCDR
00597
00598
00599 #define PINA0_REG PINA
00600 #define PINA1_REG PINA
00601 #define PINA2_REG PINA
00602 #define PINA3_REG PINA
00603 #define PINA4_REG PINA
00604 #define PINA5_REG PINA
00605 #define PINA6_REG PINA
00606 #define PINA7_REG PINA
00607
00608
00609 #define USICNT0_REG USISR
00610 #define USICNT1_REG USISR
00611 #define USICNT2_REG USISR
00612 #define USICNT3_REG USISR
00613 #define USIDC_REG USISR
00614 #define USIPF_REG USISR
00615 #define USIOIF_REG USISR
00616 #define USISIF_REG USISR
00617
00618
00619 #define ADPS0_REG ADCSRA
00620 #define ADPS1_REG ADCSRA
00621 #define ADPS2_REG ADCSRA
00622 #define ADIE_REG ADCSRA
00623 #define ADIF_REG ADCSRA
00624 #define ADATE_REG ADCSRA
00625 #define ADSC_REG ADCSRA
00626 #define ADEN_REG ADCSRA
00627
00628
00629 #define ADTS0_REG ADCSRB
00630 #define ADTS1_REG ADCSRB
00631 #define ADTS2_REG ADCSRB
00632 #define ACME_REG ADCSRB
00633
00634
00635 #define DDF0_REG DDRF
00636 #define DDF1_REG DDRF
00637 #define DDF2_REG DDRF
00638 #define DDF3_REG DDRF
00639 #define DDF4_REG DDRF
00640 #define DDF5_REG DDRF
00641 #define DDF6_REG DDRF
00642 #define DDF7_REG DDRF
00643
00644
00645 #define OCR0A0_REG OCR0A
00646 #define OCR0A1_REG OCR0A
00647 #define OCR0A2_REG OCR0A
00648 #define OCR0A3_REG OCR0A
00649 #define OCR0A4_REG OCR0A
00650 #define OCR0A5_REG OCR0A
00651 #define OCR0A6_REG OCR0A
00652 #define OCR0A7_REG OCR0A
00653
00654
00655 #define ACIS0_REG ACSR
00656 #define ACIS1_REG ACSR
00657 #define ACIC_REG ACSR
00658 #define ACIE_REG ACSR
00659 #define ACI_REG ACSR
00660 #define ACO_REG ACSR
00661 #define ACBG_REG ACSR
00662 #define ACD_REG ACSR
00663
00664
00665 #define MPCM0_REG UCSR0A
00666 #define U2X0_REG UCSR0A
00667 #define UPE0_REG UCSR0A
00668 #define DOR0_REG UCSR0A
00669 #define FE0_REG UCSR0A
00670 #define UDRE0_REG UCSR0A
00671 #define TXC0_REG UCSR0A
00672 #define RXC0_REG UCSR0A
00673
00674
00675 #define DDD0_REG DDRD
00676 #define DDD1_REG DDRD
00677 #define DDD2_REG DDRD
00678 #define DDD3_REG DDRD
00679 #define DDD4_REG DDRD
00680 #define DDD5_REG DDRD
00681 #define DDD6_REG DDRD
00682 #define DDD7_REG DDRD
00683
00684
00685 #define USITC_REG USICR
00686 #define USICLK_REG USICR
00687 #define USICS0_REG USICR
00688 #define USICS1_REG USICR
00689 #define USIWM0_REG USICR
00690 #define USIWM1_REG USICR
00691 #define USIOIE_REG USICR
00692 #define USISIE_REG USICR
00693
00694
00695 #define UCPOL0_REG UCSR0C
00696 #define UCSZ00_REG UCSR0C
00697 #define UCSZ01_REG UCSR0C
00698 #define USBS0_REG UCSR0C
00699 #define UPM00_REG UCSR0C
00700 #define UPM01_REG UCSR0C
00701 #define UMSEL0_REG UCSR0C
00702
00703
00704 #define TXB80_REG UCSR0B
00705 #define RXB80_REG UCSR0B
00706 #define UCSZ02_REG UCSR0B
00707 #define TXEN0_REG UCSR0B
00708 #define RXEN0_REG UCSR0B
00709 #define UDRIE0_REG UCSR0B
00710 #define TXCIE0_REG UCSR0B
00711 #define RXCIE0_REG UCSR0B
00712
00713
00714 #define SPMEN_REG SPMCSR
00715 #define PGERS_REG SPMCSR
00716 #define PGWRT_REG SPMCSR
00717 #define BLBSET_REG SPMCSR
00718 #define RWWSRE_REG SPMCSR
00719 #define RWWSB_REG SPMCSR
00720 #define SPMIE_REG SPMCSR
00721
00722
00723 #define TCNT1H0_REG TCNT1H
00724 #define TCNT1H1_REG TCNT1H
00725 #define TCNT1H2_REG TCNT1H
00726 #define TCNT1H3_REG TCNT1H
00727 #define TCNT1H4_REG TCNT1H
00728 #define TCNT1H5_REG TCNT1H
00729 #define TCNT1H6_REG TCNT1H
00730 #define TCNT1H7_REG TCNT1H
00731
00732
00733 #define ADCL0_REG ADCL
00734 #define ADCL1_REG ADCL
00735 #define ADCL2_REG ADCL
00736 #define ADCL3_REG ADCL
00737 #define ADCL4_REG ADCL
00738 #define ADCL5_REG ADCL
00739 #define ADCL6_REG ADCL
00740 #define ADCL7_REG ADCL
00741
00742
00743 #define ADCH0_REG ADCH
00744 #define ADCH1_REG ADCH
00745 #define ADCH2_REG ADCH
00746 #define ADCH3_REG ADCH
00747 #define ADCH4_REG ADCH
00748 #define ADCH5_REG ADCH
00749 #define ADCH6_REG ADCH
00750 #define ADCH7_REG ADCH
00751
00752
00753 #define TOIE2_REG TIMSK2
00754 #define OCIE2A_REG TIMSK2
00755
00756
00757 #define INT0_REG EIMSK
00758 #define PCIE0_REG EIMSK
00759 #define PCIE1_REG EIMSK
00760 #define PCIE2_REG EIMSK
00761 #define PCIE3_REG EIMSK
00762
00763
00764 #define TOIE0_REG TIMSK0
00765 #define OCIE0A_REG TIMSK0
00766
00767
00768 #define TOIE1_REG TIMSK1
00769 #define OCIE1A_REG TIMSK1
00770 #define OCIE1B_REG TIMSK1
00771 #define ICIE1_REG TIMSK1
00772
00773
00774 #define PCINT0_REG PCMSK0
00775 #define PCINT1_REG PCMSK0
00776 #define PCINT2_REG PCMSK0
00777 #define PCINT3_REG PCMSK0
00778 #define PCINT4_REG PCMSK0
00779 #define PCINT5_REG PCMSK0
00780 #define PCINT6_REG PCMSK0
00781 #define PCINT7_REG PCMSK0
00782
00783
00784 #define PCINT8_REG PCMSK1
00785 #define PCINT9_REG PCMSK1
00786 #define PCINT10_REG PCMSK1
00787 #define PCINT11_REG PCMSK1
00788 #define PCINT12_REG PCMSK1
00789 #define PCINT13_REG PCMSK1
00790 #define PCINT14_REG PCMSK1
00791 #define PCINT15_REG PCMSK1
00792
00793
00794 #define TCNT1L0_REG TCNT1L
00795 #define TCNT1L1_REG TCNT1L
00796 #define TCNT1L2_REG TCNT1L
00797 #define TCNT1L3_REG TCNT1L
00798 #define TCNT1L4_REG TCNT1L
00799 #define TCNT1L5_REG TCNT1L
00800 #define TCNT1L6_REG TCNT1L
00801 #define TCNT1L7_REG TCNT1L
00802
00803
00804 #define PINB0_REG PINB
00805 #define PINB1_REG PINB
00806 #define PINB2_REG PINB
00807 #define PINB3_REG PINB
00808 #define PINB4_REG PINB
00809 #define PINB5_REG PINB
00810 #define PINB6_REG PINB
00811 #define PINB7_REG PINB
00812
00813
00814 #define INTF0_REG EIFR
00815 #define PCIF0_REG EIFR
00816 #define PCIF1_REG EIFR
00817 #define PCIF2_REG EIFR
00818 #define PCIF3_REG EIFR
00819
00820
00821 #define PING0_REG PING
00822 #define PING1_REG PING
00823 #define PING2_REG PING
00824 #define PING3_REG PING
00825 #define PING4_REG PING
00826 #define PING5_REG PING
00827
00828
00829 #define PINF0_REG PINF
00830 #define PINF1_REG PINF
00831 #define PINF2_REG PINF
00832 #define PINF3_REG PINF
00833 #define PINF4_REG PINF
00834 #define PINF5_REG PINF
00835 #define PINF6_REG PINF
00836 #define PINF7_REG PINF
00837
00838
00839 #define PINE0_REG PINE
00840 #define PINE1_REG PINE
00841 #define PINE2_REG PINE
00842 #define PINE3_REG PINE
00843 #define PINE4_REG PINE
00844 #define PINE5_REG PINE
00845 #define PINE6_REG PINE
00846 #define PINE7_REG PINE
00847
00848
00849 #define PIND0_REG PIND
00850 #define PIND1_REG PIND
00851 #define PIND2_REG PIND
00852 #define PIND3_REG PIND
00853 #define PIND4_REG PIND
00854 #define PIND5_REG PIND
00855 #define PIND6_REG PIND
00856 #define PIND7_REG PIND
00857
00858
00859 #define OCR1AH0_REG OCR1AH
00860 #define OCR1AH1_REG OCR1AH
00861 #define OCR1AH2_REG OCR1AH
00862 #define OCR1AH3_REG OCR1AH
00863 #define OCR1AH4_REG OCR1AH
00864 #define OCR1AH5_REG OCR1AH
00865 #define OCR1AH6_REG OCR1AH
00866 #define OCR1AH7_REG OCR1AH
00867
00868
00869 #define OCR1AL0_REG OCR1AL
00870 #define OCR1AL1_REG OCR1AL
00871 #define OCR1AL2_REG OCR1AL
00872 #define OCR1AL3_REG OCR1AL
00873 #define OCR1AL4_REG OCR1AL
00874 #define OCR1AL5_REG OCR1AL
00875 #define OCR1AL6_REG OCR1AL
00876 #define OCR1AL7_REG OCR1AL
00877
00878
00879 #define SPR0_REG SPCR
00880 #define SPR1_REG SPCR
00881 #define CPHA_REG SPCR
00882 #define CPOL_REG SPCR
00883 #define MSTR_REG SPCR
00884 #define DORD_REG SPCR
00885 #define SPE_REG SPCR
00886 #define SPIE_REG SPCR
00887
00888
00889 #define USIDR0_REG USIDR
00890 #define USIDR1_REG USIDR
00891 #define USIDR2_REG USIDR
00892 #define USIDR3_REG USIDR
00893 #define USIDR4_REG USIDR
00894 #define USIDR5_REG USIDR
00895 #define USIDR6_REG USIDR
00896 #define USIDR7_REG USIDR
00897
00898
00899