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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER0A_AVAILABLE
00088 #define TIMER0B_AVAILABLE
00089 #define TIMER1_AVAILABLE
00090 #define TIMER1A_AVAILABLE
00091 #define TIMER1B_AVAILABLE
00092 #define TIMER2_AVAILABLE
00093 #define TIMER2A_AVAILABLE
00094 #define TIMER2B_AVAILABLE
00095
00096
00097 #define SIG_OVERFLOW0_NUM 0
00098 #define SIG_OVERFLOW1_NUM 1
00099 #define SIG_OVERFLOW2_NUM 2
00100 #define SIG_OVERFLOW_TOTAL_NUM 3
00101
00102
00103 #define SIG_OUTPUT_COMPARE0A_NUM 0
00104 #define SIG_OUTPUT_COMPARE0B_NUM 1
00105 #define SIG_OUTPUT_COMPARE1A_NUM 2
00106 #define SIG_OUTPUT_COMPARE1B_NUM 3
00107 #define SIG_OUTPUT_COMPARE2A_NUM 4
00108 #define SIG_OUTPUT_COMPARE2B_NUM 5
00109 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
00110
00111
00112 #define PWM0A_NUM 0
00113 #define PWM0B_NUM 1
00114 #define PWM1A_NUM 2
00115 #define PWM1B_NUM 3
00116 #define PWM2A_NUM 4
00117 #define PWM2B_NUM 5
00118 #define PWM_TOTAL_NUM 6
00119
00120
00121 #define SIG_INPUT_CAPTURE1_NUM 0
00122 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00123
00124
00125
00126 #define MUX0_REG ADMUX
00127 #define MUX1_REG ADMUX
00128 #define MUX2_REG ADMUX
00129 #define MUX3_REG ADMUX
00130 #define MUX4_REG ADMUX
00131 #define ADLAR_REG ADMUX
00132 #define REFS0_REG ADMUX
00133 #define REFS1_REG ADMUX
00134
00135
00136 #define WDP0_REG WDTCSR
00137 #define WDP1_REG WDTCSR
00138 #define WDP2_REG WDTCSR
00139 #define WDE_REG WDTCSR
00140 #define WDCE_REG WDTCSR
00141 #define WDP3_REG WDTCSR
00142 #define WDIE_REG WDTCSR
00143 #define WDIF_REG WDTCSR
00144
00145
00146 #define EEDR0_REG EEDR
00147 #define EEDR1_REG EEDR
00148 #define EEDR2_REG EEDR
00149 #define EEDR3_REG EEDR
00150 #define EEDR4_REG EEDR
00151 #define EEDR5_REG EEDR
00152 #define EEDR6_REG EEDR
00153 #define EEDR7_REG EEDR
00154
00155
00156 #define ACIS0_REG ACSR
00157 #define ACIS1_REG ACSR
00158 #define ACIC_REG ACSR
00159 #define ACIE_REG ACSR
00160 #define ACI_REG ACSR
00161 #define ACO_REG ACSR
00162 #define ACBG_REG ACSR
00163 #define ACD_REG ACSR
00164
00165
00166 #define RAMPZ0_REG RAMPZ
00167
00168
00169 #define OCR2B_0_REG OCR2B
00170 #define OCR2B_1_REG OCR2B
00171 #define OCR2B_2_REG OCR2B
00172 #define OCR2B_3_REG OCR2B
00173 #define OCR2B_4_REG OCR2B
00174 #define OCR2B_5_REG OCR2B
00175 #define OCR2B_6_REG OCR2B
00176 #define OCR2B_7_REG OCR2B
00177
00178
00179 #define OCR2A_0_REG OCR2A
00180 #define OCR2A_1_REG OCR2A
00181 #define OCR2A_2_REG OCR2A
00182 #define OCR2A_3_REG OCR2A
00183 #define OCR2A_4_REG OCR2A
00184 #define OCR2A_5_REG OCR2A
00185 #define OCR2A_6_REG OCR2A
00186 #define OCR2A_7_REG OCR2A
00187
00188
00189 #define SPDR0_REG SPDR
00190 #define SPDR1_REG SPDR
00191 #define SPDR2_REG SPDR
00192 #define SPDR3_REG SPDR
00193 #define SPDR4_REG SPDR
00194 #define SPDR5_REG SPDR
00195 #define SPDR6_REG SPDR
00196 #define SPDR7_REG SPDR
00197
00198
00199 #define SPI2X_REG SPSR
00200 #define WCOL_REG SPSR
00201 #define SPIF_REG SPSR
00202
00203
00204 #define SP8_REG SPH
00205 #define SP9_REG SPH
00206 #define SP10_REG SPH
00207 #define SP11_REG SPH
00208 #define SP12_REG SPH
00209
00210
00211 #define ICR1L0_REG ICR1L
00212 #define ICR1L1_REG ICR1L
00213 #define ICR1L2_REG ICR1L
00214 #define ICR1L3_REG ICR1L
00215 #define ICR1L4_REG ICR1L
00216 #define ICR1L5_REG ICR1L
00217 #define ICR1L6_REG ICR1L
00218 #define ICR1L7_REG ICR1L
00219
00220
00221 #define PRADC_REG PRR
00222 #define PRUSART0_REG PRR
00223 #define PRSPI_REG PRR
00224 #define PRTIM1_REG PRR
00225 #define PRTIM0_REG PRR
00226 #define PRTIM2_REG PRR
00227 #define PRTWI_REG PRR
00228
00229
00230 #define TWPS0_REG TWSR
00231 #define TWPS1_REG TWSR
00232 #define TWS3_REG TWSR
00233 #define TWS4_REG TWSR
00234 #define TWS5_REG TWSR
00235 #define TWS6_REG TWSR
00236 #define TWS7_REG TWSR
00237
00238
00239 #define MPCM0_REG UCSR0A
00240 #define U2X0_REG UCSR0A
00241 #define UPE0_REG UCSR0A
00242 #define DOR0_REG UCSR0A
00243 #define FE0_REG UCSR0A
00244 #define UDRE0_REG UCSR0A
00245 #define TXC0_REG UCSR0A
00246 #define RXC0_REG UCSR0A
00247
00248
00249 #define PORTD0_REG PORTD
00250 #define PORTD1_REG PORTD
00251 #define PORTD2_REG PORTD
00252 #define PORTD3_REG PORTD
00253 #define PORTD4_REG PORTD
00254 #define PORTD5_REG PORTD
00255 #define PORTD6_REG PORTD
00256 #define PORTD7_REG PORTD
00257
00258
00259 #define TXB80_REG UCSR0B
00260 #define RXB80_REG UCSR0B
00261 #define UCSZ02_REG UCSR0B
00262 #define TXEN0_REG UCSR0B
00263 #define RXEN0_REG UCSR0B
00264 #define UDRIE0_REG UCSR0B
00265 #define TXCIE0_REG UCSR0B
00266 #define RXCIE0_REG UCSR0B
00267
00268
00269 #define TCNT1H0_REG TCNT1H
00270 #define TCNT1H1_REG TCNT1H
00271 #define TCNT1H2_REG TCNT1H
00272 #define TCNT1H3_REG TCNT1H
00273 #define TCNT1H4_REG TCNT1H
00274 #define TCNT1H5_REG TCNT1H
00275 #define TCNT1H6_REG TCNT1H
00276 #define TCNT1H7_REG TCNT1H
00277
00278
00279 #define PORTC0_REG PORTC
00280 #define PORTC1_REG PORTC
00281 #define PORTC2_REG PORTC
00282 #define PORTC3_REG PORTC
00283 #define PORTC4_REG PORTC
00284 #define PORTC5_REG PORTC
00285 #define PORTC6_REG PORTC
00286 #define PORTC7_REG PORTC
00287
00288
00289 #define PORTA0_REG PORTA
00290 #define PORTA1_REG PORTA
00291 #define PORTA2_REG PORTA
00292 #define PORTA3_REG PORTA
00293 #define PORTA4_REG PORTA
00294 #define PORTA5_REG PORTA
00295 #define PORTA6_REG PORTA
00296 #define PORTA7_REG PORTA
00297
00298
00299 #define UDR0_0_REG UDR0
00300 #define UDR0_1_REG UDR0
00301 #define UDR0_2_REG UDR0
00302 #define UDR0_3_REG UDR0
00303 #define UDR0_4_REG UDR0
00304 #define UDR0_5_REG UDR0
00305 #define UDR0_6_REG UDR0
00306 #define UDR0_7_REG UDR0
00307
00308
00309 #define ISC00_REG EICRA
00310 #define ISC01_REG EICRA
00311 #define ISC10_REG EICRA
00312 #define ISC11_REG EICRA
00313 #define ISC20_REG EICRA
00314 #define ISC21_REG EICRA
00315
00316
00317 #define ADC0D_REG DIDR0
00318 #define ADC1D_REG DIDR0
00319 #define ADC2D_REG DIDR0
00320 #define ADC3D_REG DIDR0
00321 #define ADC4D_REG DIDR0
00322 #define ADC5D_REG DIDR0
00323 #define ADC6D_REG DIDR0
00324 #define ADC7D_REG DIDR0
00325
00326
00327 #define AIN0D_REG DIDR1
00328 #define AIN1D_REG DIDR1
00329
00330
00331 #define TCR2BUB_REG ASSR
00332 #define TCR2AUB_REG ASSR
00333 #define OCR2BUB_REG ASSR
00334 #define OCR2AUB_REG ASSR
00335 #define TCN2UB_REG ASSR
00336 #define AS2_REG ASSR
00337 #define EXCLK_REG ASSR
00338
00339
00340 #define CLKPS0_REG CLKPR
00341 #define CLKPS1_REG CLKPR
00342 #define CLKPS2_REG CLKPR
00343 #define CLKPS3_REG CLKPR
00344 #define CLKPCE_REG CLKPR
00345
00346
00347 #define C_REG SREG
00348 #define Z_REG SREG
00349 #define N_REG SREG
00350 #define V_REG SREG
00351 #define S_REG SREG
00352 #define H_REG SREG
00353 #define T_REG SREG
00354 #define I_REG SREG
00355
00356
00357 #define DDB0_REG DDRB
00358 #define DDB1_REG DDRB
00359 #define DDB2_REG DDRB
00360 #define DDB3_REG DDRB
00361 #define DDB4_REG DDRB
00362 #define DDB5_REG DDRB
00363 #define DDB6_REG DDRB
00364 #define DDB7_REG DDRB
00365
00366
00367 #define DDC0_REG DDRC
00368 #define DDC1_REG DDRC
00369 #define DDC2_REG DDRC
00370 #define DDC3_REG DDRC
00371 #define DDC4_REG DDRC
00372 #define DDC5_REG DDRC
00373 #define DDC6_REG DDRC
00374 #define DDC7_REG DDRC
00375
00376
00377 #define DDA0_REG DDRA
00378 #define DDA1_REG DDRA
00379 #define DDA2_REG DDRA
00380 #define DDA3_REG DDRA
00381 #define DDA4_REG DDRA
00382 #define DDA5_REG DDRA
00383 #define DDA6_REG DDRA
00384 #define DDA7_REG DDRA
00385
00386
00387 #define WGM10_REG TCCR1A
00388 #define WGM11_REG TCCR1A
00389 #define COM1B0_REG TCCR1A
00390 #define COM1B1_REG TCCR1A
00391 #define COM1A0_REG TCCR1A
00392 #define COM1A1_REG TCCR1A
00393
00394
00395 #define FOC1B_REG TCCR1C
00396 #define FOC1A_REG TCCR1C
00397
00398
00399 #define CS10_REG TCCR1B
00400 #define CS11_REG TCCR1B
00401 #define CS12_REG TCCR1B
00402 #define WGM12_REG TCCR1B
00403 #define WGM13_REG TCCR1B
00404 #define ICES1_REG TCCR1B
00405 #define ICNC1_REG TCCR1B
00406
00407
00408 #define CAL0_REG OSCCAL
00409 #define CAL1_REG OSCCAL
00410 #define CAL2_REG OSCCAL
00411 #define CAL3_REG OSCCAL
00412 #define CAL4_REG OSCCAL
00413 #define CAL5_REG OSCCAL
00414 #define CAL6_REG OSCCAL
00415 #define CAL7_REG OSCCAL
00416
00417
00418 #define GPIOR10_REG GPIOR1
00419 #define GPIOR11_REG GPIOR1
00420 #define GPIOR12_REG GPIOR1
00421 #define GPIOR13_REG GPIOR1
00422 #define GPIOR14_REG GPIOR1
00423 #define GPIOR15_REG GPIOR1
00424 #define GPIOR16_REG GPIOR1
00425 #define GPIOR17_REG GPIOR1
00426
00427
00428 #define GPIOR00_REG GPIOR0
00429 #define GPIOR01_REG GPIOR0
00430 #define GPIOR02_REG GPIOR0
00431 #define GPIOR03_REG GPIOR0
00432 #define GPIOR04_REG GPIOR0
00433 #define GPIOR05_REG GPIOR0
00434 #define GPIOR06_REG GPIOR0
00435 #define GPIOR07_REG GPIOR0
00436
00437
00438 #define GPIOR20_REG GPIOR2
00439 #define GPIOR21_REG GPIOR2
00440 #define GPIOR22_REG GPIOR2
00441 #define GPIOR23_REG GPIOR2
00442 #define GPIOR24_REG GPIOR2
00443 #define GPIOR25_REG GPIOR2
00444 #define GPIOR26_REG GPIOR2
00445 #define GPIOR27_REG GPIOR2
00446
00447
00448 #define PCIE0_REG PCICR
00449 #define PCIE1_REG PCICR
00450 #define PCIE2_REG PCICR
00451 #define PCIE3_REG PCICR
00452
00453
00454 #define TCNT2_0_REG TCNT2
00455 #define TCNT2_1_REG TCNT2
00456 #define TCNT2_2_REG TCNT2
00457 #define TCNT2_3_REG TCNT2
00458 #define TCNT2_4_REG TCNT2
00459 #define TCNT2_5_REG TCNT2
00460 #define TCNT2_6_REG TCNT2
00461 #define TCNT2_7_REG TCNT2
00462
00463
00464 #define TCNT0_0_REG TCNT0
00465 #define TCNT0_1_REG TCNT0
00466 #define TCNT0_2_REG TCNT0
00467 #define TCNT0_3_REG TCNT0
00468 #define TCNT0_4_REG TCNT0
00469 #define TCNT0_5_REG TCNT0
00470 #define TCNT0_6_REG TCNT0
00471 #define TCNT0_7_REG TCNT0
00472
00473
00474 #define TWGCE_REG TWAR
00475 #define TWA0_REG TWAR
00476 #define TWA1_REG TWAR
00477 #define TWA2_REG TWAR
00478 #define TWA3_REG TWAR
00479 #define TWA4_REG TWAR
00480 #define TWA5_REG TWAR
00481 #define TWA6_REG TWAR
00482
00483
00484 #define CS00_REG TCCR0B
00485 #define CS01_REG TCCR0B
00486 #define CS02_REG TCCR0B
00487 #define WGM02_REG TCCR0B
00488 #define FOC0B_REG TCCR0B
00489 #define FOC0A_REG TCCR0B
00490
00491
00492 #define WGM00_REG TCCR0A
00493 #define WGM01_REG TCCR0A
00494 #define COM0B0_REG TCCR0A
00495 #define COM0B1_REG TCCR0A
00496 #define COM0A0_REG TCCR0A
00497 #define COM0A1_REG TCCR0A
00498
00499
00500 #define TOV2_REG TIFR2
00501 #define OCF2A_REG TIFR2
00502 #define OCF2B_REG TIFR2
00503
00504
00505 #define TOV0_REG TIFR0
00506 #define OCF0A_REG TIFR0
00507 #define OCF0B_REG TIFR0
00508
00509
00510 #define TOV1_REG TIFR1
00511 #define OCF1A_REG TIFR1
00512 #define OCF1B_REG TIFR1
00513 #define ICF1_REG TIFR1
00514
00515
00516 #define PSRSYNC_REG GTCCR
00517 #define TSM_REG GTCCR
00518 #define PSRASY_REG GTCCR
00519
00520
00521 #define TWBR0_REG TWBR
00522 #define TWBR1_REG TWBR
00523 #define TWBR2_REG TWBR
00524 #define TWBR3_REG TWBR
00525 #define TWBR4_REG TWBR
00526 #define TWBR5_REG TWBR
00527 #define TWBR6_REG TWBR
00528 #define TWBR7_REG TWBR
00529
00530
00531 #define ICR1H0_REG ICR1H
00532 #define ICR1H1_REG ICR1H
00533 #define ICR1H2_REG ICR1H
00534 #define ICR1H3_REG ICR1H
00535 #define ICR1H4_REG ICR1H
00536 #define ICR1H5_REG ICR1H
00537 #define ICR1H6_REG ICR1H
00538 #define ICR1H7_REG ICR1H
00539
00540
00541
00542
00543
00544
00545
00546
00547
00548
00549
00550
00551 #define PCIF0_REG PCIFR
00552 #define PCIF1_REG PCIFR
00553 #define PCIF2_REG PCIFR
00554 #define PCIF3_REG PCIFR
00555
00556
00557 #define SP0_REG SPL
00558 #define SP1_REG SPL
00559 #define SP2_REG SPL
00560 #define SP3_REG SPL
00561 #define SP4_REG SPL
00562 #define SP5_REG SPL
00563 #define SP6_REG SPL
00564 #define SP7_REG SPL
00565
00566
00567
00568
00569
00570
00571
00572
00573
00574
00575
00576
00577 #define EERE_REG EECR
00578 #define EEPE_REG EECR
00579 #define EEMPE_REG EECR
00580 #define EERIE_REG EECR
00581 #define EEPM0_REG EECR
00582 #define EEPM1_REG EECR
00583
00584
00585 #define SE_REG SMCR
00586 #define SM0_REG SMCR
00587 #define SM1_REG SMCR
00588 #define SM2_REG SMCR
00589
00590
00591 #define TWIE_REG TWCR
00592 #define TWEN_REG TWCR
00593 #define TWWC_REG TWCR
00594 #define TWSTO_REG TWCR
00595 #define TWSTA_REG TWCR
00596 #define TWEA_REG TWCR
00597 #define TWINT_REG TWCR
00598
00599
00600 #define WGM20_REG TCCR2A
00601 #define WGM21_REG TCCR2A
00602 #define COM2B0_REG TCCR2A
00603 #define COM2B1_REG TCCR2A
00604 #define COM2A0_REG TCCR2A
00605 #define COM2A1_REG TCCR2A
00606
00607
00608 #define CS20_REG TCCR2B
00609 #define CS21_REG TCCR2B
00610 #define CS22_REG TCCR2B
00611 #define WGM22_REG TCCR2B
00612 #define FOC2B_REG TCCR2B
00613 #define FOC2A_REG TCCR2B
00614
00615
00616 #define UBRR8_REG UBRR0H
00617 #define UBRR9_REG UBRR0H
00618 #define UBRR10_REG UBRR0H
00619 #define UBRR11_REG UBRR0H
00620
00621
00622 #define UBRR0_REG UBRR0L
00623 #define UBRR1_REG UBRR0L
00624 #define UBRR2_REG UBRR0L
00625 #define UBRR3_REG UBRR0L
00626 #define UBRR4_REG UBRR0L
00627 #define UBRR5_REG UBRR0L
00628 #define UBRR6_REG UBRR0L
00629 #define UBRR7_REG UBRR0L
00630
00631
00632 #define EEAR8_REG EEARH
00633 #define EEAR9_REG EEARH
00634 #define EEAR10_REG EEARH
00635 #define EEAR11_REG EEARH
00636
00637
00638 #define EEAR0_REG EEARL
00639 #define EEAR1_REG EEARL
00640 #define EEAR2_REG EEARL
00641 #define EEAR3_REG EEARL
00642 #define EEAR4_REG EEARL
00643 #define EEAR5_REG EEARL
00644 #define EEAR6_REG EEARL
00645 #define EEAR7_REG EEARL
00646
00647
00648 #define JTD_REG MCUCR
00649 #define IVCE_REG MCUCR
00650 #define IVSEL_REG MCUCR
00651 #define PUD_REG MCUCR
00652
00653
00654 #define JTRF_REG MCUSR
00655 #define PORF_REG MCUSR
00656 #define EXTRF_REG MCUSR
00657 #define BORF_REG MCUSR
00658 #define WDRF_REG MCUSR
00659
00660
00661 #define OCDR0_REG OCDR
00662 #define OCDR1_REG OCDR
00663 #define OCDR2_REG OCDR
00664 #define OCDR3_REG OCDR
00665 #define OCDR4_REG OCDR
00666 #define OCDR5_REG OCDR
00667 #define OCDR6_REG OCDR
00668 #define OCDR7_REG OCDR
00669
00670
00671 #define PINA0_REG PINA
00672 #define PINA1_REG PINA
00673 #define PINA2_REG PINA
00674 #define PINA3_REG PINA
00675 #define PINA4_REG PINA
00676 #define PINA5_REG PINA
00677 #define PINA6_REG PINA
00678 #define PINA7_REG PINA
00679
00680
00681 #define TWD0_REG TWDR
00682 #define TWD1_REG TWDR
00683 #define TWD2_REG TWDR
00684 #define TWD3_REG TWDR
00685 #define TWD4_REG TWDR
00686 #define TWD5_REG TWDR
00687 #define TWD6_REG TWDR
00688 #define TWD7_REG TWDR
00689
00690
00691
00692
00693
00694
00695
00696
00697
00698
00699
00700
00701 #define ADPS0_REG ADCSRA
00702 #define ADPS1_REG ADCSRA
00703 #define ADPS2_REG ADCSRA
00704 #define ADIE_REG ADCSRA
00705 #define ADIF_REG ADCSRA
00706 #define ADATE_REG ADCSRA
00707 #define ADSC_REG ADCSRA
00708 #define ADEN_REG ADCSRA
00709
00710
00711 #define ACME_REG ADCSRB
00712 #define ADTS0_REG ADCSRB
00713 #define ADTS1_REG ADCSRB
00714 #define ADTS2_REG ADCSRB
00715
00716
00717 #define OCROA_0_REG OCR0A
00718 #define OCROA_1_REG OCR0A
00719 #define OCROA_2_REG OCR0A
00720 #define OCROA_3_REG OCR0A
00721 #define OCROA_4_REG OCR0A
00722 #define OCROA_5_REG OCR0A
00723 #define OCROA_6_REG OCR0A
00724 #define OCROA_7_REG OCR0A
00725
00726
00727 #define OCR0B_0_REG OCR0B
00728 #define OCR0B_1_REG OCR0B
00729 #define OCR0B_2_REG OCR0B
00730 #define OCR0B_3_REG OCR0B
00731 #define OCR0B_4_REG OCR0B
00732 #define OCR0B_5_REG OCR0B
00733 #define OCR0B_6_REG OCR0B
00734 #define OCR0B_7_REG OCR0B
00735
00736
00737 #define TCNT1L0_REG TCNT1L
00738 #define TCNT1L1_REG TCNT1L
00739 #define TCNT1L2_REG TCNT1L
00740 #define TCNT1L3_REG TCNT1L
00741 #define TCNT1L4_REG TCNT1L
00742 #define TCNT1L5_REG TCNT1L
00743 #define TCNT1L6_REG TCNT1L
00744 #define TCNT1L7_REG TCNT1L
00745
00746
00747 #define DDD0_REG DDRD
00748 #define DDD1_REG DDRD
00749 #define DDD2_REG DDRD
00750 #define DDD3_REG DDRD
00751 #define DDD4_REG DDRD
00752 #define DDD5_REG DDRD
00753 #define DDD6_REG DDRD
00754 #define DDD7_REG DDRD
00755
00756
00757 #define UCPOL0_REG UCSR0C
00758 #define UCSZ00_REG UCSR0C
00759 #define UCSZ01_REG UCSR0C
00760 #define USBS0_REG UCSR0C
00761 #define UPM00_REG UCSR0C
00762 #define UPM01_REG UCSR0C
00763 #define UMSEL00_REG UCSR0C
00764 #define UMSEL01_REG UCSR0C
00765
00766
00767 #define SPMEN_REG SPMCSR
00768 #define PGERS_REG SPMCSR
00769 #define PGWRT_REG SPMCSR
00770 #define BLBSET_REG SPMCSR
00771 #define RWWSRE_REG SPMCSR
00772 #define SIGRD_REG SPMCSR
00773 #define RWWSB_REG SPMCSR
00774 #define SPMIE_REG SPMCSR
00775
00776
00777 #define PORTB0_REG PORTB
00778 #define PORTB1_REG PORTB
00779 #define PORTB2_REG PORTB
00780 #define PORTB3_REG PORTB
00781 #define PORTB4_REG PORTB
00782 #define PORTB5_REG PORTB
00783 #define PORTB6_REG PORTB
00784 #define PORTB7_REG PORTB
00785
00786
00787 #define ADCL0_REG ADCL
00788 #define ADCL1_REG ADCL
00789 #define ADCL2_REG ADCL
00790 #define ADCL3_REG ADCL
00791 #define ADCL4_REG ADCL
00792 #define ADCL5_REG ADCL
00793 #define ADCL6_REG ADCL
00794 #define ADCL7_REG ADCL
00795
00796
00797 #define ADCH0_REG ADCH
00798 #define ADCH1_REG ADCH
00799 #define ADCH2_REG ADCH
00800 #define ADCH3_REG ADCH
00801 #define ADCH4_REG ADCH
00802 #define ADCH5_REG ADCH
00803 #define ADCH6_REG ADCH
00804 #define ADCH7_REG ADCH
00805
00806
00807 #define TOIE2_REG TIMSK2
00808 #define OCIE2A_REG TIMSK2
00809 #define OCIE2B_REG TIMSK2
00810
00811
00812 #define INT0_REG EIMSK
00813 #define INT1_REG EIMSK
00814 #define INT2_REG EIMSK
00815
00816
00817 #define TOIE0_REG TIMSK0
00818 #define OCIE0A_REG TIMSK0
00819 #define OCIE0B_REG TIMSK0
00820
00821
00822 #define TOIE1_REG TIMSK1
00823 #define OCIE1A_REG TIMSK1
00824 #define OCIE1B_REG TIMSK1
00825 #define ICIE1_REG TIMSK1
00826
00827
00828 #define PCINT0_REG PCMSK0
00829 #define PCINT1_REG PCMSK0
00830 #define PCINT2_REG PCMSK0
00831 #define PCINT3_REG PCMSK0
00832 #define PCINT4_REG PCMSK0
00833 #define PCINT5_REG PCMSK0
00834 #define PCINT6_REG PCMSK0
00835 #define PCINT7_REG PCMSK0
00836
00837
00838 #define PCINT8_REG PCMSK1
00839 #define PCINT9_REG PCMSK1
00840 #define PCINT10_REG PCMSK1
00841 #define PCINT11_REG PCMSK1
00842 #define PCINT12_REG PCMSK1
00843 #define PCINT13_REG PCMSK1
00844 #define PCINT14_REG PCMSK1
00845 #define PCINT15_REG PCMSK1
00846
00847
00848 #define PCINT16_REG PCMSK2
00849 #define PCINT17_REG PCMSK2
00850 #define PCINT18_REG PCMSK2
00851 #define PCINT19_REG PCMSK2
00852 #define PCINT20_REG PCMSK2
00853 #define PCINT21_REG PCMSK2
00854 #define PCINT22_REG PCMSK2
00855 #define PCINT23_REG PCMSK2
00856
00857
00858 #define PCINT24_REG PCMSK3
00859 #define PCINT25_REG PCMSK3
00860 #define PCINT26_REG PCMSK3
00861 #define PCINT27_REG PCMSK3
00862 #define PCINT28_REG PCMSK3
00863 #define PCINT29_REG PCMSK3
00864 #define PCINT30_REG PCMSK3
00865 #define PCINT31_REG PCMSK3
00866
00867
00868 #define PINC0_REG PINC
00869 #define PINC1_REG PINC
00870 #define PINC2_REG PINC
00871 #define PINC3_REG PINC
00872 #define PINC4_REG PINC
00873 #define PINC5_REG PINC
00874 #define PINC6_REG PINC
00875 #define PINC7_REG PINC
00876
00877
00878 #define PINB0_REG PINB
00879 #define PINB1_REG PINB
00880 #define PINB2_REG PINB
00881 #define PINB3_REG PINB
00882 #define PINB4_REG PINB
00883 #define PINB5_REG PINB
00884 #define PINB6_REG PINB
00885 #define PINB7_REG PINB
00886
00887
00888 #define INTF0_REG EIFR
00889 #define INTF1_REG EIFR
00890 #define INTF2_REG EIFR
00891
00892
00893 #define PIND0_REG PIND
00894 #define PIND1_REG PIND
00895 #define PIND2_REG PIND
00896 #define PIND3_REG PIND
00897 #define PIND4_REG PIND
00898 #define PIND5_REG PIND
00899 #define PIND6_REG PIND
00900 #define PIND7_REG PIND
00901
00902
00903 #define TWAM0_REG TWAMR
00904 #define TWAM1_REG TWAMR
00905 #define TWAM2_REG TWAMR
00906 #define TWAM3_REG TWAMR
00907 #define TWAM4_REG TWAMR
00908 #define TWAM5_REG TWAMR
00909 #define TWAM6_REG TWAMR
00910
00911
00912
00913
00914
00915
00916
00917
00918
00919
00920
00921
00922 #define SPR0_REG SPCR
00923 #define SPR1_REG SPCR
00924 #define CPHA_REG SPCR
00925 #define CPOL_REG SPCR
00926 #define MSTR_REG SPCR
00927 #define DORD_REG SPCR
00928 #define SPE_REG SPCR
00929 #define SPIE_REG SPCR
00930
00931
00932 #define ADC0_PORT PORTA
00933 #define ADC0_BIT 0
00934 #define PCINT0_PORT PORTA
00935 #define PCINT0_BIT 0
00936
00937 #define ADC1_PORT PORTA
00938 #define ADC1_BIT 1
00939 #define PCINT1_PORT PORTA
00940 #define PCINT1_BIT 1
00941
00942 #define ADC2_PORT PORTA
00943 #define ADC2_BIT 2
00944 #define PCINT2_PORT PORTA
00945 #define PCINT2_BIT 2
00946
00947 #define ADC3_PORT PORTA
00948 #define ADC3_BIT 3
00949 #define PCINT3_PORT PORTA
00950 #define PCINT3_BIT 3
00951
00952 #define ADC4_PORT PORTA
00953 #define ADC4_BIT 4
00954 #define PCINT4_PORT PORTA
00955 #define PCINT4_BIT 4
00956
00957 #define ADC5_PORT PORTA
00958 #define ADC5_BIT 5
00959 #define PCINT5_PORT PORTA
00960 #define PCINT5_BIT 5
00961
00962 #define ADC6_PORT PORTA
00963 #define ADC6_BIT 6
00964 #define PCINT6_PORT PORTA
00965 #define PCINT6_BIT 6
00966
00967 #define ADC7_PORT PORTA
00968 #define ADC7_BIT 7
00969 #define PCINT7_PORT PORTA
00970 #define PCINT7_BIT 7
00971
00972 #define XCK_PORT PORTB
00973 #define XCK_BIT 0
00974 #define T0_PORT PORTB
00975 #define T0_BIT 0
00976 #define PCINT9_PORT PORTB
00977 #define PCINT9_BIT 0
00978
00979 #define T1_PORT PORTB
00980 #define T1_BIT 1
00981 #define CLKO_PORT PORTB
00982 #define CLKO_BIT 1
00983 #define PCINT9_PORT PORTB
00984 #define PCINT9_BIT 1
00985
00986 #define AIN0_PORT PORTB
00987 #define AIN0_BIT 2
00988 #define INT2_PORT PORTB
00989 #define INT2_BIT 2
00990 #define PCINT10_PORT PORTB
00991 #define PCINT10_BIT 2
00992
00993 #define AIN1_PORT PORTB
00994 #define AIN1_BIT 3
00995 #define OC0A_PORT PORTB
00996 #define OC0A_BIT 3
00997 #define PCINT11_PORT PORTB
00998 #define PCINT11_BIT 3
00999
01000 #define SS_PORT PORTB
01001 #define SS_BIT 4
01002 #define OC0B_PORT PORTB
01003 #define OC0B_BIT 4
01004 #define PCINT12_PORT PORTB
01005 #define PCINT12_BIT 4
01006
01007 #define MOSI_PORT PORTB
01008 #define MOSI_BIT 5
01009 #define PCINT13_PORT PORTB
01010 #define PCINT13_BIT 5
01011
01012 #define MISO_PORT PORTB
01013 #define MISO_BIT 6
01014 #define PCINT14_PORT PORTB
01015 #define PCINT14_BIT 6
01016
01017 #define SCK_PORT PORTB
01018 #define SCK_BIT 7
01019 #define PCINT15_PORT PORTB
01020 #define PCINT15_BIT 7
01021
01022 #define SCL_PORT PORTC
01023 #define SCL_BIT 0
01024 #define PCINT16_PORT PORTC
01025 #define PCINT16_BIT 0
01026
01027 #define SDA_PORT PORTC
01028 #define SDA_BIT 1
01029 #define PCINT17_PORT PORTC
01030 #define PCINT17_BIT 1
01031
01032 #define TCK_PORT PORTC
01033 #define TCK_BIT 2
01034 #define PCINT18_PORT PORTC
01035 #define PCINT18_BIT 2
01036
01037 #define TMS_PORT PORTC
01038 #define TMS_BIT 3
01039 #define PCINT19_PORT PORTC
01040 #define PCINT19_BIT 3
01041
01042 #define TDO_PORT PORTC
01043 #define TDO_BIT 4
01044 #define PCINT20_PORT PORTC
01045 #define PCINT20_BIT 4
01046
01047 #define TDI_PORT PORTC
01048 #define TDI_BIT 5
01049 #define PCINT21_PORT PORTC
01050 #define PCINT21_BIT 5
01051
01052 #define TOSC1_PORT PORTC
01053 #define TOSC1_BIT 6
01054 #define PCINT22_PORT PORTC
01055 #define PCINT22_BIT 6
01056
01057 #define TOSC2_PORT PORTC
01058 #define TOSC2_BIT 7
01059 #define PCINT23_PORT PORTC
01060 #define PCINT23_BIT 7
01061
01062 #define RXD_PORT PORTD
01063 #define RXD_BIT 0
01064 #define PCINT24_PORT PORTD
01065 #define PCINT24_BIT 0
01066
01067 #define TXD_PORT PORTD
01068 #define TXD_BIT 1
01069 #define PCINT25_PORT PORTD
01070 #define PCINT25_BIT 1
01071
01072 #define INT0_PORT PORTD
01073 #define INT0_BIT 2
01074 #define PCINT26_PORT PORTD
01075 #define PCINT26_BIT 2
01076
01077 #define INT1_PORT PORTD
01078 #define INT1_BIT 3
01079 #define PCINT27_PORT PORTD
01080 #define PCINT27_BIT 3
01081
01082 #define OC1B_PORT PORTD
01083 #define OC1B_BIT 4
01084 #define PCINT28_PORT PORTD
01085 #define PCINT28_BIT 4
01086
01087 #define OC1A_PORT PORTD
01088 #define OC1A_BIT 5
01089 #define PCINT29_PORT PORTD
01090 #define PCINT29_BIT 5
01091
01092 #define ICP_PORT PORTD
01093 #define ICP_BIT 6
01094 #define OC2B_PORT PORTD
01095 #define OC2B_BIT 6
01096 #define PCINT30_PORT PORTD
01097 #define PCINT30_BIT 6
01098
01099 #define OC2A_PORT PORTD
01100 #define OC2A_BIT 7
01101 #define PCINT31_PORT PORTD
01102 #define PCINT31_BIT 7
01103
01104