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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER0A_AVAILABLE
00088 #define TIMER0B_AVAILABLE
00089 #define TIMER1_AVAILABLE
00090 #define TIMER1A_AVAILABLE
00091 #define TIMER1B_AVAILABLE
00092 #define TIMER2_AVAILABLE
00093 #define TIMER2A_AVAILABLE
00094 #define TIMER2B_AVAILABLE
00095
00096
00097 #define SIG_OVERFLOW0_NUM 0
00098 #define SIG_OVERFLOW1_NUM 1
00099 #define SIG_OVERFLOW2_NUM 2
00100 #define SIG_OVERFLOW_TOTAL_NUM 3
00101
00102
00103 #define SIG_OUTPUT_COMPARE0A_NUM 0
00104 #define SIG_OUTPUT_COMPARE0B_NUM 1
00105 #define SIG_OUTPUT_COMPARE1A_NUM 2
00106 #define SIG_OUTPUT_COMPARE1B_NUM 3
00107 #define SIG_OUTPUT_COMPARE2A_NUM 4
00108 #define SIG_OUTPUT_COMPARE2B_NUM 5
00109 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
00110
00111
00112 #define PWM0A_NUM 0
00113 #define PWM0B_NUM 1
00114 #define PWM1A_NUM 2
00115 #define PWM1B_NUM 3
00116 #define PWM2A_NUM 4
00117 #define PWM2B_NUM 5
00118 #define PWM_TOTAL_NUM 6
00119
00120
00121 #define SIG_INPUT_CAPTURE1_NUM 0
00122 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00123
00124
00125
00126 #define MUX0_REG ADMUX
00127 #define MUX1_REG ADMUX
00128 #define MUX2_REG ADMUX
00129 #define MUX3_REG ADMUX
00130 #define ADLAR_REG ADMUX
00131 #define REFS0_REG ADMUX
00132 #define REFS1_REG ADMUX
00133
00134
00135 #define WDP0_REG WDTCSR
00136 #define WDP1_REG WDTCSR
00137 #define WDP2_REG WDTCSR
00138 #define WDE_REG WDTCSR
00139 #define WDCE_REG WDTCSR
00140 #define WDP3_REG WDTCSR
00141 #define WDIE_REG WDTCSR
00142 #define WDIF_REG WDTCSR
00143
00144
00145 #define EEDR0_REG EEDR
00146 #define EEDR1_REG EEDR
00147 #define EEDR2_REG EEDR
00148 #define EEDR3_REG EEDR
00149 #define EEDR4_REG EEDR
00150 #define EEDR5_REG EEDR
00151 #define EEDR6_REG EEDR
00152 #define EEDR7_REG EEDR
00153
00154
00155 #define ACIS0_REG ACSR
00156 #define ACIS1_REG ACSR
00157 #define ACIC_REG ACSR
00158 #define ACIE_REG ACSR
00159 #define ACI_REG ACSR
00160 #define ACO_REG ACSR
00161 #define ACBG_REG ACSR
00162 #define ACD_REG ACSR
00163
00164
00165 #define OCR2B_0_REG OCR2B
00166 #define OCR2B_1_REG OCR2B
00167 #define OCR2B_2_REG OCR2B
00168 #define OCR2B_3_REG OCR2B
00169 #define OCR2B_4_REG OCR2B
00170 #define OCR2B_5_REG OCR2B
00171 #define OCR2B_6_REG OCR2B
00172 #define OCR2B_7_REG OCR2B
00173
00174
00175 #define OCR2A_0_REG OCR2A
00176 #define OCR2A_1_REG OCR2A
00177 #define OCR2A_2_REG OCR2A
00178 #define OCR2A_3_REG OCR2A
00179 #define OCR2A_4_REG OCR2A
00180 #define OCR2A_5_REG OCR2A
00181 #define OCR2A_6_REG OCR2A
00182 #define OCR2A_7_REG OCR2A
00183
00184
00185 #define SPDR0_REG SPDR
00186 #define SPDR1_REG SPDR
00187 #define SPDR2_REG SPDR
00188 #define SPDR3_REG SPDR
00189 #define SPDR4_REG SPDR
00190 #define SPDR5_REG SPDR
00191 #define SPDR6_REG SPDR
00192 #define SPDR7_REG SPDR
00193
00194
00195 #define SPI2X_REG SPSR
00196 #define WCOL_REG SPSR
00197 #define SPIF_REG SPSR
00198
00199
00200 #define SP8_REG SPH
00201 #define SP9_REG SPH
00202
00203
00204 #define ICR1L0_REG ICR1L
00205 #define ICR1L1_REG ICR1L
00206 #define ICR1L2_REG ICR1L
00207 #define ICR1L3_REG ICR1L
00208 #define ICR1L4_REG ICR1L
00209 #define ICR1L5_REG ICR1L
00210 #define ICR1L6_REG ICR1L
00211 #define ICR1L7_REG ICR1L
00212
00213
00214 #define PRADC_REG PRR
00215 #define PRUSART0_REG PRR
00216 #define PRSPI_REG PRR
00217 #define PRTIM1_REG PRR
00218 #define PRTIM0_REG PRR
00219 #define PRTIM2_REG PRR
00220 #define PRTWI_REG PRR
00221
00222
00223 #define MPCM0_REG UCSR0A
00224 #define U2X0_REG UCSR0A
00225 #define UPE0_REG UCSR0A
00226 #define DOR0_REG UCSR0A
00227 #define FE0_REG UCSR0A
00228 #define UDRE0_REG UCSR0A
00229 #define TXC0_REG UCSR0A
00230 #define RXC0_REG UCSR0A
00231
00232
00233 #define PORTD0_REG PORTD
00234 #define PORTD1_REG PORTD
00235 #define PORTD2_REG PORTD
00236 #define PORTD3_REG PORTD
00237 #define PORTD4_REG PORTD
00238 #define PORTD5_REG PORTD
00239 #define PORTD6_REG PORTD
00240 #define PORTD7_REG PORTD
00241
00242
00243 #define TXB80_REG UCSR0B
00244 #define RXB80_REG UCSR0B
00245 #define UCSZ02_REG UCSR0B
00246 #define TXEN0_REG UCSR0B
00247 #define RXEN0_REG UCSR0B
00248 #define UDRIE0_REG UCSR0B
00249 #define TXCIE0_REG UCSR0B
00250 #define RXCIE0_REG UCSR0B
00251
00252
00253 #define PORTB0_REG PORTB
00254 #define PORTB1_REG PORTB
00255 #define PORTB2_REG PORTB
00256 #define PORTB3_REG PORTB
00257 #define PORTB4_REG PORTB
00258 #define PORTB5_REG PORTB
00259 #define PORTB6_REG PORTB
00260 #define PORTB7_REG PORTB
00261
00262
00263 #define PORTC0_REG PORTC
00264 #define PORTC1_REG PORTC
00265 #define PORTC2_REG PORTC
00266 #define PORTC3_REG PORTC
00267 #define PORTC4_REG PORTC
00268 #define PORTC5_REG PORTC
00269 #define PORTC6_REG PORTC
00270
00271
00272 #define UDR0_0_REG UDR0
00273 #define UDR0_1_REG UDR0
00274 #define UDR0_2_REG UDR0
00275 #define UDR0_3_REG UDR0
00276 #define UDR0_4_REG UDR0
00277 #define UDR0_5_REG UDR0
00278 #define UDR0_6_REG UDR0
00279 #define UDR0_7_REG UDR0
00280
00281
00282 #define ISC00_REG EICRA
00283 #define ISC01_REG EICRA
00284 #define ISC10_REG EICRA
00285 #define ISC11_REG EICRA
00286
00287
00288 #define ADC0D_REG DIDR0
00289 #define ADC1D_REG DIDR0
00290 #define ADC2D_REG DIDR0
00291 #define ADC3D_REG DIDR0
00292 #define ADC4D_REG DIDR0
00293 #define ADC5D_REG DIDR0
00294
00295
00296 #define AIN0D_REG DIDR1
00297 #define AIN1D_REG DIDR1
00298
00299
00300 #define TCR2BUB_REG ASSR
00301 #define TCR2AUB_REG ASSR
00302 #define OCR2BUB_REG ASSR
00303 #define OCR2AUB_REG ASSR
00304 #define TCN2UB_REG ASSR
00305 #define AS2_REG ASSR
00306 #define EXCLK_REG ASSR
00307
00308
00309 #define CLKPS0_REG CLKPR
00310 #define CLKPS1_REG CLKPR
00311 #define CLKPS2_REG CLKPR
00312 #define CLKPS3_REG CLKPR
00313 #define CLKPCE_REG CLKPR
00314
00315
00316 #define C_REG SREG
00317 #define Z_REG SREG
00318 #define N_REG SREG
00319 #define V_REG SREG
00320 #define S_REG SREG
00321 #define H_REG SREG
00322 #define T_REG SREG
00323 #define I_REG SREG
00324
00325
00326 #define DDB0_REG DDRB
00327 #define DDB1_REG DDRB
00328 #define DDB2_REG DDRB
00329 #define DDB3_REG DDRB
00330 #define DDB4_REG DDRB
00331 #define DDB5_REG DDRB
00332 #define DDB6_REG DDRB
00333 #define DDB7_REG DDRB
00334
00335
00336 #define DDC0_REG DDRC
00337 #define DDC1_REG DDRC
00338 #define DDC2_REG DDRC
00339 #define DDC3_REG DDRC
00340 #define DDC4_REG DDRC
00341 #define DDC5_REG DDRC
00342 #define DDC6_REG DDRC
00343
00344
00345 #define WGM10_REG TCCR1A
00346 #define WGM11_REG TCCR1A
00347 #define COM1B0_REG TCCR1A
00348 #define COM1B1_REG TCCR1A
00349 #define COM1A0_REG TCCR1A
00350 #define COM1A1_REG TCCR1A
00351
00352
00353 #define FOC1B_REG TCCR1C
00354 #define FOC1A_REG TCCR1C
00355
00356
00357 #define CS10_REG TCCR1B
00358 #define CS11_REG TCCR1B
00359 #define CS12_REG TCCR1B
00360 #define WGM12_REG TCCR1B
00361 #define WGM13_REG TCCR1B
00362 #define ICES1_REG TCCR1B
00363 #define ICNC1_REG TCCR1B
00364
00365
00366 #define CAL0_REG OSCCAL
00367 #define CAL1_REG OSCCAL
00368 #define CAL2_REG OSCCAL
00369 #define CAL3_REG OSCCAL
00370 #define CAL4_REG OSCCAL
00371 #define CAL5_REG OSCCAL
00372 #define CAL6_REG OSCCAL
00373 #define CAL7_REG OSCCAL
00374
00375
00376 #define GPIOR10_REG GPIOR1
00377 #define GPIOR11_REG GPIOR1
00378 #define GPIOR12_REG GPIOR1
00379 #define GPIOR13_REG GPIOR1
00380 #define GPIOR14_REG GPIOR1
00381 #define GPIOR15_REG GPIOR1
00382 #define GPIOR16_REG GPIOR1
00383 #define GPIOR17_REG GPIOR1
00384
00385
00386 #define GPIOR00_REG GPIOR0
00387 #define GPIOR01_REG GPIOR0
00388 #define GPIOR02_REG GPIOR0
00389 #define GPIOR03_REG GPIOR0
00390 #define GPIOR04_REG GPIOR0
00391 #define GPIOR05_REG GPIOR0
00392 #define GPIOR06_REG GPIOR0
00393 #define GPIOR07_REG GPIOR0
00394
00395
00396 #define GPIOR20_REG GPIOR2
00397 #define GPIOR21_REG GPIOR2
00398 #define GPIOR22_REG GPIOR2
00399 #define GPIOR23_REG GPIOR2
00400 #define GPIOR24_REG GPIOR2
00401 #define GPIOR25_REG GPIOR2
00402 #define GPIOR26_REG GPIOR2
00403 #define GPIOR27_REG GPIOR2
00404
00405
00406 #define PCIE0_REG PCICR
00407 #define PCIE1_REG PCICR
00408 #define PCIE2_REG PCICR
00409
00410
00411 #define TCNT2_0_REG TCNT2
00412 #define TCNT2_1_REG TCNT2
00413 #define TCNT2_2_REG TCNT2
00414 #define TCNT2_3_REG TCNT2
00415 #define TCNT2_4_REG TCNT2
00416 #define TCNT2_5_REG TCNT2
00417 #define TCNT2_6_REG TCNT2
00418 #define TCNT2_7_REG TCNT2
00419
00420
00421 #define TCNT0_0_REG TCNT0
00422 #define TCNT0_1_REG TCNT0
00423 #define TCNT0_2_REG TCNT0
00424 #define TCNT0_3_REG TCNT0
00425 #define TCNT0_4_REG TCNT0
00426 #define TCNT0_5_REG TCNT0
00427 #define TCNT0_6_REG TCNT0
00428 #define TCNT0_7_REG TCNT0
00429
00430
00431 #define TWGCE_REG TWAR
00432 #define TWA0_REG TWAR
00433 #define TWA1_REG TWAR
00434 #define TWA2_REG TWAR
00435 #define TWA3_REG TWAR
00436 #define TWA4_REG TWAR
00437 #define TWA5_REG TWAR
00438 #define TWA6_REG TWAR
00439
00440
00441 #define CS00_REG TCCR0B
00442 #define CS01_REG TCCR0B
00443 #define CS02_REG TCCR0B
00444 #define WGM02_REG TCCR0B
00445 #define FOC0B_REG TCCR0B
00446 #define FOC0A_REG TCCR0B
00447
00448
00449 #define WGM00_REG TCCR0A
00450 #define WGM01_REG TCCR0A
00451 #define COM0B0_REG TCCR0A
00452 #define COM0B1_REG TCCR0A
00453 #define COM0A0_REG TCCR0A
00454 #define COM0A1_REG TCCR0A
00455
00456
00457 #define TOV2_REG TIFR2
00458 #define OCF2A_REG TIFR2
00459 #define OCF2B_REG TIFR2
00460
00461
00462 #define TOV0_REG TIFR0
00463 #define OCF0A_REG TIFR0
00464 #define OCF0B_REG TIFR0
00465
00466
00467 #define TOV1_REG TIFR1
00468 #define OCF1A_REG TIFR1
00469 #define OCF1B_REG TIFR1
00470 #define ICF1_REG TIFR1
00471
00472
00473 #define PSRSYNC_REG GTCCR
00474 #define TSM_REG GTCCR
00475 #define PSRASY_REG GTCCR
00476
00477
00478 #define TWBR0_REG TWBR
00479 #define TWBR1_REG TWBR
00480 #define TWBR2_REG TWBR
00481 #define TWBR3_REG TWBR
00482 #define TWBR4_REG TWBR
00483 #define TWBR5_REG TWBR
00484 #define TWBR6_REG TWBR
00485 #define TWBR7_REG TWBR
00486
00487
00488 #define ICR1H0_REG ICR1H
00489 #define ICR1H1_REG ICR1H
00490 #define ICR1H2_REG ICR1H
00491 #define ICR1H3_REG ICR1H
00492 #define ICR1H4_REG ICR1H
00493 #define ICR1H5_REG ICR1H
00494 #define ICR1H6_REG ICR1H
00495 #define ICR1H7_REG ICR1H
00496
00497
00498 #define OCR1BL0_REG OCR1BL
00499 #define OCR1BL1_REG OCR1BL
00500 #define OCR1BL2_REG OCR1BL
00501 #define OCR1BL3_REG OCR1BL
00502 #define OCR1BL4_REG OCR1BL
00503 #define OCR1BL5_REG OCR1BL
00504 #define OCR1BL6_REG OCR1BL
00505 #define OCR1BL7_REG OCR1BL
00506
00507
00508 #define PCIF0_REG PCIFR
00509 #define PCIF1_REG PCIFR
00510 #define PCIF2_REG PCIFR
00511
00512
00513 #define SP0_REG SPL
00514 #define SP1_REG SPL
00515 #define SP2_REG SPL
00516 #define SP3_REG SPL
00517 #define SP4_REG SPL
00518 #define SP5_REG SPL
00519 #define SP6_REG SPL
00520 #define SP7_REG SPL
00521
00522
00523 #define OCR1BH0_REG OCR1BH
00524 #define OCR1BH1_REG OCR1BH
00525 #define OCR1BH2_REG OCR1BH
00526 #define OCR1BH3_REG OCR1BH
00527 #define OCR1BH4_REG OCR1BH
00528 #define OCR1BH5_REG OCR1BH
00529 #define OCR1BH6_REG OCR1BH
00530 #define OCR1BH7_REG OCR1BH
00531
00532
00533 #define EERE_REG EECR
00534 #define EEPE_REG EECR
00535 #define EEMPE_REG EECR
00536 #define EERIE_REG EECR
00537 #define EEPM0_REG EECR
00538 #define EEPM1_REG EECR
00539
00540
00541 #define SE_REG SMCR
00542 #define SM0_REG SMCR
00543 #define SM1_REG SMCR
00544 #define SM2_REG SMCR
00545
00546
00547 #define TWIE_REG TWCR
00548 #define TWEN_REG TWCR
00549 #define TWWC_REG TWCR
00550 #define TWSTO_REG TWCR
00551 #define TWSTA_REG TWCR
00552 #define TWEA_REG TWCR
00553 #define TWINT_REG TWCR
00554
00555
00556 #define WGM20_REG TCCR2A
00557 #define WGM21_REG TCCR2A
00558 #define COM2B0_REG TCCR2A
00559 #define COM2B1_REG TCCR2A
00560 #define COM2A0_REG TCCR2A
00561 #define COM2A1_REG TCCR2A
00562
00563
00564 #define CS20_REG TCCR2B
00565 #define CS21_REG TCCR2B
00566 #define CS22_REG TCCR2B
00567 #define WGM22_REG TCCR2B
00568 #define FOC2B_REG TCCR2B
00569 #define FOC2A_REG TCCR2B
00570
00571
00572 #define UBRR8_REG UBRR0H
00573 #define UBRR9_REG UBRR0H
00574 #define UBRR10_REG UBRR0H
00575 #define UBRR11_REG UBRR0H
00576
00577
00578 #define UBRR0_REG UBRR0L
00579 #define UBRR1_REG UBRR0L
00580 #define UBRR2_REG UBRR0L
00581 #define UBRR3_REG UBRR0L
00582 #define UBRR4_REG UBRR0L
00583 #define UBRR5_REG UBRR0L
00584 #define UBRR6_REG UBRR0L
00585 #define UBRR7_REG UBRR0L
00586
00587
00588 #define TWPS0_REG TWSR
00589 #define TWPS1_REG TWSR
00590 #define TWS3_REG TWSR
00591 #define TWS4_REG TWSR
00592 #define TWS5_REG TWSR
00593 #define TWS6_REG TWSR
00594 #define TWS7_REG TWSR
00595
00596
00597 #define EEAR0_REG EEARL
00598 #define EEAR1_REG EEARL
00599 #define EEAR2_REG EEARL
00600 #define EEAR3_REG EEARL
00601 #define EEAR4_REG EEARL
00602 #define EEAR5_REG EEARL
00603 #define EEAR6_REG EEARL
00604 #define EEAR7_REG EEARL
00605
00606
00607 #define PUD_REG MCUCR
00608
00609
00610 #define PORF_REG MCUSR
00611 #define EXTRF_REG MCUSR
00612 #define BORF_REG MCUSR
00613 #define WDRF_REG MCUSR
00614
00615
00616 #define TWD0_REG TWDR
00617 #define TWD1_REG TWDR
00618 #define TWD2_REG TWDR
00619 #define TWD3_REG TWDR
00620 #define TWD4_REG TWDR
00621 #define TWD5_REG TWDR
00622 #define TWD6_REG TWDR
00623 #define TWD7_REG TWDR
00624
00625
00626 #define OCR1AH0_REG OCR1AH
00627 #define OCR1AH1_REG OCR1AH
00628 #define OCR1AH2_REG OCR1AH
00629 #define OCR1AH3_REG OCR1AH
00630 #define OCR1AH4_REG OCR1AH
00631 #define OCR1AH5_REG OCR1AH
00632 #define OCR1AH6_REG OCR1AH
00633 #define OCR1AH7_REG OCR1AH
00634
00635
00636 #define ADPS0_REG ADCSRA
00637 #define ADPS1_REG ADCSRA
00638 #define ADPS2_REG ADCSRA
00639 #define ADIE_REG ADCSRA
00640 #define ADIF_REG ADCSRA
00641 #define ADATE_REG ADCSRA
00642 #define ADSC_REG ADCSRA
00643 #define ADEN_REG ADCSRA
00644
00645
00646 #define ADTS0_REG ADCSRB
00647 #define ADTS1_REG ADCSRB
00648 #define ADTS2_REG ADCSRB
00649 #define ACME_REG ADCSRB
00650
00651
00652 #define OCROA_0_REG OCR0A
00653 #define OCROA_1_REG OCR0A
00654 #define OCROA_2_REG OCR0A
00655 #define OCROA_3_REG OCR0A
00656 #define OCROA_4_REG OCR0A
00657 #define OCROA_5_REG OCR0A
00658 #define OCROA_6_REG OCR0A
00659 #define OCROA_7_REG OCR0A
00660
00661
00662 #define OCR0B_0_REG OCR0B
00663 #define OCR0B_1_REG OCR0B
00664 #define OCR0B_2_REG OCR0B
00665 #define OCR0B_3_REG OCR0B
00666 #define OCR0B_4_REG OCR0B
00667 #define OCR0B_5_REG OCR0B
00668 #define OCR0B_6_REG OCR0B
00669 #define OCR0B_7_REG OCR0B
00670
00671
00672 #define TCNT1L0_REG TCNT1L
00673 #define TCNT1L1_REG TCNT1L
00674 #define TCNT1L2_REG TCNT1L
00675 #define TCNT1L3_REG TCNT1L
00676 #define TCNT1L4_REG TCNT1L
00677 #define TCNT1L5_REG TCNT1L
00678 #define TCNT1L6_REG TCNT1L
00679 #define TCNT1L7_REG TCNT1L
00680
00681
00682 #define DDD0_REG DDRD
00683 #define DDD1_REG DDRD
00684 #define DDD2_REG DDRD
00685 #define DDD3_REG DDRD
00686 #define DDD4_REG DDRD
00687 #define DDD5_REG DDRD
00688 #define DDD6_REG DDRD
00689 #define DDD7_REG DDRD
00690
00691
00692 #define UCPOL0_REG UCSR0C
00693 #define UCSZ00_REG UCSR0C
00694 #define UCSZ01_REG UCSR0C
00695 #define USBS0_REG UCSR0C
00696 #define UPM00_REG UCSR0C
00697 #define UPM01_REG UCSR0C
00698 #define UMSEL00_REG UCSR0C
00699 #define UMSEL01_REG UCSR0C
00700
00701
00702 #define SELFPRGEN_REG SPMCSR
00703 #define PGERS_REG SPMCSR
00704 #define PGWRT_REG SPMCSR
00705 #define BLBSET_REG SPMCSR
00706 #define RWWSRE_REG SPMCSR
00707 #define RWWSB_REG SPMCSR
00708 #define SPMIE_REG SPMCSR
00709
00710
00711 #define TCNT1H0_REG TCNT1H
00712 #define TCNT1H1_REG TCNT1H
00713 #define TCNT1H2_REG TCNT1H
00714 #define TCNT1H3_REG TCNT1H
00715 #define TCNT1H4_REG TCNT1H
00716 #define TCNT1H5_REG TCNT1H
00717 #define TCNT1H6_REG TCNT1H
00718 #define TCNT1H7_REG TCNT1H
00719
00720
00721 #define ADCL0_REG ADCL
00722 #define ADCL1_REG ADCL
00723 #define ADCL2_REG ADCL
00724 #define ADCL3_REG ADCL
00725 #define ADCL4_REG ADCL
00726 #define ADCL5_REG ADCL
00727 #define ADCL6_REG ADCL
00728 #define ADCL7_REG ADCL
00729
00730
00731 #define ADCH0_REG ADCH
00732 #define ADCH1_REG ADCH
00733 #define ADCH2_REG ADCH
00734 #define ADCH3_REG ADCH
00735 #define ADCH4_REG ADCH
00736 #define ADCH5_REG ADCH
00737 #define ADCH6_REG ADCH
00738 #define ADCH7_REG ADCH
00739
00740
00741 #define TOIE2_REG TIMSK2
00742 #define OCIE2A_REG TIMSK2
00743 #define OCIE2B_REG TIMSK2
00744
00745
00746 #define INT0_REG EIMSK
00747 #define INT1_REG EIMSK
00748
00749
00750 #define TOIE0_REG TIMSK0
00751 #define OCIE0A_REG TIMSK0
00752 #define OCIE0B_REG TIMSK0
00753
00754
00755 #define TOIE1_REG TIMSK1
00756 #define OCIE1A_REG TIMSK1
00757 #define OCIE1B_REG TIMSK1
00758 #define ICIE1_REG TIMSK1
00759
00760
00761 #define PCINT0_REG PCMSK0
00762 #define PCINT1_REG PCMSK0
00763 #define PCINT2_REG PCMSK0
00764 #define PCINT3_REG PCMSK0
00765 #define PCINT4_REG PCMSK0
00766 #define PCINT5_REG PCMSK0
00767 #define PCINT6_REG PCMSK0
00768 #define PCINT7_REG PCMSK0
00769
00770
00771 #define PCINT8_REG PCMSK1
00772 #define PCINT9_REG PCMSK1
00773 #define PCINT10_REG PCMSK1
00774 #define PCINT11_REG PCMSK1
00775 #define PCINT12_REG PCMSK1
00776 #define PCINT13_REG PCMSK1
00777 #define PCINT14_REG PCMSK1
00778
00779
00780 #define PCINT16_REG PCMSK2
00781 #define PCINT17_REG PCMSK2
00782 #define PCINT18_REG PCMSK2
00783 #define PCINT19_REG PCMSK2
00784 #define PCINT20_REG PCMSK2
00785 #define PCINT21_REG PCMSK2
00786 #define PCINT22_REG PCMSK2
00787 #define PCINT23_REG PCMSK2
00788
00789
00790 #define PINC0_REG PINC
00791 #define PINC1_REG PINC
00792 #define PINC2_REG PINC
00793 #define PINC3_REG PINC
00794 #define PINC4_REG PINC
00795 #define PINC5_REG PINC
00796 #define PINC6_REG PINC
00797
00798
00799 #define PINB0_REG PINB
00800 #define PINB1_REG PINB
00801 #define PINB2_REG PINB
00802 #define PINB3_REG PINB
00803 #define PINB4_REG PINB
00804 #define PINB5_REG PINB
00805 #define PINB6_REG PINB
00806 #define PINB7_REG PINB
00807
00808
00809 #define INTF0_REG EIFR
00810 #define INTF1_REG EIFR
00811
00812
00813 #define PIND0_REG PIND
00814 #define PIND1_REG PIND
00815 #define PIND2_REG PIND
00816 #define PIND3_REG PIND
00817 #define PIND4_REG PIND
00818 #define PIND5_REG PIND
00819 #define PIND6_REG PIND
00820 #define PIND7_REG PIND
00821
00822
00823 #define TWAM0_REG TWAMR
00824 #define TWAM1_REG TWAMR
00825 #define TWAM2_REG TWAMR
00826 #define TWAM3_REG TWAMR
00827 #define TWAM4_REG TWAMR
00828 #define TWAM5_REG TWAMR
00829 #define TWAM6_REG TWAMR
00830
00831
00832 #define OCR1AL0_REG OCR1AL
00833 #define OCR1AL1_REG OCR1AL
00834 #define OCR1AL2_REG OCR1AL
00835 #define OCR1AL3_REG OCR1AL
00836 #define OCR1AL4_REG OCR1AL
00837 #define OCR1AL5_REG OCR1AL
00838 #define OCR1AL6_REG OCR1AL
00839 #define OCR1AL7_REG OCR1AL
00840
00841
00842 #define SPR0_REG SPCR
00843 #define SPR1_REG SPCR
00844 #define CPHA_REG SPCR
00845 #define CPOL_REG SPCR
00846 #define MSTR_REG SPCR
00847 #define DORD_REG SPCR
00848 #define SPE_REG SPCR
00849 #define SPIE_REG SPCR
00850
00851
00852 #define ICP1_PORT PORTB
00853 #define ICP1_BIT 0
00854 #define CLKO_PORT PORTB
00855 #define CLKO_BIT 0
00856 #define PCINT0_PORT PORTB
00857 #define PCINT0_BIT 0
00858
00859 #define OC1A_PORT PORTB
00860 #define OC1A_BIT 1
00861 #define PCINT1_PORT PORTB
00862 #define PCINT1_BIT 1
00863
00864 #define SS_PORT PORTB
00865 #define SS_BIT 2
00866 #define OC1B_PORT PORTB
00867 #define OC1B_BIT 2
00868 #define PCINT2_PORT PORTB
00869 #define PCINT2_BIT 2
00870
00871 #define MOSI_PORT PORTB
00872 #define MOSI_BIT 3
00873 #define OC2A_PORT PORTB
00874 #define OC2A_BIT 3
00875 #define PCINT3_PORT PORTB
00876 #define PCINT3_BIT 3
00877
00878 #define MISO_PORT PORTB
00879 #define MISO_BIT 4
00880 #define PCINT4_PORT PORTB
00881 #define PCINT4_BIT 4
00882
00883 #define SCK_PORT PORTB
00884 #define SCK_BIT 5
00885 #define PCINT5_PORT PORTB
00886 #define PCINT5_BIT 5
00887
00888 #define XTAL1_PORT PORTB
00889 #define XTAL1_BIT 6
00890 #define TOSC1_PORT PORTB
00891 #define TOSC1_BIT 6
00892 #define PCINT6_PORT PORTB
00893 #define PCINT6_BIT 6
00894
00895 #define XTAL2_PORT PORTB
00896 #define XTAL2_BIT 7
00897 #define TOSC2_PORT PORTB
00898 #define TOSC2_BIT 7
00899 #define PCINT7_PORT PORTB
00900 #define PCINT7_BIT 7
00901
00902 #define ADC0_PORT PORTC
00903 #define ADC0_BIT 0
00904 #define PCINT8_PORT PORTC
00905 #define PCINT8_BIT 0
00906
00907 #define ADC1_PORT PORTC
00908 #define ADC1_BIT 1
00909 #define PCINT9_PORT PORTC
00910 #define PCINT9_BIT 1
00911
00912 #define ADC2_PORT PORTC
00913 #define ADC2_BIT 2
00914 #define PCINT10_PORT PORTC
00915 #define PCINT10_BIT 2
00916
00917 #define ADC3_PORT PORTC
00918 #define ADC3_BIT 3
00919 #define PCINT11_PORT PORTC
00920 #define PCINT11_BIT 3
00921
00922 #define ADC4_PORT PORTC
00923 #define ADC4_BIT 4
00924 #define SDA_PORT PORTC
00925 #define SDA_BIT 4
00926 #define PCINT12_PORT PORTC
00927 #define PCINT12_BIT 4
00928
00929 #define ADC5_PORT PORTC
00930 #define ADC5_BIT 5
00931 #define SCL_PORT PORTC
00932 #define SCL_BIT 5
00933 #define PCINT13_PORT PORTC
00934 #define PCINT13_BIT 5
00935
00936 #define RESET_PORT PORTC
00937 #define RESET_BIT 6
00938 #define PCINT14_PORT PORTC
00939 #define PCINT14_BIT 6
00940
00941 #define RXD_PORT PORTD
00942 #define RXD_BIT 0
00943 #define PCINT16_PORT PORTD
00944 #define PCINT16_BIT 0
00945
00946 #define TXD_PORT PORTD
00947 #define TXD_BIT 1
00948 #define PCINT17_PORT PORTD
00949 #define PCINT17_BIT 1
00950
00951 #define INT0_PORT PORTD
00952 #define INT0_BIT 2
00953 #define PCINT18_PORT PORTD
00954 #define PCINT18_BIT 2
00955
00956 #define PCINT19_PORT PORTD
00957 #define PCINT19_BIT 3
00958 #define OC2B_PORT PORTD
00959 #define OC2B_BIT 3
00960 #define INT1_PORT PORTD
00961 #define INT1_BIT 3
00962
00963 #define XCK_PORT PORTD
00964 #define XCK_BIT 4
00965 #define T0_PORT PORTD
00966 #define T0_BIT 4
00967 #define PCINT20_PORT PORTD
00968 #define PCINT20_BIT 4
00969
00970 #define T1_PORT PORTD
00971 #define T1_BIT 5
00972 #define OC0B_PORT PORTD
00973 #define OC0B_BIT 5
00974 #define PCINT21_PORT PORTD
00975 #define PCINT21_BIT 5
00976
00977 #define AIN0_PORT PORTD
00978 #define AIN0_BIT 6
00979 #define OC0A_PORT PORTD
00980 #define OC0A_BIT 6
00981 #define PCINT22_PORT PORTD
00982 #define PCINT22_BIT 6
00983
00984 #define AIN1_PORT PORTD
00985 #define AIN1_BIT 7
00986 #define PCINT23_PORT PORTD
00987 #define PCINT23_BIT 7
00988
00989