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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_32 3
00051 #define TIMER1_PRESCALER_DIV_64 4
00052 #define TIMER1_PRESCALER_DIV_128 5
00053 #define TIMER1_PRESCALER_DIV_256 6
00054 #define TIMER1_PRESCALER_DIV_1024 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 32
00060 #define TIMER1_PRESCALER_REG_4 64
00061 #define TIMER1_PRESCALER_REG_5 128
00062 #define TIMER1_PRESCALER_REG_6 256
00063 #define TIMER1_PRESCALER_REG_7 1024
00064
00065
00066
00067
00068
00069 #define SIG_OVERFLOW_TOTAL_NUM 0
00070
00071
00072 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 0
00073
00074
00075 #define PWM_TOTAL_NUM 0
00076
00077
00078 #define SIG_INPUT_CAPTURE_TOTAL_NUM 0
00079
00080
00081
00082 #define CADAC16_REG CADAC2
00083 #define CADAC17_REG CADAC2
00084 #define CADAC18_REG CADAC2
00085 #define CADAC19_REG CADAC2
00086 #define CADAC20_REG CADAC2
00087 #define CADAC21_REG CADAC2
00088 #define CADAC22_REG CADAC2
00089 #define CADAC23_REG CADAC2
00090
00091
00092 #define CADAC24_REG CADAC3
00093 #define CADAC25_REG CADAC3
00094 #define CADAC26_REG CADAC3
00095 #define CADAC27_REG CADAC3
00096 #define CADAC28_REG CADAC3
00097 #define CADAC29_REG CADAC3
00098 #define CADAC30_REG CADAC3
00099 #define CADAC31_REG CADAC3
00100
00101
00102 #define CADAC00_REG CADAC0
00103 #define CADAC01_REG CADAC0
00104 #define CADAC02_REG CADAC0
00105 #define CADAC03_REG CADAC0
00106 #define CADAC04_REG CADAC0
00107 #define CADAC05_REG CADAC0
00108 #define CADAC06_REG CADAC0
00109 #define CADAC07_REG CADAC0
00110
00111
00112 #define CADAC08_REG CADAC1
00113 #define CADAC09_REG CADAC1
00114 #define CADAC10_REG CADAC1
00115 #define CADAC11_REG CADAC1
00116 #define CADAC12_REG CADAC1
00117 #define CADAC13_REG CADAC1
00118 #define CADAC14_REG CADAC1
00119 #define CADAC15_REG CADAC1
00120
00121
00122 #define EERE_REG EECR
00123 #define EEPE_REG EECR
00124 #define EEMPE_REG EECR
00125 #define EERIE_REG EECR
00126 #define EEPM0_REG EECR
00127 #define EEPM1_REG EECR
00128
00129
00130 #define PCIF0_REG PCIFR
00131 #define PCIF1_REG PCIFR
00132
00133
00134 #define WUTP0_REG WUTCSR
00135 #define WUTP1_REG WUTCSR
00136 #define WUTP2_REG WUTCSR
00137 #define WUTE_REG WUTCSR
00138 #define WUTR_REG WUTCSR
00139 #define WUTCF_REG WUTCSR
00140 #define WUTIE_REG WUTCSR
00141 #define WUTIF_REG WUTCSR
00142
00143
00144 #define C_REG SREG
00145 #define Z_REG SREG
00146 #define N_REG SREG
00147 #define V_REG SREG
00148 #define S_REG SREG
00149 #define H_REG SREG
00150 #define T_REG SREG
00151 #define I_REG SREG
00152
00153
00154 #define PCIE0_REG PCICR
00155 #define PCIE1_REG PCICR
00156
00157
00158 #define DDB0_REG DDRB
00159 #define DDB1_REG DDRB
00160 #define DDB2_REG DDRB
00161 #define DDB3_REG DDRB
00162 #define DDB4_REG DDRB
00163 #define DDB5_REG DDRB
00164 #define DDB6_REG DDRB
00165 #define DDB7_REG DDRB
00166
00167
00168 #define CCD_REG BPCR
00169 #define DCD_REG BPCR
00170 #define SCD_REG BPCR
00171 #define DUVD_REG BPCR
00172
00173
00174 #define WDP0_REG WDTCSR
00175 #define WDP1_REG WDTCSR
00176 #define WDP2_REG WDTCSR
00177 #define WDE_REG WDTCSR
00178 #define WDCE_REG WDTCSR
00179 #define WDP3_REG WDTCSR
00180 #define WDIE_REG WDTCSR
00181 #define WDIF_REG WDTCSR
00182
00183
00184 #define EEDR0_REG EEDR
00185 #define EEDR1_REG EEDR
00186 #define EEDR2_REG EEDR
00187 #define EEDR3_REG EEDR
00188 #define EEDR4_REG EEDR
00189 #define EEDR5_REG EEDR
00190 #define EEDR6_REG EEDR
00191 #define EEDR7_REG EEDR
00192
00193
00194 #define TWD0_REG TWDR
00195 #define TWD1_REG TWDR
00196 #define TWD2_REG TWDR
00197 #define TWD3_REG TWDR
00198 #define TWD4_REG TWDR
00199 #define TWD5_REG TWDR
00200 #define TWD6_REG TWDR
00201 #define TWD7_REG TWDR
00202
00203
00204 #define PIND0_REG PIND
00205 #define PIND1_REG PIND
00206
00207
00208 #define PSRSYNC_REG GTCCR
00209 #define TSM_REG GTCCR
00210
00211
00212 #define TWBR0_REG TWBR
00213 #define TWBR1_REG TWBR
00214 #define TWBR2_REG TWBR
00215 #define TWBR3_REG TWBR
00216 #define TWBR4_REG TWBR
00217 #define TWBR5_REG TWBR
00218 #define TWBR6_REG TWBR
00219 #define TWBR7_REG TWBR
00220
00221
00222 #define BGCR0_REG BGCRR
00223 #define BGCR1_REG BGCRR
00224 #define BGCR2_REG BGCRR
00225 #define BGCR3_REG BGCRR
00226 #define BGCR4_REG BGCRR
00227 #define BGCR5_REG BGCRR
00228 #define BGCR6_REG BGCRR
00229 #define BGCR7_REG BGCRR
00230
00231
00232 #define DDA0_REG DDRA
00233 #define DDA1_REG DDRA
00234 #define DDA2_REG DDRA
00235 #define DDA3_REG DDRA
00236 #define DDA4_REG DDRA
00237 #define DDA5_REG DDRA
00238 #define DDA6_REG DDRA
00239 #define DDA7_REG DDRA
00240
00241
00242 #define INT0_REG EIMSK
00243 #define INT1_REG EIMSK
00244 #define INT2_REG EIMSK
00245 #define INT3_REG EIMSK
00246
00247
00248 #define PRVADC_REG PRR0
00249 #define PRTIM0_REG PRR0
00250 #define PRTIM1_REG PRR0
00251 #define PRTWI_REG PRR0
00252
00253
00254 #define PCINT8_REG PCMSK1
00255 #define PCINT9_REG PCMSK1
00256 #define PCINT10_REG PCMSK1
00257 #define PCINT11_REG PCMSK1
00258 #define PCINT12_REG PCMSK1
00259 #define PCINT13_REG PCMSK1
00260 #define PCINT14_REG PCMSK1
00261 #define PCINT15_REG PCMSK1
00262
00263
00264 #define OCR0A0_REG OCR0A
00265 #define OCR0A1_REG OCR0A
00266 #define OCR0A2_REG OCR0A
00267 #define OCR0A3_REG OCR0A
00268 #define OCR0A4_REG OCR0A
00269 #define OCR0A5_REG OCR0A
00270 #define OCR0A6_REG OCR0A
00271 #define OCR0A7_REG OCR0A
00272
00273
00274 #define CCDL0_REG BPOCD
00275 #define CCDL1_REG BPOCD
00276 #define CCDL2_REG BPOCD
00277 #define CCDL3_REG BPOCD
00278 #define DCDL0_REG BPOCD
00279 #define DCDL1_REG BPOCD
00280 #define DCDL2_REG BPOCD
00281 #define DCDL3_REG BPOCD
00282
00283
00284 #define DDD0_REG DDRD
00285 #define DDD1_REG DDRD
00286
00287
00288 #define OCR0B0_REG OCR0B
00289 #define OCR0B1_REG OCR0B
00290 #define OCR0B2_REG OCR0B
00291 #define OCR0B3_REG OCR0B
00292 #define OCR0B4_REG OCR0B
00293 #define OCR0B5_REG OCR0B
00294 #define OCR0B6_REG OCR0B
00295 #define OCR0B7_REG OCR0B
00296
00297
00298 #define SP8_REG SPH
00299 #define SP9_REG SPH
00300 #define SP10_REG SPH
00301 #define SP11_REG SPH
00302 #define SP12_REG SPH
00303 #define SP13_REG SPH
00304 #define SP14_REG SPH
00305 #define SP15_REG SPH
00306
00307
00308 #define ACS_REG CCSR
00309 #define XOE_REG CCSR
00310
00311
00312 #define CADICH0_REG CADICH
00313 #define CADICH1_REG CADICH
00314 #define CADICH2_REG CADICH
00315 #define CADICH3_REG CADICH
00316 #define CADICH4_REG CADICH
00317 #define CADICH5_REG CADICH
00318 #define CADICH6_REG CADICH
00319 #define CADICH7_REG CADICH
00320
00321
00322 #define PFD_REG FCSR
00323 #define CFE_REG FCSR
00324 #define DFE_REG FCSR
00325 #define CPS_REG FCSR
00326 #define PWMOPC_REG FCSR
00327 #define PWMOC_REG FCSR
00328
00329
00330 #define SP0_REG SPL
00331 #define SP1_REG SPL
00332 #define SP2_REG SPL
00333 #define SP3_REG SPL
00334 #define SP4_REG SPL
00335 #define SP5_REG SPL
00336 #define SP6_REG SPL
00337 #define SP7_REG SPL
00338
00339
00340 #define CADICIF_REG CADCSRB
00341 #define CADRCIF_REG CADCSRB
00342 #define CADACIF_REG CADCSRB
00343 #define CADICIE_REG CADCSRB
00344 #define CADRCIE_REG CADCSRB
00345 #define CADACIE_REG CADCSRB
00346
00347
00348 #define CADICL0_REG CADICL
00349 #define CADICL1_REG CADICL
00350 #define CADICL2_REG CADICL
00351 #define CADICL3_REG CADICL
00352 #define CADICL4_REG CADICL
00353 #define CADICL5_REG CADICL
00354 #define CADICL6_REG CADICL
00355 #define CADICL7_REG CADICL
00356
00357
00358 #define SCIE_REG BPIR
00359 #define DOCIE_REG BPIR
00360 #define COCIE_REG BPIR
00361 #define DUVIE_REG BPIR
00362 #define SCIF_REG BPIR
00363 #define DOCIF_REG BPIR
00364 #define COCIF_REG BPIR
00365 #define DUVIF_REG BPIR
00366
00367
00368 #define GPIOR10_REG GPIOR1
00369 #define GPIOR11_REG GPIOR1
00370 #define GPIOR12_REG GPIOR1
00371 #define GPIOR13_REG GPIOR1
00372 #define GPIOR14_REG GPIOR1
00373 #define GPIOR15_REG GPIOR1
00374 #define GPIOR16_REG GPIOR1
00375 #define GPIOR17_REG GPIOR1
00376
00377
00378 #define BPPL_REG BPPLR
00379 #define BPPLE_REG BPPLR
00380
00381
00382 #define CS10_REG TCCR1B
00383 #define CS11_REG TCCR1B
00384 #define CS12_REG TCCR1B
00385 #define CTC1_REG TCCR1B
00386
00387
00388 #define PORF_REG MCUSR
00389 #define EXTRF_REG MCUSR
00390 #define BODRF_REG MCUSR
00391 #define WDRF_REG MCUSR
00392 #define JTRF_REG MCUSR
00393
00394
00395 #define EEAR8_REG EEARH
00396
00397
00398 #define OCPT0_REG CBPTR
00399 #define OCPT1_REG CBPTR
00400 #define OCPT2_REG CBPTR
00401 #define OCPT3_REG CBPTR
00402 #define SCPT0_REG CBPTR
00403 #define SCPT1_REG CBPTR
00404 #define SCPT2_REG CBPTR
00405 #define SCPT3_REG CBPTR
00406
00407
00408 #define SPMEN_REG SPMCSR
00409 #define PGERS_REG SPMCSR
00410 #define PGWRT_REG SPMCSR
00411 #define BLBSET_REG SPMCSR
00412 #define RWWSRE_REG SPMCSR
00413 #define SIGRD_REG SPMCSR
00414 #define RWWSB_REG SPMCSR
00415 #define SPMIE_REG SPMCSR
00416
00417
00418 #define CADSE_REG CADCSRA
00419 #define CADSI0_REG CADCSRA
00420 #define CADSI1_REG CADCSRA
00421 #define CADAS0_REG CADCSRA
00422 #define CADAS1_REG CADCSRA
00423 #define CADUB_REG CADCSRA
00424 #define CADEN_REG CADCSRA
00425
00426
00427 #define DUDL0_REG BPDUV
00428 #define DUDL1_REG BPDUV
00429 #define DUDL2_REG BPDUV
00430 #define DUDL3_REG BPDUV
00431 #define DUVT0_REG BPDUV
00432 #define DUVT1_REG BPDUV
00433
00434
00435 #define CADRDC0_REG CADRDC
00436 #define CADRDC1_REG CADRDC
00437 #define CADRDC2_REG CADRDC
00438 #define CADRDC3_REG CADRDC
00439 #define CADRDC4_REG CADRDC
00440 #define CADRDC5_REG CADRDC
00441 #define CADRDC6_REG CADRDC
00442 #define CADRDC7_REG CADRDC
00443
00444
00445 #define TCNT1L0_REG TCNT1L
00446 #define TCNT1L1_REG TCNT1L
00447 #define TCNT1L2_REG TCNT1L
00448 #define TCNT1L3_REG TCNT1L
00449 #define TCNT1L4_REG TCNT1L
00450 #define TCNT1L5_REG TCNT1L
00451 #define TCNT1L6_REG TCNT1L
00452 #define TCNT1L7_REG TCNT1L
00453
00454
00455 #define PORTB0_REG PORTB
00456 #define PORTB1_REG PORTB
00457 #define PORTB2_REG PORTB
00458 #define PORTB3_REG PORTB
00459 #define PORTB4_REG PORTB
00460 #define PORTB5_REG PORTB
00461 #define PORTB6_REG PORTB
00462 #define PORTB7_REG PORTB
00463
00464
00465 #define PORTD0_REG PORTD
00466 #define PORTD1_REG PORTD
00467
00468
00469 #define SE_REG SMCR
00470 #define SM0_REG SMCR
00471 #define SM1_REG SMCR
00472 #define SM2_REG SMCR
00473
00474
00475 #define TCNT1H0_REG TCNT1H
00476 #define TCNT1H1_REG TCNT1H
00477 #define TCNT1H2_REG TCNT1H
00478 #define TCNT1H3_REG TCNT1H
00479 #define TCNT1H4_REG TCNT1H
00480 #define TCNT1H5_REG TCNT1H
00481 #define TCNT1H6_REG TCNT1H
00482 #define TCNT1H7_REG TCNT1H
00483
00484
00485 #define PORTC0_REG PORTC
00486
00487
00488 #define TWAM0_REG TWAMR
00489 #define TWAM1_REG TWAMR
00490 #define TWAM2_REG TWAMR
00491 #define TWAM3_REG TWAMR
00492 #define TWAM4_REG TWAMR
00493 #define TWAM5_REG TWAMR
00494 #define TWAM6_REG TWAMR
00495
00496
00497 #define PORTA0_REG PORTA
00498 #define PORTA1_REG PORTA
00499 #define PORTA2_REG PORTA
00500 #define PORTA3_REG PORTA
00501 #define PORTA4_REG PORTA
00502 #define PORTA5_REG PORTA
00503 #define PORTA6_REG PORTA
00504 #define PORTA7_REG PORTA
00505
00506
00507 #define TWIE_REG TWCR
00508 #define TWEN_REG TWCR
00509 #define TWWC_REG TWCR
00510 #define TWSTO_REG TWCR
00511 #define TWSTA_REG TWCR
00512 #define TWEA_REG TWCR
00513 #define TWINT_REG TWCR
00514
00515
00516 #define SCDL0_REG BPSCD
00517 #define SCDL1_REG BPSCD
00518 #define SCDL2_REG BPSCD
00519 #define SCDL3_REG BPSCD
00520
00521
00522 #define TCNT00_REG TCNT0
00523 #define TCNT01_REG TCNT0
00524 #define TCNT02_REG TCNT0
00525 #define TCNT03_REG TCNT0
00526 #define TCNT04_REG TCNT0
00527 #define TCNT05_REG TCNT0
00528 #define TCNT06_REG TCNT0
00529 #define TCNT07_REG TCNT0
00530
00531
00532 #define PINA0_REG PINA
00533 #define PINA1_REG PINA
00534 #define PINA2_REG PINA
00535 #define PINA3_REG PINA
00536 #define PINA4_REG PINA
00537 #define PINA5_REG PINA
00538 #define PINA6_REG PINA
00539 #define PINA7_REG PINA
00540
00541
00542 #define OCR1AH0_REG OCR1AH
00543 #define OCR1AH1_REG OCR1AH
00544 #define OCR1AH2_REG OCR1AH
00545 #define OCR1AH3_REG OCR1AH
00546 #define OCR1AH4_REG OCR1AH
00547 #define OCR1AH5_REG OCR1AH
00548 #define OCR1AH6_REG OCR1AH
00549 #define OCR1AH7_REG OCR1AH
00550
00551
00552 #define TWGCE_REG TWAR
00553 #define TWA0_REG TWAR
00554 #define TWA1_REG TWAR
00555 #define TWA2_REG TWAR
00556 #define TWA3_REG TWAR
00557 #define TWA4_REG TWAR
00558 #define TWA5_REG TWAR
00559 #define TWA6_REG TWAR
00560
00561
00562 #define GPIOR00_REG GPIOR0
00563 #define GPIOR01_REG GPIOR0
00564 #define GPIOR02_REG GPIOR0
00565 #define GPIOR03_REG GPIOR0
00566 #define GPIOR04_REG GPIOR0
00567 #define GPIOR05_REG GPIOR0
00568 #define GPIOR06_REG GPIOR0
00569 #define GPIOR07_REG GPIOR0
00570
00571
00572 #define EEAR0_REG EEARL
00573 #define EEAR1_REG EEARL
00574 #define EEAR2_REG EEARL
00575 #define EEAR3_REG EEARL
00576 #define EEAR4_REG EEARL
00577 #define EEAR5_REG EEARL
00578 #define EEAR6_REG EEARL
00579 #define EEAR7_REG EEARL
00580
00581
00582 #define TOIE0_REG TIMSK0
00583 #define OCIE0A_REG TIMSK0
00584 #define OCIE0B_REG TIMSK0
00585
00586
00587 #define TOIE1_REG TIMSK1
00588 #define OCIE1A_REG TIMSK1
00589
00590
00591 #define CS00_REG TCCR0B
00592 #define CS01_REG TCCR0B
00593 #define CS02_REG TCCR0B
00594 #define WGM02_REG TCCR0B
00595 #define FOC0B_REG TCCR0B
00596 #define FOC0A_REG TCCR0B
00597
00598
00599 #define BGCC0_REG BGCCR
00600 #define BGCC1_REG BGCCR
00601 #define BGCC2_REG BGCCR
00602 #define BGCC3_REG BGCCR
00603 #define BGCC4_REG BGCCR
00604 #define BGCC5_REG BGCCR
00605 #define BGD_REG BGCCR
00606
00607
00608 #define VADMUX0_REG VADMUX
00609 #define VADMUX1_REG VADMUX
00610 #define VADMUX2_REG VADMUX
00611 #define VADMUX3_REG VADMUX
00612
00613
00614 #define TWPS0_REG TWSR
00615 #define TWPS1_REG TWSR
00616 #define TWS3_REG TWSR
00617 #define TWS4_REG TWSR
00618 #define TWS5_REG TWSR
00619 #define TWS6_REG TWSR
00620 #define TWS7_REG TWSR
00621
00622
00623 #define VADC8_REG VADCH
00624 #define VADC9_REG VADCH
00625 #define VADC10_REG VADCH
00626 #define VADC11_REG VADCH
00627
00628
00629 #define GPIOR20_REG GPIOR2
00630 #define GPIOR21_REG GPIOR2
00631 #define GPIOR22_REG GPIOR2
00632 #define GPIOR23_REG GPIOR2
00633 #define GPIOR24_REG GPIOR2
00634 #define GPIOR25_REG GPIOR2
00635 #define GPIOR26_REG GPIOR2
00636 #define GPIOR27_REG GPIOR2
00637
00638
00639 #define PCINT0_REG PCMSK0
00640 #define PCINT1_REG PCMSK0
00641 #define PCINT2_REG PCMSK0
00642 #define PCINT3_REG PCMSK0
00643 #define PCINT4_REG PCMSK0
00644 #define PCINT5_REG PCMSK0
00645 #define PCINT6_REG PCMSK0
00646 #define PCINT7_REG PCMSK0
00647
00648
00649 #define VADC0_REG VADCL
00650 #define VADC1_REG VADCL
00651 #define VADC2_REG VADCL
00652 #define VADC3_REG VADCL
00653 #define VADC4_REG VADCL
00654 #define VADC5_REG VADCL
00655 #define VADC6_REG VADCL
00656 #define VADC7_REG VADCL
00657
00658
00659 #define ISC00_REG EICRA
00660 #define ISC01_REG EICRA
00661 #define ISC10_REG EICRA
00662 #define ISC11_REG EICRA
00663 #define ISC20_REG EICRA
00664 #define ISC21_REG EICRA
00665 #define ISC30_REG EICRA
00666 #define ISC31_REG EICRA
00667
00668
00669 #define VADCCIE_REG VADCSR
00670 #define VADCCIF_REG VADCSR
00671 #define VADSC_REG VADCSR
00672 #define VADEN_REG VADCSR
00673
00674
00675 #define FCAL0_REG FOSCCAL
00676 #define FCAL1_REG FOSCCAL
00677 #define FCAL2_REG FOSCCAL
00678 #define FCAL3_REG FOSCCAL
00679 #define FCAL4_REG FOSCCAL
00680 #define FCAL5_REG FOSCCAL
00681 #define FCAL6_REG FOSCCAL
00682 #define FCAL7_REG FOSCCAL
00683
00684
00685 #define VADC0D_REG DIDR0
00686 #define VADC1D_REG DIDR0
00687 #define VADC2D_REG DIDR0
00688 #define VADC3D_REG DIDR0
00689
00690
00691 #define WGM00_REG TCCR0A
00692 #define WGM01_REG TCCR0A
00693 #define COM0B0_REG TCCR0A
00694 #define COM0B1_REG TCCR0A
00695 #define COM0A0_REG TCCR0A
00696 #define COM0A1_REG TCCR0A
00697
00698
00699 #define IVCE_REG MCUCR
00700 #define IVSEL_REG MCUCR
00701 #define PUD_REG MCUCR
00702 #define JTD_REG MCUCR
00703
00704
00705 #define CBE1_REG CBCR
00706 #define CBE2_REG CBCR
00707 #define CBE3_REG CBCR
00708 #define CBE4_REG CBCR
00709
00710
00711 #define TWBCIP_REG TWBCSR
00712 #define TWBDT0_REG TWBCSR
00713 #define TWBDT1_REG TWBCSR
00714 #define TWBCIE_REG TWBCSR
00715 #define TWBCIF_REG TWBCSR
00716
00717
00718 #define OCR1AL0_REG OCR1AL
00719 #define OCR1AL1_REG OCR1AL
00720 #define OCR1AL2_REG OCR1AL
00721 #define OCR1AL3_REG OCR1AL
00722 #define OCR1AL4_REG OCR1AL
00723 #define OCR1AL5_REG OCR1AL
00724 #define OCR1AL6_REG OCR1AL
00725 #define OCR1AL7_REG OCR1AL
00726
00727
00728 #define CADRCC0_REG CADRCC
00729 #define CADRCC1_REG CADRCC
00730 #define CADRCC2_REG CADRCC
00731 #define CADRCC3_REG CADRCC
00732 #define CADRCC4_REG CADRCC
00733 #define CADRCC5_REG CADRCC
00734 #define CADRCC6_REG CADRCC
00735 #define CADRCC7_REG CADRCC
00736
00737
00738 #define PINB0_REG PINB
00739 #define PINB1_REG PINB
00740 #define PINB2_REG PINB
00741 #define PINB3_REG PINB
00742 #define PINB4_REG PINB
00743 #define PINB5_REG PINB
00744 #define PINB6_REG PINB
00745 #define PINB7_REG PINB
00746
00747
00748 #define INTF0_REG EIFR
00749 #define INTF1_REG EIFR
00750 #define INTF2_REG EIFR
00751 #define INTF3_REG EIFR
00752
00753
00754 #define TOV0_REG TIFR0
00755 #define OCF0A_REG TIFR0
00756 #define OCF0B_REG TIFR0
00757
00758
00759 #define TOV1_REG TIFR1
00760 #define OCF1A_REG TIFR1
00761
00762
00763 #define ADC0_PORT PORTA
00764 #define ADC0_BIT 0
00765 #define PCINT0_PORT PORTA
00766 #define PCINT0_BIT 0
00767
00768 #define ADC1_PORT PORTA
00769 #define ADC1_BIT 1
00770 #define PCINT1_PORT PORTA
00771 #define PCINT1_BIT 1
00772
00773 #define ADC2_PORT PORTA
00774 #define ADC2_BIT 2
00775 #define PCINT2_PORT PORTA
00776 #define PCINT2_BIT 2
00777
00778 #define ADC3_PORT PORTA
00779 #define ADC3_BIT 3
00780 #define PCINT3_PORT PORTA
00781 #define PCINT3_BIT 3
00782
00783 #define ADC4_PORT PORTA
00784 #define ADC4_BIT 4
00785 #define INT0_PORT PORTA
00786 #define INT0_BIT 4
00787 #define PCINT4_PORT PORTA
00788 #define PCINT4_BIT 4
00789
00790 #define INT1_PORT PORTA
00791 #define INT1_BIT 5
00792 #define PCINT5_PORT PORTA
00793 #define PCINT5_BIT 5
00794
00795 #define INT2_PORT PORTA
00796 #define INT2_BIT 6
00797 #define PCINT6_PORT PORTA
00798 #define PCINT6_BIT 6
00799
00800 #define INT3_PORT PORTA
00801 #define INT3_BIT 7
00802 #define PCINT7_PORT PORTA
00803 #define PCINT7_BIT 7
00804
00805 #define TDO_PORT PORTB
00806 #define TDO_BIT 0
00807 #define PCINT8_PORT PORTB
00808 #define PCINT8_BIT 0
00809
00810 #define TDI_PORT PORTB
00811 #define TDI_BIT 1
00812 #define PCINT9_PORT PORTB
00813 #define PCINT9_BIT 1
00814
00815 #define TMS_PORT PORTB
00816 #define TMS_BIT 2
00817 #define PCINT10_PORT PORTB
00818 #define PCINT10_BIT 2
00819
00820 #define TCK_PORT PORTB
00821 #define TCK_BIT 3
00822 #define PCINT11_PORT PORTB
00823 #define PCINT11_BIT 3
00824
00825 #define PCINT12_PORT PORTB
00826 #define PCINT12_BIT 4
00827
00828 #define PCINT13_PORT PORTB
00829 #define PCINT13_BIT 5
00830
00831 #define OC0A_PORT PORTB
00832 #define OC0A_BIT 6
00833 #define PCINT14_PORT PORTB
00834 #define PCINT14_BIT 6
00835
00836 #define OC0B_PORT PORTB
00837 #define OC0B_BIT 7
00838 #define PCINT15_PORT PORTB
00839 #define PCINT15_BIT 7
00840
00841
00842 #define T0_PORT PORTD
00843 #define T0_BIT 0
00844
00845
00846
00847
00848
00849
00850