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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER3_PRESCALER_DIV_0 0
00067 #define TIMER3_PRESCALER_DIV_1 1
00068 #define TIMER3_PRESCALER_DIV_8 2
00069 #define TIMER3_PRESCALER_DIV_64 3
00070 #define TIMER3_PRESCALER_DIV_256 4
00071 #define TIMER3_PRESCALER_DIV_1024 5
00072 #define TIMER3_PRESCALER_DIV_FALL 6
00073 #define TIMER3_PRESCALER_DIV_RISE 7
00074
00075 #define TIMER3_PRESCALER_REG_0 0
00076 #define TIMER3_PRESCALER_REG_1 1
00077 #define TIMER3_PRESCALER_REG_2 8
00078 #define TIMER3_PRESCALER_REG_3 64
00079 #define TIMER3_PRESCALER_REG_4 256
00080 #define TIMER3_PRESCALER_REG_5 1024
00081 #define TIMER3_PRESCALER_REG_6 -1
00082 #define TIMER3_PRESCALER_REG_7 -2
00083
00084
00085
00086
00087
00088
00089 #define TIMER0_AVAILABLE
00090 #define TIMER0A_AVAILABLE
00091 #define TIMER0B_AVAILABLE
00092 #define TIMER1_AVAILABLE
00093 #define TIMER1A_AVAILABLE
00094 #define TIMER1B_AVAILABLE
00095 #define TIMER1C_AVAILABLE
00096 #define TIMER3_AVAILABLE
00097 #define TIMER3A_AVAILABLE
00098 #define TIMER3B_AVAILABLE
00099 #define TIMER3C_AVAILABLE
00100 #define TIMER4_AVAILABLE
00101 #define TIMER4A_AVAILABLE
00102 #define TIMER4B_AVAILABLE
00103
00104
00105 #define SIG_OVERFLOW0_NUM 0
00106 #define SIG_OVERFLOW1_NUM 1
00107 #define SIG_OVERFLOW3_NUM 2
00108 #define SIG_OVERFLOW4_NUM 3
00109 #define SIG_OVERFLOW_TOTAL_NUM 4
00110
00111
00112 #define SIG_OUTPUT_COMPARE0A_NUM 0
00113 #define SIG_OUTPUT_COMPARE0B_NUM 1
00114 #define SIG_OUTPUT_COMPARE1A_NUM 2
00115 #define SIG_OUTPUT_COMPARE1B_NUM 3
00116 #define SIG_OUTPUT_COMPARE1C_NUM 4
00117 #define SIG_OUTPUT_COMPARE3A_NUM 5
00118 #define SIG_OUTPUT_COMPARE3B_NUM 6
00119 #define SIG_OUTPUT_COMPARE3C_NUM 7
00120 #define SIG_OUTPUT_COMPARE4_NUM 8
00121 #define SIG_OUTPUT_COMPARE4A_NUM 9
00122 #define SIG_OUTPUT_COMPARE4B_NUM 10
00123 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 11
00124
00125
00126 #define PWM0A_NUM 0
00127 #define PWM0B_NUM 1
00128 #define PWM1A_NUM 2
00129 #define PWM1B_NUM 3
00130 #define PWM1C_NUM 4
00131 #define PWM3A_NUM 5
00132 #define PWM3B_NUM 6
00133 #define PWM3C_NUM 7
00134 #define PWM4_NUM 8
00135 #define PWM4A_NUM 9
00136 #define PWM4B_NUM 10
00137 #define PWM_TOTAL_NUM 11
00138
00139
00140 #define SIG_INPUT_CAPTURE1_NUM 0
00141 #define SIG_INPUT_CAPTURE3_NUM 1
00142 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00143
00144
00145
00146 #define MUX0_REG ADMUX
00147 #define MUX1_REG ADMUX
00148 #define MUX2_REG ADMUX
00149 #define MUX3_REG ADMUX
00150 #define MUX4_REG ADMUX
00151 #define ADLAR_REG ADMUX
00152 #define REFS0_REG ADMUX
00153 #define REFS1_REG ADMUX
00154
00155
00156 #define SUSPE_REG UDIEN
00157 #define SOFE_REG UDIEN
00158 #define EORSTE_REG UDIEN
00159 #define WAKEUPE_REG UDIEN
00160 #define EORSME_REG UDIEN
00161 #define UPRSME_REG UDIEN
00162
00163
00164 #define WDP0_REG WDTCSR
00165 #define WDP1_REG WDTCSR
00166 #define WDP2_REG WDTCSR
00167 #define WDE_REG WDTCSR
00168 #define WDCE_REG WDTCSR
00169 #define WDP3_REG WDTCSR
00170 #define WDIE_REG WDTCSR
00171 #define WDIF_REG WDTCSR
00172
00173
00174 #define EEDR0_REG EEDR
00175 #define EEDR1_REG EEDR
00176 #define EEDR2_REG EEDR
00177 #define EEDR3_REG EEDR
00178 #define EEDR4_REG EEDR
00179 #define EEDR5_REG EEDR
00180 #define EEDR6_REG EEDR
00181 #define EEDR7_REG EEDR
00182
00183
00184 #define OCR0B_0_REG OCR0B
00185 #define OCR0B_1_REG OCR0B
00186 #define OCR0B_2_REG OCR0B
00187 #define OCR0B_3_REG OCR0B
00188 #define OCR0B_4_REG OCR0B
00189 #define OCR0B_5_REG OCR0B
00190 #define OCR0B_6_REG OCR0B
00191 #define OCR0B_7_REG OCR0B
00192
00193
00194 #define SUSPI_REG UDINT
00195 #define SOFI_REG UDINT
00196 #define EORSTI_REG UDINT
00197 #define WAKEUPI_REG UDINT
00198 #define EORSMI_REG UDINT
00199 #define UPRSMI_REG UDINT
00200
00201
00202 #define EPRST0_REG UERST
00203 #define EPRST1_REG UERST
00204 #define EPRST2_REG UERST
00205 #define EPRST3_REG UERST
00206 #define EPRST4_REG UERST
00207 #define EPRST5_REG UERST
00208 #define EPRST6_REG UERST
00209
00210
00211 #define RAMPZ0_REG RAMPZ
00212
00213
00214 #define ALLOC_REG UECFG1X
00215 #define EPBK0_REG UECFG1X
00216 #define EPBK1_REG UECFG1X
00217 #define EPSIZE0_REG UECFG1X
00218 #define EPSIZE1_REG UECFG1X
00219 #define EPSIZE2_REG UECFG1X
00220
00221
00222 #define SPDR0_REG SPDR
00223 #define SPDR1_REG SPDR
00224 #define SPDR2_REG SPDR
00225 #define SPDR3_REG SPDR
00226 #define SPDR4_REG SPDR
00227 #define SPDR5_REG SPDR
00228 #define SPDR6_REG SPDR
00229 #define SPDR7_REG SPDR
00230
00231
00232 #define SPI2X_REG SPSR
00233 #define WCOL_REG SPSR
00234 #define SPIF_REG SPSR
00235
00236
00237 #define SP8_REG SPH
00238 #define SP9_REG SPH
00239 #define SP10_REG SPH
00240 #define SP11_REG SPH
00241 #define SP12_REG SPH
00242 #define SP13_REG SPH
00243 #define SP14_REG SPH
00244 #define SP15_REG SPH
00245
00246
00247 #define ICR1L0_REG ICR1L
00248 #define ICR1L1_REG ICR1L
00249 #define ICR1L2_REG ICR1L
00250 #define ICR1L3_REG ICR1L
00251 #define ICR1L4_REG ICR1L
00252 #define ICR1L5_REG ICR1L
00253 #define ICR1L6_REG ICR1L
00254 #define ICR1L7_REG ICR1L
00255
00256
00257 #define EEAR8_REG EEARH
00258 #define EEAR9_REG EEARH
00259 #define EEAR10_REG EEARH
00260 #define EEAR11_REG EEARH
00261
00262
00263 #define TCNT1L0_REG TCNT1L
00264 #define TCNT1L1_REG TCNT1L
00265 #define TCNT1L2_REG TCNT1L
00266 #define TCNT1L3_REG TCNT1L
00267 #define TCNT1L4_REG TCNT1L
00268 #define TCNT1L5_REG TCNT1L
00269 #define TCNT1L6_REG TCNT1L
00270 #define TCNT1L7_REG TCNT1L
00271
00272
00273 #define PORTD0_REG PORTD
00274 #define PORTD1_REG PORTD
00275 #define PORTD2_REG PORTD
00276 #define PORTD3_REG PORTD
00277 #define PORTD4_REG PORTD
00278 #define PORTD5_REG PORTD
00279 #define PORTD6_REG PORTD
00280 #define PORTD7_REG PORTD
00281
00282
00283 #define PORTE2_REG PORTE
00284 #define PORTE6_REG PORTE
00285
00286
00287 #define TCNT1H0_REG TCNT1H
00288 #define TCNT1H1_REG TCNT1H
00289 #define TCNT1H2_REG TCNT1H
00290 #define TCNT1H3_REG TCNT1H
00291 #define TCNT1H4_REG TCNT1H
00292 #define TCNT1H5_REG TCNT1H
00293 #define TCNT1H6_REG TCNT1H
00294 #define TCNT1H7_REG TCNT1H
00295
00296
00297 #define PORTC6_REG PORTC
00298 #define PORTC7_REG PORTC
00299
00300
00301 #define INT0_REG EIMSK
00302 #define INT1_REG EIMSK
00303 #define INT2_REG EIMSK
00304 #define INT3_REG EIMSK
00305 #define INT4_REG EIMSK
00306 #define INT5_REG EIMSK
00307 #define INT6_REG EIMSK
00308 #define INT7_REG EIMSK
00309
00310
00311 #define UDR1_0_REG UDR1
00312 #define UDR1_1_REG UDR1
00313 #define UDR1_2_REG UDR1
00314 #define UDR1_3_REG UDR1
00315 #define UDR1_4_REG UDR1
00316 #define UDR1_5_REG UDR1
00317 #define UDR1_6_REG UDR1
00318 #define UDR1_7_REG UDR1
00319
00320
00321 #define ISC40_REG EICRB
00322 #define ISC41_REG EICRB
00323 #define ISC50_REG EICRB
00324 #define ISC51_REG EICRB
00325 #define ISC60_REG EICRB
00326 #define ISC61_REG EICRB
00327 #define ISC70_REG EICRB
00328 #define ISC71_REG EICRB
00329
00330
00331 #define DAT0_REG UEDATX
00332 #define DAT1_REG UEDATX
00333 #define DAT2_REG UEDATX
00334 #define DAT3_REG UEDATX
00335 #define DAT4_REG UEDATX
00336 #define DAT5_REG UEDATX
00337 #define DAT6_REG UEDATX
00338 #define DAT7_REG UEDATX
00339
00340
00341 #define ISC00_REG EICRA
00342 #define ISC01_REG EICRA
00343 #define ISC10_REG EICRA
00344 #define ISC11_REG EICRA
00345 #define ISC20_REG EICRA
00346 #define ISC21_REG EICRA
00347 #define ISC30_REG EICRA
00348 #define ISC31_REG EICRA
00349
00350
00351 #define EPDIR_REG UECFG0X
00352 #define EPTYPE0_REG UECFG0X
00353 #define EPTYPE1_REG UECFG0X
00354
00355
00356 #define ADC0D_REG DIDR0
00357 #define ADC1D_REG DIDR0
00358 #define ADC2D_REG DIDR0
00359 #define ADC3D_REG DIDR0
00360 #define ADC4D_REG DIDR0
00361 #define ADC5D_REG DIDR0
00362 #define ADC6D_REG DIDR0
00363 #define ADC7D_REG DIDR0
00364
00365
00366 #define AIN0D_REG DIDR1
00367 #define AIN1D_REG DIDR1
00368
00369
00370 #define ADC8D_REG DIDR2
00371 #define ADC9D_REG DIDR2
00372 #define ADC10D_REG DIDR2
00373 #define ADC11D_REG DIDR2
00374 #define ADC12D_REG DIDR2
00375 #define ADC13D_REG DIDR2
00376
00377
00378 #define DDF0_REG DDRF
00379 #define DDF1_REG DDRF
00380 #define DDF4_REG DDRF
00381 #define DDF5_REG DDRF
00382 #define DDF6_REG DDRF
00383 #define DDF7_REG DDRF
00384
00385
00386 #define EXCKSEL0_REG CLKSEL1
00387 #define EXCKSEL1_REG CLKSEL1
00388 #define EXCKSEL2_REG CLKSEL1
00389 #define EXCKSEL3_REG CLKSEL1
00390 #define RCCKSEL0_REG CLKSEL1
00391 #define RCCKSEL1_REG CLKSEL1
00392 #define RCCKSEL2_REG CLKSEL1
00393 #define RCCKSEL3_REG CLKSEL1
00394
00395
00396 #define CLKS_REG CLKSEL0
00397 #define EXTE_REG CLKSEL0
00398 #define RCE_REG CLKSEL0
00399 #define EXSUT0_REG CLKSEL0
00400 #define EXSUT1_REG CLKSEL0
00401 #define RCSUT0_REG CLKSEL0
00402 #define RCSUT1_REG CLKSEL0
00403
00404
00405 #define CLKPS0_REG CLKPR
00406 #define CLKPS1_REG CLKPR
00407 #define CLKPS2_REG CLKPR
00408 #define CLKPS3_REG CLKPR
00409 #define CLKPCE_REG CLKPR
00410
00411
00412 #define C_REG SREG
00413 #define Z_REG SREG
00414 #define N_REG SREG
00415 #define V_REG SREG
00416 #define S_REG SREG
00417 #define H_REG SREG
00418 #define T_REG SREG
00419 #define I_REG SREG
00420
00421
00422 #define UENUM_0_REG UENUM
00423 #define UENUM_1_REG UENUM
00424 #define UENUM_2_REG UENUM
00425
00426
00427 #define UBRR_0_REG UBRR1L
00428 #define UBRR_1_REG UBRR1L
00429 #define UBRR_2_REG UBRR1L
00430 #define UBRR_3_REG UBRR1L
00431 #define UBRR_4_REG UBRR1L
00432 #define UBRR_5_REG UBRR1L
00433 #define UBRR_6_REG UBRR1L
00434 #define UBRR_7_REG UBRR1L
00435
00436
00437 #define DDC6_REG DDRC
00438 #define DDC7_REG DDRC
00439
00440
00441 #define OCR3AL0_REG OCR3AL
00442 #define OCR3AL1_REG OCR3AL
00443 #define OCR3AL2_REG OCR3AL
00444 #define OCR3AL3_REG OCR3AL
00445 #define OCR3AL4_REG OCR3AL
00446 #define OCR3AL5_REG OCR3AL
00447 #define OCR3AL6_REG OCR3AL
00448 #define OCR3AL7_REG OCR3AL
00449
00450
00451 #define WGM10_REG TCCR1A
00452 #define WGM11_REG TCCR1A
00453 #define COM1C0_REG TCCR1A
00454 #define COM1C1_REG TCCR1A
00455 #define COM1B0_REG TCCR1A
00456 #define COM1B1_REG TCCR1A
00457 #define COM1A0_REG TCCR1A
00458 #define COM1A1_REG TCCR1A
00459
00460
00461 #define OCR3AH0_REG OCR3AH
00462 #define OCR3AH1_REG OCR3AH
00463 #define OCR3AH2_REG OCR3AH
00464 #define OCR3AH3_REG OCR3AH
00465 #define OCR3AH4_REG OCR3AH
00466 #define OCR3AH5_REG OCR3AH
00467 #define OCR3AH6_REG OCR3AH
00468 #define OCR3AH7_REG OCR3AH
00469
00470
00471 #define CS10_REG TCCR1B
00472 #define CS11_REG TCCR1B
00473 #define CS12_REG TCCR1B
00474 #define WGM12_REG TCCR1B
00475 #define WGM13_REG TCCR1B
00476 #define ICES1_REG TCCR1B
00477 #define ICNC1_REG TCCR1B
00478
00479
00480 #define CAL0_REG OSCCAL
00481 #define CAL1_REG OSCCAL
00482 #define CAL2_REG OSCCAL
00483 #define CAL3_REG OSCCAL
00484 #define CAL4_REG OSCCAL
00485 #define CAL5_REG OSCCAL
00486 #define CAL6_REG OSCCAL
00487 #define CAL7_REG OSCCAL
00488
00489
00490 #define DDD0_REG DDRD
00491 #define DDD1_REG DDRD
00492 #define DDD2_REG DDRD
00493 #define DDD3_REG DDRD
00494 #define DDD4_REG DDRD
00495 #define DDD5_REG DDRD
00496 #define DDD6_REG DDRD
00497 #define DDD7_REG DDRD
00498
00499
00500 #define OCR4A0_REG OCR4A
00501 #define OCR4A1_REG OCR4A
00502 #define OCR4A2_REG OCR4A
00503 #define OCR4A3_REG OCR4A
00504 #define OCR4A4_REG OCR4A
00505 #define OCR4A5_REG OCR4A
00506 #define OCR4A6_REG OCR4A
00507 #define OCR4A7_REG OCR4A
00508
00509
00510 #define OCR4C0_REG OCR4C
00511 #define OCR4C1_REG OCR4C
00512 #define OCR4C2_REG OCR4C
00513 #define OCR4C3_REG OCR4C
00514 #define OCR4C4_REG OCR4C
00515 #define OCR4C5_REG OCR4C
00516 #define OCR4C6_REG OCR4C
00517 #define OCR4C7_REG OCR4C
00518
00519
00520 #define OCR4B0_REG OCR4B
00521 #define OCR4B1_REG OCR4B
00522 #define OCR4B2_REG OCR4B
00523 #define OCR4B3_REG OCR4B
00524 #define OCR4B4_REG OCR4B
00525 #define OCR4B5_REG OCR4B
00526 #define OCR4B6_REG OCR4B
00527 #define OCR4B7_REG OCR4B
00528
00529
00530 #define OCR4D0_REG OCR4D
00531 #define OCR4D1_REG OCR4D
00532 #define OCR4D2_REG OCR4D
00533 #define OCR4D3_REG OCR4D
00534 #define OCR4D4_REG OCR4D
00535 #define OCR4D5_REG OCR4D
00536 #define OCR4D6_REG OCR4D
00537 #define OCR4D7_REG OCR4D
00538
00539
00540 #define GPIOR10_REG GPIOR1
00541 #define GPIOR11_REG GPIOR1
00542 #define GPIOR12_REG GPIOR1
00543 #define GPIOR13_REG GPIOR1
00544 #define GPIOR14_REG GPIOR1
00545 #define GPIOR15_REG GPIOR1
00546 #define GPIOR16_REG GPIOR1
00547 #define GPIOR17_REG GPIOR1
00548
00549
00550 #define GPIOR00_REG GPIOR0
00551 #define GPIOR01_REG GPIOR0
00552 #define GPIOR02_REG GPIOR0
00553 #define GPIOR03_REG GPIOR0
00554 #define GPIOR04_REG GPIOR0
00555 #define GPIOR05_REG GPIOR0
00556 #define GPIOR06_REG GPIOR0
00557 #define GPIOR07_REG GPIOR0
00558
00559
00560 #define GPIOR20_REG GPIOR2
00561 #define GPIOR21_REG GPIOR2
00562 #define GPIOR22_REG GPIOR2
00563 #define GPIOR23_REG GPIOR2
00564 #define GPIOR24_REG GPIOR2
00565 #define GPIOR25_REG GPIOR2
00566 #define GPIOR26_REG GPIOR2
00567 #define GPIOR27_REG GPIOR2
00568
00569
00570 #define RCFREQ_REG RCCTRL
00571
00572
00573 #define DETACH_REG UDCON
00574 #define RMWKUP_REG UDCON
00575 #define LSM_REG UDCON
00576 #define RSTCPU_REG UDCON
00577
00578
00579 #define PCIE0_REG PCICR
00580
00581
00582 #define VBUSTI_REG USBINT
00583
00584
00585 #define TCNT0_0_REG TCNT0
00586 #define TCNT0_1_REG TCNT0
00587 #define TCNT0_2_REG TCNT0
00588 #define TCNT0_3_REG TCNT0
00589 #define TCNT0_4_REG TCNT0
00590 #define TCNT0_5_REG TCNT0
00591 #define TCNT0_6_REG TCNT0
00592 #define TCNT0_7_REG TCNT0
00593
00594
00595 #define TC40_REG TCNT4
00596 #define TC41_REG TCNT4
00597 #define TC42_REG TCNT4
00598 #define TC43_REG TCNT4
00599 #define TC44_REG TCNT4
00600 #define TC45_REG TCNT4
00601 #define TC46_REG TCNT4
00602 #define TC47_REG TCNT4
00603
00604
00605 #define TC48_REG TC4H
00606 #define TC49_REG TC4H
00607 #define TC410_REG TC4H
00608
00609
00610 #define UVREGE_REG UHWCON
00611
00612
00613 #define CS00_REG TCCR0B
00614 #define CS01_REG TCCR0B
00615 #define CS02_REG TCCR0B
00616 #define WGM02_REG TCCR0B
00617 #define FOC0B_REG TCCR0B
00618 #define FOC0A_REG TCCR0B
00619
00620
00621 #define FNCERR_REG UDMFN
00622
00623
00624 #define WGM00_REG TCCR0A
00625 #define WGM01_REG TCCR0A
00626 #define COM0B0_REG TCCR0A
00627 #define COM0B1_REG TCCR0A
00628 #define COM0A0_REG TCCR0A
00629 #define COM0A1_REG TCCR0A
00630
00631
00632 #define TOV4_REG TIFR4
00633 #define OCF4B_REG TIFR4
00634 #define OCF4A_REG TIFR4
00635 #define OCF4D_REG TIFR4
00636
00637
00638 #define TOV3_REG TIFR3
00639 #define OCF3A_REG TIFR3
00640 #define OCF3B_REG TIFR3
00641 #define OCF3C_REG TIFR3
00642 #define ICF3_REG TIFR3
00643
00644
00645 #define SPR0_REG SPCR
00646 #define SPR1_REG SPCR
00647 #define CPHA_REG SPCR
00648 #define CPOL_REG SPCR
00649 #define MSTR_REG SPCR
00650 #define DORD_REG SPCR
00651 #define SPE_REG SPCR
00652 #define SPIE_REG SPCR
00653
00654
00655 #define TOV1_REG TIFR1
00656 #define OCF1A_REG TIFR1
00657 #define OCF1B_REG TIFR1
00658 #define OCF1C_REG TIFR1
00659 #define ICF1_REG TIFR1
00660
00661
00662 #define BYCT0_REG UEBCLX
00663 #define BYCT1_REG UEBCLX
00664 #define BYCT2_REG UEBCLX
00665 #define BYCT3_REG UEBCLX
00666 #define BYCT4_REG UEBCLX
00667 #define BYCT5_REG UEBCLX
00668 #define BYCT6_REG UEBCLX
00669 #define BYCT7_REG UEBCLX
00670
00671
00672 #define OCR3CH0_REG OCR3CH
00673 #define OCR3CH1_REG OCR3CH
00674 #define OCR3CH2_REG OCR3CH
00675 #define OCR3CH3_REG OCR3CH
00676 #define OCR3CH4_REG OCR3CH
00677 #define OCR3CH5_REG OCR3CH
00678 #define OCR3CH6_REG OCR3CH
00679 #define OCR3CH7_REG OCR3CH
00680
00681
00682 #define CURRBK0_REG UESTA1X
00683 #define CURRBK1_REG UESTA1X
00684 #define CTRLDIR_REG UESTA1X
00685
00686
00687 #define OCR3CL0_REG OCR3CL
00688 #define OCR3CL1_REG OCR3CL
00689 #define OCR3CL2_REG OCR3CL
00690 #define OCR3CL3_REG OCR3CL
00691 #define OCR3CL4_REG OCR3CL
00692 #define OCR3CL5_REG OCR3CL
00693 #define OCR3CL6_REG OCR3CL
00694 #define OCR3CL7_REG OCR3CL
00695
00696
00697 #define PSRSYNC_REG GTCCR
00698 #define TSM_REG GTCCR
00699
00700
00701 #define ICR1H0_REG ICR1H
00702 #define ICR1H1_REG ICR1H
00703 #define ICR1H2_REG ICR1H
00704 #define ICR1H3_REG ICR1H
00705 #define ICR1H4_REG ICR1H
00706 #define ICR1H5_REG ICR1H
00707 #define ICR1H6_REG ICR1H
00708 #define ICR1H7_REG ICR1H
00709
00710
00711 #define FOC3C_REG TCCR3C
00712 #define FOC3B_REG TCCR3C
00713 #define FOC3A_REG TCCR3C
00714
00715
00716 #define CS30_REG TCCR3B
00717 #define CS31_REG TCCR3B
00718 #define CS32_REG TCCR3B
00719 #define WGM32_REG TCCR3B
00720 #define WGM33_REG TCCR3B
00721 #define ICES3_REG TCCR3B
00722 #define ICNC3_REG TCCR3B
00723
00724
00725 #define WGM30_REG TCCR3A
00726 #define WGM31_REG TCCR3A
00727 #define COM3C0_REG TCCR3A
00728 #define COM3C1_REG TCCR3A
00729 #define COM3B0_REG TCCR3A
00730 #define COM3B1_REG TCCR3A
00731 #define COM3A0_REG TCCR3A
00732 #define COM3A1_REG TCCR3A
00733
00734
00735 #define TXINI_REG UEINTX
00736 #define STALLEDI_REG UEINTX
00737 #define RXOUTI_REG UEINTX
00738 #define RXSTPI_REG UEINTX
00739 #define NAKOUTI_REG UEINTX
00740 #define RWAL_REG UEINTX
00741 #define NAKINI_REG UEINTX
00742 #define FIFOCON_REG UEINTX
00743
00744
00745 #define OCR1BL0_REG OCR1BL
00746 #define OCR1BL1_REG OCR1BL
00747 #define OCR1BL2_REG OCR1BL
00748 #define OCR1BL3_REG OCR1BL
00749 #define OCR1BL4_REG OCR1BL
00750 #define OCR1BL5_REG OCR1BL
00751 #define OCR1BL6_REG OCR1BL
00752 #define OCR1BL7_REG OCR1BL
00753
00754
00755 #define TCNT3H0_REG TCNT3H
00756 #define TCNT3H1_REG TCNT3H
00757 #define TCNT3H2_REG TCNT3H
00758 #define TCNT3H3_REG TCNT3H
00759 #define TCNT3H4_REG TCNT3H
00760 #define TCNT3H5_REG TCNT3H
00761 #define TCNT3H6_REG TCNT3H
00762 #define TCNT3H7_REG TCNT3H
00763
00764
00765 #define OCR1BH0_REG OCR1BH
00766 #define OCR1BH1_REG OCR1BH
00767 #define OCR1BH2_REG OCR1BH
00768 #define OCR1BH3_REG OCR1BH
00769 #define OCR1BH4_REG OCR1BH
00770 #define OCR1BH5_REG OCR1BH
00771 #define OCR1BH6_REG OCR1BH
00772 #define OCR1BH7_REG OCR1BH
00773
00774
00775 #define TCNT3L0_REG TCNT3L
00776 #define TCNT3L1_REG TCNT3L
00777 #define TCNT3L2_REG TCNT3L
00778 #define TCNT3L3_REG TCNT3L
00779 #define TCNT3L4_REG TCNT3L
00780 #define TCNT3L5_REG TCNT3L
00781 #define TCNT3L6_REG TCNT3L
00782 #define TCNT3L7_REG TCNT3L
00783
00784
00785 #define SP0_REG SPL
00786 #define SP1_REG SPL
00787 #define SP2_REG SPL
00788 #define SP3_REG SPL
00789 #define SP4_REG SPL
00790 #define SP5_REG SPL
00791 #define SP6_REG SPL
00792 #define SP7_REG SPL
00793
00794
00795 #define VBUSTE_REG USBCON
00796 #define OTGPADE_REG USBCON
00797 #define FRZCLK_REG USBCON
00798 #define USBE_REG USBCON
00799
00800
00801 #define JTRF_REG MCUSR
00802 #define PORF_REG MCUSR
00803 #define EXTRF_REG MCUSR
00804 #define BORF_REG MCUSR
00805 #define WDRF_REG MCUSR
00806
00807
00808 #define EERE_REG EECR
00809 #define EEPE_REG EECR
00810 #define EEMPE_REG EECR
00811 #define EERIE_REG EECR
00812 #define EEPM0_REG EECR
00813 #define EEPM1_REG EECR
00814
00815
00816 #define SE_REG SMCR
00817 #define SM0_REG SMCR
00818 #define SM1_REG SMCR
00819 #define SM2_REG SMCR
00820
00821
00822 #define PCIF0_REG PCIFR
00823
00824
00825 #define EPEN_REG UECONX
00826 #define RSTDT_REG UECONX
00827 #define STALLRQC_REG UECONX
00828 #define STALLRQ_REG UECONX
00829
00830
00831 #define PDIV0_REG PLLFRQ
00832 #define PDIV1_REG PLLFRQ
00833 #define PDIV2_REG PLLFRQ
00834 #define PDIV3_REG PLLFRQ
00835 #define PLLTM0_REG PLLFRQ
00836 #define PLLTM1_REG PLLFRQ
00837 #define PLLUSB_REG PLLFRQ
00838 #define PINMUX_REG PLLFRQ
00839
00840
00841 #define EPINT0_REG UEINT
00842 #define EPINT1_REG UEINT
00843 #define EPINT2_REG UEINT
00844 #define EPINT3_REG UEINT
00845 #define EPINT4_REG UEINT
00846 #define EPINT5_REG UEINT
00847 #define EPINT6_REG UEINT
00848
00849
00850 #define EEAR0_REG EEARL
00851 #define EEAR1_REG EEARL
00852 #define EEAR2_REG EEARL
00853 #define EEAR3_REG EEARL
00854 #define EEAR4_REG EEARL
00855 #define EEAR5_REG EEARL
00856 #define EEAR6_REG EEARL
00857 #define EEAR7_REG EEARL
00858
00859
00860 #define JTD_REG MCUCR
00861 #define IVCE_REG MCUCR
00862 #define IVSEL_REG MCUCR
00863 #define PUD_REG MCUCR
00864
00865
00866 #define OCR1CL0_REG OCR1CL
00867 #define OCR1CL1_REG OCR1CL
00868 #define OCR1CL2_REG OCR1CL
00869 #define OCR1CL3_REG OCR1CL
00870 #define OCR1CL4_REG OCR1CL
00871 #define OCR1CL5_REG OCR1CL
00872 #define OCR1CL6_REG OCR1CL
00873 #define OCR1CL7_REG OCR1CL
00874
00875
00876 #define OCR1CH0_REG OCR1CH
00877 #define OCR1CH1_REG OCR1CH
00878 #define OCR1CH2_REG OCR1CH
00879 #define OCR1CH3_REG OCR1CH
00880 #define OCR1CH4_REG OCR1CH
00881 #define OCR1CH5_REG OCR1CH
00882 #define OCR1CH6_REG OCR1CH
00883 #define OCR1CH7_REG OCR1CH
00884
00885
00886 #define OCDR0_REG OCDR
00887 #define OCDR1_REG OCDR
00888 #define OCDR2_REG OCDR
00889 #define OCDR3_REG OCDR
00890 #define OCDR4_REG OCDR
00891 #define OCDR5_REG OCDR
00892 #define OCDR6_REG OCDR
00893 #define OCDR7_REG OCDR
00894
00895
00896 #define VBUS_REG USBSTA
00897 #define SPEED_REG USBSTA
00898
00899
00900 #define TXINE_REG UEIENX
00901 #define STALLEDE_REG UEIENX
00902 #define RXOUTE_REG UEIENX
00903 #define RXSTPE_REG UEIENX
00904 #define NAKOUTE_REG UEIENX
00905 #define NAKINE_REG UEIENX
00906 #define FLERRE_REG UEIENX
00907
00908
00909 #define TXB81_REG UCSR1B
00910 #define RXB81_REG UCSR1B
00911 #define UCSZ12_REG UCSR1B
00912 #define TXEN1_REG UCSR1B
00913 #define RXEN1_REG UCSR1B
00914 #define UDRIE1_REG UCSR1B
00915 #define TXCIE1_REG UCSR1B
00916 #define RXCIE1_REG UCSR1B
00917
00918
00919 #define UCPOL1_REG UCSR1C
00920 #define UCSZ10_REG UCSR1C
00921 #define UCSZ11_REG UCSR1C
00922 #define USBS1_REG UCSR1C
00923 #define UPM10_REG UCSR1C
00924 #define UPM11_REG UCSR1C
00925 #define UMSEL10_REG UCSR1C
00926 #define UMSEL11_REG UCSR1C
00927
00928
00929 #define MPCM1_REG UCSR1A
00930 #define U2X1_REG UCSR1A
00931 #define UPE1_REG UCSR1A
00932 #define DOR1_REG UCSR1A
00933 #define FE1_REG UCSR1A
00934 #define UDRE1_REG UCSR1A
00935 #define TXC1_REG UCSR1A
00936 #define RXC1_REG UCSR1A
00937
00938
00939 #define DDB0_REG DDRB
00940 #define DDB1_REG DDRB
00941 #define DDB2_REG DDRB
00942 #define DDB3_REG DDRB
00943 #define DDB4_REG DDRB
00944 #define DDB5_REG DDRB
00945 #define DDB6_REG DDRB
00946 #define DDB7_REG DDRB
00947
00948
00949 #define EIND0_REG EIND
00950
00951
00952 #define FNUM0_REG UDFNUML
00953 #define FNUM1_REG UDFNUML
00954 #define FNUM2_REG UDFNUML
00955 #define FNUM3_REG UDFNUML
00956 #define FNUM4_REG UDFNUML
00957 #define FNUM5_REG UDFNUML
00958 #define FNUM6_REG UDFNUML
00959 #define FNUM7_REG UDFNUML
00960
00961
00962 #define FNUM8_REG UDFNUMH
00963 #define FNUM9_REG UDFNUMH
00964 #define FNUM10_REG UDFNUMH
00965
00966
00967 #define ADPS0_REG ADCSRA
00968 #define ADPS1_REG ADCSRA
00969 #define ADPS2_REG ADCSRA
00970 #define ADIE_REG ADCSRA
00971 #define ADIF_REG ADCSRA
00972 #define ADATE_REG ADCSRA
00973 #define ADSC_REG ADCSRA
00974 #define ADEN_REG ADCSRA
00975
00976
00977 #define ADTS0_REG ADCSRB
00978 #define ADTS1_REG ADCSRB
00979 #define ADTS2_REG ADCSRB
00980 #define ADTS3_REG ADCSRB
00981 #define MUX5_REG ADCSRB
00982 #define ADHSM_REG ADCSRB
00983 #define ACME_REG ADCSRB
00984
00985
00986 #define PRADC_REG PRR0
00987 #define PRUSART0_REG PRR0
00988 #define PRSPI_REG PRR0
00989 #define PRTIM1_REG PRR0
00990 #define PRTIM0_REG PRR0
00991 #define PRTIM2_REG PRR0
00992 #define PRTWI_REG PRR0
00993
00994
00995 #define UBRR_8_REG UBRR1H
00996 #define UBRR_9_REG UBRR1H
00997 #define UBRR_10_REG UBRR1H
00998 #define UBRR_11_REG UBRR1H
00999
01000
01001 #define OCROA_0_REG OCR0A
01002 #define OCROA_1_REG OCR0A
01003 #define OCROA_2_REG OCR0A
01004 #define OCROA_3_REG OCR0A
01005 #define OCROA_4_REG OCR0A
01006 #define OCROA_5_REG OCR0A
01007 #define OCROA_6_REG OCR0A
01008 #define OCROA_7_REG OCR0A
01009
01010
01011 #define ACIS0_REG ACSR
01012 #define ACIS1_REG ACSR
01013 #define ACIC_REG ACSR
01014 #define ACIE_REG ACSR
01015 #define ACI_REG ACSR
01016 #define ACO_REG ACSR
01017 #define ACBG_REG ACSR
01018 #define ACD_REG ACSR
01019
01020
01021 #define PORTF0_REG PORTF
01022 #define PORTF1_REG PORTF
01023 #define PORTF4_REG PORTF
01024 #define PORTF5_REG PORTF
01025 #define PORTF6_REG PORTF
01026 #define PORTF7_REG PORTF
01027
01028
01029 #define FOC1C_REG TCCR1C
01030 #define FOC1B_REG TCCR1C
01031 #define FOC1A_REG TCCR1C
01032
01033
01034 #define ICR3H0_REG ICR3H
01035 #define ICR3H1_REG ICR3H
01036 #define ICR3H2_REG ICR3H
01037 #define ICR3H3_REG ICR3H
01038 #define ICR3H4_REG ICR3H
01039 #define ICR3H5_REG ICR3H
01040 #define ICR3H6_REG ICR3H
01041 #define ICR3H7_REG ICR3H
01042
01043
01044 #define DDE2_REG DDRE
01045 #define DDE6_REG DDRE
01046
01047
01048 #define UADD0_REG UDADDR
01049 #define UADD1_REG UDADDR
01050 #define UADD2_REG UDADDR
01051 #define UADD3_REG UDADDR
01052 #define UADD4_REG UDADDR
01053 #define UADD5_REG UDADDR
01054 #define UADD6_REG UDADDR
01055 #define ADDEN_REG UDADDR
01056
01057
01058 #define ICR3L0_REG ICR3L
01059 #define ICR3L1_REG ICR3L
01060 #define ICR3L2_REG ICR3L
01061 #define ICR3L3_REG ICR3L
01062 #define ICR3L4_REG ICR3L
01063 #define ICR3L5_REG ICR3L
01064 #define ICR3L6_REG ICR3L
01065 #define ICR3L7_REG ICR3L
01066
01067
01068 #define SPMEN_REG SPMCSR
01069 #define PGERS_REG SPMCSR
01070 #define PGWRT_REG SPMCSR
01071 #define BLBSET_REG SPMCSR
01072 #define RWWSRE_REG SPMCSR
01073 #define SIGRD_REG SPMCSR
01074 #define RWWSB_REG SPMCSR
01075 #define SPMIE_REG SPMCSR
01076
01077
01078 #define NBUSYBK0_REG UESTA0X
01079 #define NBUSYBK1_REG UESTA0X
01080 #define DTSEQ0_REG UESTA0X
01081 #define DTSEQ1_REG UESTA0X
01082 #define UNDERFI_REG UESTA0X
01083 #define OVERFI_REG UESTA0X
01084 #define CFGOK_REG UESTA0X
01085
01086
01087 #define PORTB0_REG PORTB
01088 #define PORTB1_REG PORTB
01089 #define PORTB2_REG PORTB
01090 #define PORTB3_REG PORTB
01091 #define PORTB4_REG PORTB
01092 #define PORTB5_REG PORTB
01093 #define PORTB6_REG PORTB
01094 #define PORTB7_REG PORTB
01095
01096
01097 #define ADCL0_REG ADCL
01098 #define ADCL1_REG ADCL
01099 #define ADCL2_REG ADCL
01100 #define ADCL3_REG ADCL
01101 #define ADCL4_REG ADCL
01102 #define ADCL5_REG ADCL
01103 #define ADCL6_REG ADCL
01104 #define ADCL7_REG ADCL
01105
01106
01107 #define ADCH0_REG ADCH
01108 #define ADCH1_REG ADCH
01109 #define ADCH2_REG ADCH
01110 #define ADCH3_REG ADCH
01111 #define ADCH4_REG ADCH
01112 #define ADCH5_REG ADCH
01113 #define ADCH6_REG ADCH
01114 #define ADCH7_REG ADCH
01115
01116
01117 #define OCR3BL0_REG OCR3BL
01118 #define OCR3BL1_REG OCR3BL
01119 #define OCR3BL2_REG OCR3BL
01120 #define OCR3BL3_REG OCR3BL
01121 #define OCR3BL4_REG OCR3BL
01122 #define OCR3BL5_REG OCR3BL
01123 #define OCR3BL6_REG OCR3BL
01124 #define OCR3BL7_REG OCR3BL
01125
01126
01127 #define OCR3BH0_REG OCR3BH
01128 #define OCR3BH1_REG OCR3BH
01129 #define OCR3BH2_REG OCR3BH
01130 #define OCR3BH3_REG OCR3BH
01131 #define OCR3BH4_REG OCR3BH
01132 #define OCR3BH5_REG OCR3BH
01133 #define OCR3BH6_REG OCR3BH
01134 #define OCR3BH7_REG OCR3BH
01135
01136
01137 #define TOIE3_REG TIMSK3
01138 #define OCIE3A_REG TIMSK3
01139 #define OCIE3B_REG TIMSK3
01140 #define OCIE3C_REG TIMSK3
01141 #define ICIE3_REG TIMSK3
01142
01143
01144 #define TOIE0_REG TIMSK0
01145 #define OCIE0A_REG TIMSK0
01146 #define OCIE0B_REG TIMSK0
01147
01148
01149 #define TOIE1_REG TIMSK1
01150 #define OCIE1A_REG TIMSK1
01151 #define OCIE1B_REG TIMSK1
01152 #define OCIE1C_REG TIMSK1
01153 #define ICIE1_REG TIMSK1
01154
01155
01156 #define EXTON_REG CLKSTA
01157 #define RCON_REG CLKSTA
01158
01159
01160 #define TOIE4_REG TIMSK4
01161 #define OCIE4B_REG TIMSK4
01162 #define OCIE4A_REG TIMSK4
01163 #define OCIE4D_REG TIMSK4
01164
01165
01166 #define CS40_REG TCCR4B
01167 #define CS41_REG TCCR4B
01168 #define CS42_REG TCCR4B
01169 #define CS43_REG TCCR4B
01170 #define DTPS40_REG TCCR4B
01171 #define DTPS41_REG TCCR4B
01172 #define PSR4_REG TCCR4B
01173 #define PWM4X_REG TCCR4B
01174
01175
01176 #define PWM4D_REG TCCR4C
01177 #define FOC4D_REG TCCR4C
01178 #define COM4D0_REG TCCR4C
01179 #define COM4D1_REG TCCR4C
01180 #define COM4B0S_REG TCCR4C
01181 #define COM4B1S_REG TCCR4C
01182 #define COM4A0S_REG TCCR4C
01183 #define COM4A1S_REG TCCR4C
01184
01185
01186 #define PLOCK_REG PLLCSR
01187 #define PLLE_REG PLLCSR
01188 #define PINDIV_REG PLLCSR
01189
01190
01191 #define PWM4B_REG TCCR4A
01192 #define PWM4A_REG TCCR4A
01193 #define FOC4B_REG TCCR4A
01194 #define FOC4A_REG TCCR4A
01195 #define COM4B0_REG TCCR4A
01196 #define COM4B1_REG TCCR4A
01197 #define COM4A0_REG TCCR4A
01198 #define COM4A1_REG TCCR4A
01199
01200
01201 #define PCINT0_REG PCMSK0
01202 #define PCINT1_REG PCMSK0
01203 #define PCINT2_REG PCMSK0
01204 #define PCINT3_REG PCMSK0
01205 #define PCINT4_REG PCMSK0
01206 #define PCINT5_REG PCMSK0
01207 #define PCINT6_REG PCMSK0
01208 #define PCINT7_REG PCMSK0
01209
01210
01211 #define WGM40_REG TCCR4D
01212 #define WGM41_REG TCCR4D
01213 #define FPF4_REG TCCR4D
01214 #define FPAC4_REG TCCR4D
01215 #define FPES4_REG TCCR4D
01216 #define FPNC4_REG TCCR4D
01217 #define FPEN4_REG TCCR4D
01218 #define FPIE4_REG TCCR4D
01219
01220
01221 #define OC4OE0_REG TCCR4E
01222 #define OC4OE1_REG TCCR4E
01223 #define OC4OE2_REG TCCR4E
01224 #define OC4OE3_REG TCCR4E
01225 #define OC4OE4_REG TCCR4E
01226 #define OC4OE5_REG TCCR4E
01227 #define ENHC4_REG TCCR4E
01228 #define TLOCK4_REG TCCR4E
01229
01230
01231 #define PINC6_REG PINC
01232 #define PINC7_REG PINC
01233
01234
01235 #define PINB0_REG PINB
01236 #define PINB1_REG PINB
01237 #define PINB2_REG PINB
01238 #define PINB3_REG PINB
01239 #define PINB4_REG PINB
01240 #define PINB5_REG PINB
01241 #define PINB6_REG PINB
01242 #define PINB7_REG PINB
01243
01244
01245 #define INTF0_REG EIFR
01246 #define INTF1_REG EIFR
01247 #define INTF2_REG EIFR
01248 #define INTF3_REG EIFR
01249 #define INTF4_REG EIFR
01250 #define INTF5_REG EIFR
01251 #define INTF6_REG EIFR
01252 #define INTF7_REG EIFR
01253
01254
01255 #define PINF0_REG PINF
01256 #define PINF1_REG PINF
01257 #define PINF4_REG PINF
01258 #define PINF5_REG PINF
01259 #define PINF6_REG PINF
01260 #define PINF7_REG PINF
01261
01262
01263 #define PINE2_REG PINE
01264 #define PINE6_REG PINE
01265
01266
01267 #define PIND0_REG PIND
01268 #define PIND1_REG PIND
01269 #define PIND2_REG PIND
01270 #define PIND3_REG PIND
01271 #define PIND4_REG PIND
01272 #define PIND5_REG PIND
01273 #define PIND6_REG PIND
01274 #define PIND7_REG PIND
01275
01276
01277 #define OCR1AH0_REG OCR1AH
01278 #define OCR1AH1_REG OCR1AH
01279 #define OCR1AH2_REG OCR1AH
01280 #define OCR1AH3_REG OCR1AH
01281 #define OCR1AH4_REG OCR1AH
01282 #define OCR1AH5_REG OCR1AH
01283 #define OCR1AH6_REG OCR1AH
01284 #define OCR1AH7_REG OCR1AH
01285
01286
01287 #define OCR1AL0_REG OCR1AL
01288 #define OCR1AL1_REG OCR1AL
01289 #define OCR1AL2_REG OCR1AL
01290 #define OCR1AL3_REG OCR1AL
01291 #define OCR1AL4_REG OCR1AL
01292 #define OCR1AL5_REG OCR1AL
01293 #define OCR1AL6_REG OCR1AL
01294 #define OCR1AL7_REG OCR1AL
01295
01296
01297 #define TOV0_REG TIFR0
01298 #define OCF0A_REG TIFR0
01299 #define OCF0B_REG TIFR0
01300
01301
01302 #define PRUSART1_REG PRR1
01303 #define PRTIM3_REG PRR1
01304 #define PRUSB_REG PRR1
01305
01306
01307 #define DT4L0_REG DT4
01308 #define DT4L1_REG DT4
01309 #define DT4L2_REG DT4
01310 #define DT4L3_REG DT4
01311 #define DT4L4_REG DT4
01312 #define DT4L5_REG DT4
01313 #define DT4L6_REG DT4
01314 #define DT4L7_REG DT4
01315
01316
01317