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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER0A_AVAILABLE
00088 #define TIMER0B_AVAILABLE
00089 #define TIMER1_AVAILABLE
00090 #define TIMER1A_AVAILABLE
00091 #define TIMER1B_AVAILABLE
00092 #define TIMER2_AVAILABLE
00093 #define TIMER2A_AVAILABLE
00094 #define TIMER2B_AVAILABLE
00095
00096
00097 #define SIG_OVERFLOW0_NUM 0
00098 #define SIG_OVERFLOW1_NUM 1
00099 #define SIG_OVERFLOW2_NUM 2
00100 #define SIG_OVERFLOW_TOTAL_NUM 3
00101
00102
00103 #define SIG_OUTPUT_COMPARE0A_NUM 0
00104 #define SIG_OUTPUT_COMPARE0B_NUM 1
00105 #define SIG_OUTPUT_COMPARE1A_NUM 2
00106 #define SIG_OUTPUT_COMPARE1B_NUM 3
00107 #define SIG_OUTPUT_COMPARE2A_NUM 4
00108 #define SIG_OUTPUT_COMPARE2B_NUM 5
00109 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
00110
00111
00112 #define PWM0A_NUM 0
00113 #define PWM0B_NUM 1
00114 #define PWM1A_NUM 2
00115 #define PWM1B_NUM 3
00116 #define PWM2A_NUM 4
00117 #define PWM2B_NUM 5
00118 #define PWM_TOTAL_NUM 6
00119
00120
00121 #define SIG_INPUT_CAPTURE1_NUM 0
00122 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00123
00124
00125
00126 #define MUX0_REG ADMUX
00127 #define MUX1_REG ADMUX
00128 #define MUX2_REG ADMUX
00129 #define MUX3_REG ADMUX
00130 #define ADLAR_REG ADMUX
00131 #define REFS0_REG ADMUX
00132 #define REFS1_REG ADMUX
00133
00134
00135 #define WDP0_REG WDTCSR
00136 #define WDP1_REG WDTCSR
00137 #define WDP2_REG WDTCSR
00138 #define WDE_REG WDTCSR
00139 #define WDCE_REG WDTCSR
00140 #define WDP3_REG WDTCSR
00141 #define WDIE_REG WDTCSR
00142 #define WDIF_REG WDTCSR
00143
00144
00145 #define EEDR0_REG EEDR
00146 #define EEDR1_REG EEDR
00147 #define EEDR2_REG EEDR
00148 #define EEDR3_REG EEDR
00149 #define EEDR4_REG EEDR
00150 #define EEDR5_REG EEDR
00151 #define EEDR6_REG EEDR
00152 #define EEDR7_REG EEDR
00153
00154
00155 #define ACIS0_REG ACSR
00156 #define ACIS1_REG ACSR
00157 #define ACIC_REG ACSR
00158 #define ACIE_REG ACSR
00159 #define ACI_REG ACSR
00160 #define ACO_REG ACSR
00161 #define ACBG_REG ACSR
00162 #define ACD_REG ACSR
00163
00164
00165 #define OCR2B_0_REG OCR2B
00166 #define OCR2B_1_REG OCR2B
00167 #define OCR2B_2_REG OCR2B
00168 #define OCR2B_3_REG OCR2B
00169 #define OCR2B_4_REG OCR2B
00170 #define OCR2B_5_REG OCR2B
00171 #define OCR2B_6_REG OCR2B
00172 #define OCR2B_7_REG OCR2B
00173
00174
00175 #define OCR2A_0_REG OCR2A
00176 #define OCR2A_1_REG OCR2A
00177 #define OCR2A_2_REG OCR2A
00178 #define OCR2A_3_REG OCR2A
00179 #define OCR2A_4_REG OCR2A
00180 #define OCR2A_5_REG OCR2A
00181 #define OCR2A_6_REG OCR2A
00182 #define OCR2A_7_REG OCR2A
00183
00184
00185 #define SPDR0_REG SPDR
00186 #define SPDR1_REG SPDR
00187 #define SPDR2_REG SPDR
00188 #define SPDR3_REG SPDR
00189 #define SPDR4_REG SPDR
00190 #define SPDR5_REG SPDR
00191 #define SPDR6_REG SPDR
00192 #define SPDR7_REG SPDR
00193
00194
00195 #define SPI2X_REG SPSR
00196 #define WCOL_REG SPSR
00197 #define SPIF_REG SPSR
00198
00199
00200 #define SP8_REG SPH
00201 #define SP9_REG SPH
00202 #define SP10_REG SPH
00203 #define SP11_REG SPH
00204
00205
00206 #define ICR1L0_REG ICR1L
00207 #define ICR1L1_REG ICR1L
00208 #define ICR1L2_REG ICR1L
00209 #define ICR1L3_REG ICR1L
00210 #define ICR1L4_REG ICR1L
00211 #define ICR1L5_REG ICR1L
00212 #define ICR1L6_REG ICR1L
00213 #define ICR1L7_REG ICR1L
00214
00215
00216 #define PRADC_REG PRR
00217 #define PRUSART0_REG PRR
00218 #define PRSPI_REG PRR
00219 #define PRTIM1_REG PRR
00220 #define PRTIM0_REG PRR
00221 #define PRTIM2_REG PRR
00222 #define PRTWI_REG PRR
00223
00224
00225 #define TWPS0_REG TWSR
00226 #define TWPS1_REG TWSR
00227 #define TWS3_REG TWSR
00228 #define TWS4_REG TWSR
00229 #define TWS5_REG TWSR
00230 #define TWS6_REG TWSR
00231 #define TWS7_REG TWSR
00232
00233
00234 #define MPCM0_REG UCSR0A
00235 #define U2X0_REG UCSR0A
00236 #define UPE0_REG UCSR0A
00237 #define DOR0_REG UCSR0A
00238 #define FE0_REG UCSR0A
00239 #define UDRE0_REG UCSR0A
00240 #define TXC0_REG UCSR0A
00241 #define RXC0_REG UCSR0A
00242
00243
00244 #define PORTD0_REG PORTD
00245 #define PORTD1_REG PORTD
00246 #define PORTD2_REG PORTD
00247 #define PORTD3_REG PORTD
00248 #define PORTD4_REG PORTD
00249 #define PORTD5_REG PORTD
00250 #define PORTD6_REG PORTD
00251 #define PORTD7_REG PORTD
00252
00253
00254 #define TXB80_REG UCSR0B
00255 #define RXB80_REG UCSR0B
00256 #define UCSZ02_REG UCSR0B
00257 #define TXEN0_REG UCSR0B
00258 #define RXEN0_REG UCSR0B
00259 #define UDRIE0_REG UCSR0B
00260 #define TXCIE0_REG UCSR0B
00261 #define RXCIE0_REG UCSR0B
00262
00263
00264 #define PORTB0_REG PORTB
00265 #define PORTB1_REG PORTB
00266 #define PORTB2_REG PORTB
00267 #define PORTB3_REG PORTB
00268 #define PORTB4_REG PORTB
00269 #define PORTB5_REG PORTB
00270 #define PORTB6_REG PORTB
00271 #define PORTB7_REG PORTB
00272
00273
00274 #define PORTC0_REG PORTC
00275 #define PORTC1_REG PORTC
00276 #define PORTC2_REG PORTC
00277 #define PORTC3_REG PORTC
00278 #define PORTC4_REG PORTC
00279 #define PORTC5_REG PORTC
00280 #define PORTC6_REG PORTC
00281
00282
00283 #define UDR0_0_REG UDR0
00284 #define UDR0_1_REG UDR0
00285 #define UDR0_2_REG UDR0
00286 #define UDR0_3_REG UDR0
00287 #define UDR0_4_REG UDR0
00288 #define UDR0_5_REG UDR0
00289 #define UDR0_6_REG UDR0
00290 #define UDR0_7_REG UDR0
00291
00292
00293 #define ISC00_REG EICRA
00294 #define ISC01_REG EICRA
00295 #define ISC10_REG EICRA
00296 #define ISC11_REG EICRA
00297
00298
00299 #define ADC0D_REG DIDR0
00300 #define ADC1D_REG DIDR0
00301 #define ADC2D_REG DIDR0
00302 #define ADC3D_REG DIDR0
00303 #define ADC4D_REG DIDR0
00304 #define ADC5D_REG DIDR0
00305
00306
00307 #define AIN0D_REG DIDR1
00308 #define AIN1D_REG DIDR1
00309
00310
00311 #define TCR2BUB_REG ASSR
00312 #define TCR2AUB_REG ASSR
00313 #define OCR2BUB_REG ASSR
00314 #define OCR2AUB_REG ASSR
00315 #define TCN2UB_REG ASSR
00316 #define AS2_REG ASSR
00317 #define EXCLK_REG ASSR
00318
00319
00320 #define CLKPS0_REG CLKPR
00321 #define CLKPS1_REG CLKPR
00322 #define CLKPS2_REG CLKPR
00323 #define CLKPS3_REG CLKPR
00324 #define CLKPCE_REG CLKPR
00325
00326
00327 #define C_REG SREG
00328 #define Z_REG SREG
00329 #define N_REG SREG
00330 #define V_REG SREG
00331 #define S_REG SREG
00332 #define H_REG SREG
00333 #define T_REG SREG
00334 #define I_REG SREG
00335
00336
00337 #define DDB0_REG DDRB
00338 #define DDB1_REG DDRB
00339 #define DDB2_REG DDRB
00340 #define DDB3_REG DDRB
00341 #define DDB4_REG DDRB
00342 #define DDB5_REG DDRB
00343 #define DDB6_REG DDRB
00344 #define DDB7_REG DDRB
00345
00346
00347 #define DDC0_REG DDRC
00348 #define DDC1_REG DDRC
00349 #define DDC2_REG DDRC
00350 #define DDC3_REG DDRC
00351 #define DDC4_REG DDRC
00352 #define DDC5_REG DDRC
00353 #define DDC6_REG DDRC
00354
00355
00356 #define WGM10_REG TCCR1A
00357 #define WGM11_REG TCCR1A
00358 #define COM1B0_REG TCCR1A
00359 #define COM1B1_REG TCCR1A
00360 #define COM1A0_REG TCCR1A
00361 #define COM1A1_REG TCCR1A
00362
00363
00364 #define FOC1B_REG TCCR1C
00365 #define FOC1A_REG TCCR1C
00366
00367
00368 #define CS10_REG TCCR1B
00369 #define CS11_REG TCCR1B
00370 #define CS12_REG TCCR1B
00371 #define WGM12_REG TCCR1B
00372 #define WGM13_REG TCCR1B
00373 #define ICES1_REG TCCR1B
00374 #define ICNC1_REG TCCR1B
00375
00376
00377 #define CAL0_REG OSCCAL
00378 #define CAL1_REG OSCCAL
00379 #define CAL2_REG OSCCAL
00380 #define CAL3_REG OSCCAL
00381 #define CAL4_REG OSCCAL
00382 #define CAL5_REG OSCCAL
00383 #define CAL6_REG OSCCAL
00384 #define CAL7_REG OSCCAL
00385
00386
00387 #define GPIOR10_REG GPIOR1
00388 #define GPIOR11_REG GPIOR1
00389 #define GPIOR12_REG GPIOR1
00390 #define GPIOR13_REG GPIOR1
00391 #define GPIOR14_REG GPIOR1
00392 #define GPIOR15_REG GPIOR1
00393 #define GPIOR16_REG GPIOR1
00394 #define GPIOR17_REG GPIOR1
00395
00396
00397 #define GPIOR00_REG GPIOR0
00398 #define GPIOR01_REG GPIOR0
00399 #define GPIOR02_REG GPIOR0
00400 #define GPIOR03_REG GPIOR0
00401 #define GPIOR04_REG GPIOR0
00402 #define GPIOR05_REG GPIOR0
00403 #define GPIOR06_REG GPIOR0
00404 #define GPIOR07_REG GPIOR0
00405
00406
00407 #define GPIOR20_REG GPIOR2
00408 #define GPIOR21_REG GPIOR2
00409 #define GPIOR22_REG GPIOR2
00410 #define GPIOR23_REG GPIOR2
00411 #define GPIOR24_REG GPIOR2
00412 #define GPIOR25_REG GPIOR2
00413 #define GPIOR26_REG GPIOR2
00414 #define GPIOR27_REG GPIOR2
00415
00416
00417 #define PCIE0_REG PCICR
00418 #define PCIE1_REG PCICR
00419 #define PCIE2_REG PCICR
00420
00421
00422 #define TCNT2_0_REG TCNT2
00423 #define TCNT2_1_REG TCNT2
00424 #define TCNT2_2_REG TCNT2
00425 #define TCNT2_3_REG TCNT2
00426 #define TCNT2_4_REG TCNT2
00427 #define TCNT2_5_REG TCNT2
00428 #define TCNT2_6_REG TCNT2
00429 #define TCNT2_7_REG TCNT2
00430
00431
00432 #define TCNT0_0_REG TCNT0
00433 #define TCNT0_1_REG TCNT0
00434 #define TCNT0_2_REG TCNT0
00435 #define TCNT0_3_REG TCNT0
00436 #define TCNT0_4_REG TCNT0
00437 #define TCNT0_5_REG TCNT0
00438 #define TCNT0_6_REG TCNT0
00439 #define TCNT0_7_REG TCNT0
00440
00441
00442 #define TWGCE_REG TWAR
00443 #define TWA0_REG TWAR
00444 #define TWA1_REG TWAR
00445 #define TWA2_REG TWAR
00446 #define TWA3_REG TWAR
00447 #define TWA4_REG TWAR
00448 #define TWA5_REG TWAR
00449 #define TWA6_REG TWAR
00450
00451
00452 #define CS00_REG TCCR0B
00453 #define CS01_REG TCCR0B
00454 #define CS02_REG TCCR0B
00455 #define WGM02_REG TCCR0B
00456 #define FOC0B_REG TCCR0B
00457 #define FOC0A_REG TCCR0B
00458
00459
00460 #define WGM00_REG TCCR0A
00461 #define WGM01_REG TCCR0A
00462 #define COM0B0_REG TCCR0A
00463 #define COM0B1_REG TCCR0A
00464 #define COM0A0_REG TCCR0A
00465 #define COM0A1_REG TCCR0A
00466
00467
00468 #define TOV2_REG TIFR2
00469 #define OCF2A_REG TIFR2
00470 #define OCF2B_REG TIFR2
00471
00472
00473 #define TOV0_REG TIFR0
00474 #define OCF0A_REG TIFR0
00475 #define OCF0B_REG TIFR0
00476
00477
00478 #define TOV1_REG TIFR1
00479 #define OCF1A_REG TIFR1
00480 #define OCF1B_REG TIFR1
00481 #define ICF1_REG TIFR1
00482
00483
00484 #define PSRSYNC_REG GTCCR
00485 #define TSM_REG GTCCR
00486 #define PSRASY_REG GTCCR
00487
00488
00489 #define TWBR0_REG TWBR
00490 #define TWBR1_REG TWBR
00491 #define TWBR2_REG TWBR
00492 #define TWBR3_REG TWBR
00493 #define TWBR4_REG TWBR
00494 #define TWBR5_REG TWBR
00495 #define TWBR6_REG TWBR
00496 #define TWBR7_REG TWBR
00497
00498
00499 #define ICR1H0_REG ICR1H
00500 #define ICR1H1_REG ICR1H
00501 #define ICR1H2_REG ICR1H
00502 #define ICR1H3_REG ICR1H
00503 #define ICR1H4_REG ICR1H
00504 #define ICR1H5_REG ICR1H
00505 #define ICR1H6_REG ICR1H
00506 #define ICR1H7_REG ICR1H
00507
00508
00509 #define OCR1BL0_REG OCR1BL
00510 #define OCR1BL1_REG OCR1BL
00511 #define OCR1BL2_REG OCR1BL
00512 #define OCR1BL3_REG OCR1BL
00513 #define OCR1BL4_REG OCR1BL
00514 #define OCR1BL5_REG OCR1BL
00515 #define OCR1BL6_REG OCR1BL
00516 #define OCR1BL7_REG OCR1BL
00517
00518
00519 #define PCIF0_REG PCIFR
00520 #define PCIF1_REG PCIFR
00521 #define PCIF2_REG PCIFR
00522
00523
00524 #define SP0_REG SPL
00525 #define SP1_REG SPL
00526 #define SP2_REG SPL
00527 #define SP3_REG SPL
00528 #define SP4_REG SPL
00529 #define SP5_REG SPL
00530 #define SP6_REG SPL
00531 #define SP7_REG SPL
00532
00533
00534 #define OCR1BH0_REG OCR1BH
00535 #define OCR1BH1_REG OCR1BH
00536 #define OCR1BH2_REG OCR1BH
00537 #define OCR1BH3_REG OCR1BH
00538 #define OCR1BH4_REG OCR1BH
00539 #define OCR1BH5_REG OCR1BH
00540 #define OCR1BH6_REG OCR1BH
00541 #define OCR1BH7_REG OCR1BH
00542
00543
00544 #define EERE_REG EECR
00545 #define EEPE_REG EECR
00546 #define EEMPE_REG EECR
00547 #define EERIE_REG EECR
00548 #define EEPM0_REG EECR
00549 #define EEPM1_REG EECR
00550
00551
00552 #define SE_REG SMCR
00553 #define SM0_REG SMCR
00554 #define SM1_REG SMCR
00555 #define SM2_REG SMCR
00556
00557
00558 #define TWIE_REG TWCR
00559 #define TWEN_REG TWCR
00560 #define TWWC_REG TWCR
00561 #define TWSTO_REG TWCR
00562 #define TWSTA_REG TWCR
00563 #define TWEA_REG TWCR
00564 #define TWINT_REG TWCR
00565
00566
00567 #define WGM20_REG TCCR2A
00568 #define WGM21_REG TCCR2A
00569 #define COM2B0_REG TCCR2A
00570 #define COM2B1_REG TCCR2A
00571 #define COM2A0_REG TCCR2A
00572 #define COM2A1_REG TCCR2A
00573
00574
00575 #define CS20_REG TCCR2B
00576 #define CS21_REG TCCR2B
00577 #define CS22_REG TCCR2B
00578 #define WGM22_REG TCCR2B
00579 #define FOC2B_REG TCCR2B
00580 #define FOC2A_REG TCCR2B
00581
00582
00583 #define UBRR8_REG UBRR0H
00584 #define UBRR9_REG UBRR0H
00585 #define UBRR10_REG UBRR0H
00586 #define UBRR11_REG UBRR0H
00587
00588
00589 #define UBRR0_REG UBRR0L
00590 #define UBRR1_REG UBRR0L
00591 #define UBRR2_REG UBRR0L
00592 #define UBRR3_REG UBRR0L
00593 #define UBRR4_REG UBRR0L
00594 #define UBRR5_REG UBRR0L
00595 #define UBRR6_REG UBRR0L
00596 #define UBRR7_REG UBRR0L
00597
00598
00599 #define EEAR8_REG EEARH
00600 #define EEAR9_REG EEARH
00601
00602
00603 #define EEAR0_REG EEARL
00604 #define EEAR1_REG EEARL
00605 #define EEAR2_REG EEARL
00606 #define EEAR3_REG EEARL
00607 #define EEAR4_REG EEARL
00608 #define EEAR5_REG EEARL
00609 #define EEAR6_REG EEARL
00610 #define EEAR7_REG EEARL
00611
00612
00613 #define IVCE_REG MCUCR
00614 #define IVSEL_REG MCUCR
00615 #define PUD_REG MCUCR
00616 #define BODSE_REG MCUCR
00617 #define BODS_REG MCUCR
00618
00619
00620 #define PORF_REG MCUSR
00621 #define EXTRF_REG MCUSR
00622 #define BORF_REG MCUSR
00623 #define WDRF_REG MCUSR
00624
00625
00626 #define TWD0_REG TWDR
00627 #define TWD1_REG TWDR
00628 #define TWD2_REG TWDR
00629 #define TWD3_REG TWDR
00630 #define TWD4_REG TWDR
00631 #define TWD5_REG TWDR
00632 #define TWD6_REG TWDR
00633 #define TWD7_REG TWDR
00634
00635
00636 #define OCR1AH0_REG OCR1AH
00637 #define OCR1AH1_REG OCR1AH
00638 #define OCR1AH2_REG OCR1AH
00639 #define OCR1AH3_REG OCR1AH
00640 #define OCR1AH4_REG OCR1AH
00641 #define OCR1AH5_REG OCR1AH
00642 #define OCR1AH6_REG OCR1AH
00643 #define OCR1AH7_REG OCR1AH
00644
00645
00646 #define ADPS0_REG ADCSRA
00647 #define ADPS1_REG ADCSRA
00648 #define ADPS2_REG ADCSRA
00649 #define ADIE_REG ADCSRA
00650 #define ADIF_REG ADCSRA
00651 #define ADATE_REG ADCSRA
00652 #define ADSC_REG ADCSRA
00653 #define ADEN_REG ADCSRA
00654
00655
00656 #define ADTS0_REG ADCSRB
00657 #define ADTS1_REG ADCSRB
00658 #define ADTS2_REG ADCSRB
00659 #define ACME_REG ADCSRB
00660
00661
00662 #define OCROA_0_REG OCR0A
00663 #define OCROA_1_REG OCR0A
00664 #define OCROA_2_REG OCR0A
00665 #define OCROA_3_REG OCR0A
00666 #define OCROA_4_REG OCR0A
00667 #define OCROA_5_REG OCR0A
00668 #define OCROA_6_REG OCR0A
00669 #define OCROA_7_REG OCR0A
00670
00671
00672 #define OCR0B_0_REG OCR0B
00673 #define OCR0B_1_REG OCR0B
00674 #define OCR0B_2_REG OCR0B
00675 #define OCR0B_3_REG OCR0B
00676 #define OCR0B_4_REG OCR0B
00677 #define OCR0B_5_REG OCR0B
00678 #define OCR0B_6_REG OCR0B
00679 #define OCR0B_7_REG OCR0B
00680
00681
00682 #define TCNT1L0_REG TCNT1L
00683 #define TCNT1L1_REG TCNT1L
00684 #define TCNT1L2_REG TCNT1L
00685 #define TCNT1L3_REG TCNT1L
00686 #define TCNT1L4_REG TCNT1L
00687 #define TCNT1L5_REG TCNT1L
00688 #define TCNT1L6_REG TCNT1L
00689 #define TCNT1L7_REG TCNT1L
00690
00691
00692 #define DDD0_REG DDRD
00693 #define DDD1_REG DDRD
00694 #define DDD2_REG DDRD
00695 #define DDD3_REG DDRD
00696 #define DDD4_REG DDRD
00697 #define DDD5_REG DDRD
00698 #define DDD6_REG DDRD
00699 #define DDD7_REG DDRD
00700
00701
00702 #define UCPOL0_REG UCSR0C
00703 #define UCSZ00_REG UCSR0C
00704 #define UCSZ01_REG UCSR0C
00705 #define USBS0_REG UCSR0C
00706 #define UPM00_REG UCSR0C
00707 #define UPM01_REG UCSR0C
00708 #define UMSEL00_REG UCSR0C
00709 #define UMSEL01_REG UCSR0C
00710
00711
00712 #define SELFPRGEN_REG SPMCSR
00713 #define PGERS_REG SPMCSR
00714 #define PGWRT_REG SPMCSR
00715 #define BLBSET_REG SPMCSR
00716 #define RWWSRE_REG SPMCSR
00717 #define RWWSB_REG SPMCSR
00718 #define SPMIE_REG SPMCSR
00719
00720
00721 #define TCNT1H0_REG TCNT1H
00722 #define TCNT1H1_REG TCNT1H
00723 #define TCNT1H2_REG TCNT1H
00724 #define TCNT1H3_REG TCNT1H
00725 #define TCNT1H4_REG TCNT1H
00726 #define TCNT1H5_REG TCNT1H
00727 #define TCNT1H6_REG TCNT1H
00728 #define TCNT1H7_REG TCNT1H
00729
00730
00731 #define ADCL0_REG ADCL
00732 #define ADCL1_REG ADCL
00733 #define ADCL2_REG ADCL
00734 #define ADCL3_REG ADCL
00735 #define ADCL4_REG ADCL
00736 #define ADCL5_REG ADCL
00737 #define ADCL6_REG ADCL
00738 #define ADCL7_REG ADCL
00739
00740
00741 #define ADCH0_REG ADCH
00742 #define ADCH1_REG ADCH
00743 #define ADCH2_REG ADCH
00744 #define ADCH3_REG ADCH
00745 #define ADCH4_REG ADCH
00746 #define ADCH5_REG ADCH
00747 #define ADCH6_REG ADCH
00748 #define ADCH7_REG ADCH
00749
00750
00751 #define TOIE2_REG TIMSK2
00752 #define OCIE2A_REG TIMSK2
00753 #define OCIE2B_REG TIMSK2
00754
00755
00756 #define INT0_REG EIMSK
00757 #define INT1_REG EIMSK
00758
00759
00760 #define TOIE0_REG TIMSK0
00761 #define OCIE0A_REG TIMSK0
00762 #define OCIE0B_REG TIMSK0
00763
00764
00765 #define TOIE1_REG TIMSK1
00766 #define OCIE1A_REG TIMSK1
00767 #define OCIE1B_REG TIMSK1
00768 #define ICIE1_REG TIMSK1
00769
00770
00771 #define PCINT0_REG PCMSK0
00772 #define PCINT1_REG PCMSK0
00773 #define PCINT2_REG PCMSK0
00774 #define PCINT3_REG PCMSK0
00775 #define PCINT4_REG PCMSK0
00776 #define PCINT5_REG PCMSK0
00777 #define PCINT6_REG PCMSK0
00778 #define PCINT7_REG PCMSK0
00779
00780
00781 #define PCINT8_REG PCMSK1
00782 #define PCINT9_REG PCMSK1
00783 #define PCINT10_REG PCMSK1
00784 #define PCINT11_REG PCMSK1
00785 #define PCINT12_REG PCMSK1
00786 #define PCINT13_REG PCMSK1
00787 #define PCINT14_REG PCMSK1
00788
00789
00790 #define PCINT16_REG PCMSK2
00791 #define PCINT17_REG PCMSK2
00792 #define PCINT18_REG PCMSK2
00793 #define PCINT19_REG PCMSK2
00794 #define PCINT20_REG PCMSK2
00795 #define PCINT21_REG PCMSK2
00796 #define PCINT22_REG PCMSK2
00797 #define PCINT23_REG PCMSK2
00798
00799
00800 #define PINC0_REG PINC
00801 #define PINC1_REG PINC
00802 #define PINC2_REG PINC
00803 #define PINC3_REG PINC
00804 #define PINC4_REG PINC
00805 #define PINC5_REG PINC
00806 #define PINC6_REG PINC
00807
00808
00809 #define PINB0_REG PINB
00810 #define PINB1_REG PINB
00811 #define PINB2_REG PINB
00812 #define PINB3_REG PINB
00813 #define PINB4_REG PINB
00814 #define PINB5_REG PINB
00815 #define PINB6_REG PINB
00816 #define PINB7_REG PINB
00817
00818
00819 #define INTF0_REG EIFR
00820 #define INTF1_REG EIFR
00821
00822
00823 #define PIND0_REG PIND
00824 #define PIND1_REG PIND
00825 #define PIND2_REG PIND
00826 #define PIND3_REG PIND
00827 #define PIND4_REG PIND
00828 #define PIND5_REG PIND
00829 #define PIND6_REG PIND
00830 #define PIND7_REG PIND
00831
00832
00833 #define TWAM0_REG TWAMR
00834 #define TWAM1_REG TWAMR
00835 #define TWAM2_REG TWAMR
00836 #define TWAM3_REG TWAMR
00837 #define TWAM4_REG TWAMR
00838 #define TWAM5_REG TWAMR
00839 #define TWAM6_REG TWAMR
00840
00841
00842 #define OCR1AL0_REG OCR1AL
00843 #define OCR1AL1_REG OCR1AL
00844 #define OCR1AL2_REG OCR1AL
00845 #define OCR1AL3_REG OCR1AL
00846 #define OCR1AL4_REG OCR1AL
00847 #define OCR1AL5_REG OCR1AL
00848 #define OCR1AL6_REG OCR1AL
00849 #define OCR1AL7_REG OCR1AL
00850
00851
00852 #define SPR0_REG SPCR
00853 #define SPR1_REG SPCR
00854 #define CPHA_REG SPCR
00855 #define CPOL_REG SPCR
00856 #define MSTR_REG SPCR
00857 #define DORD_REG SPCR
00858 #define SPE_REG SPCR
00859 #define SPIE_REG SPCR
00860
00861
00862 #define ICP1_PORT PORTB
00863 #define ICP1_BIT 0
00864 #define CLKO_PORT PORTB
00865 #define CLKO_BIT 0
00866 #define PCINT0_PORT PORTB
00867 #define PCINT0_BIT 0
00868
00869 #define OC1A_PORT PORTB
00870 #define OC1A_BIT 1
00871 #define PCINT1_PORT PORTB
00872 #define PCINT1_BIT 1
00873
00874 #define SS_PORT PORTB
00875 #define SS_BIT 2
00876 #define OC1B_PORT PORTB
00877 #define OC1B_BIT 2
00878 #define PCINT2_PORT PORTB
00879 #define PCINT2_BIT 2
00880
00881 #define MOSI_PORT PORTB
00882 #define MOSI_BIT 3
00883 #define OC2A_PORT PORTB
00884 #define OC2A_BIT 3
00885 #define PCINT3_PORT PORTB
00886 #define PCINT3_BIT 3
00887
00888 #define MISO_PORT PORTB
00889 #define MISO_BIT 4
00890 #define PCINT4_PORT PORTB
00891 #define PCINT4_BIT 4
00892
00893 #define SCK_PORT PORTB
00894 #define SCK_BIT 5
00895 #define PCINT5_PORT PORTB
00896 #define PCINT5_BIT 5
00897
00898 #define XTAL1_PORT PORTB
00899 #define XTAL1_BIT 6
00900 #define TOSC1_PORT PORTB
00901 #define TOSC1_BIT 6
00902 #define PCINT6_PORT PORTB
00903 #define PCINT6_BIT 6
00904
00905 #define XTAL2_PORT PORTB
00906 #define XTAL2_BIT 7
00907 #define TOSC2_PORT PORTB
00908 #define TOSC2_BIT 7
00909 #define PCINT7_PORT PORTB
00910 #define PCINT7_BIT 7
00911
00912 #define ADC0_PORT PORTC
00913 #define ADC0_BIT 0
00914 #define PCINT8_PORT PORTC
00915 #define PCINT8_BIT 0
00916
00917 #define ADC1_PORT PORTC
00918 #define ADC1_BIT 1
00919 #define PCINT9_PORT PORTC
00920 #define PCINT9_BIT 1
00921
00922 #define ADC2_PORT PORTC
00923 #define ADC2_BIT 2
00924 #define PCINT10_PORT PORTC
00925 #define PCINT10_BIT 2
00926
00927 #define ADC3_PORT PORTC
00928 #define ADC3_BIT 3
00929 #define PCINT11_PORT PORTC
00930 #define PCINT11_BIT 3
00931
00932 #define ADC4_PORT PORTC
00933 #define ADC4_BIT 4
00934 #define SDA_PORT PORTC
00935 #define SDA_BIT 4
00936 #define PCINT12_PORT PORTC
00937 #define PCINT12_BIT 4
00938
00939 #define ADC5_PORT PORTC
00940 #define ADC5_BIT 5
00941 #define SCL_PORT PORTC
00942 #define SCL_BIT 5
00943 #define PCINT13_PORT PORTC
00944 #define PCINT13_BIT 5
00945
00946 #define RESET_PORT PORTC
00947 #define RESET_BIT 6
00948 #define PCINT14_PORT PORTC
00949 #define PCINT14_BIT 6
00950
00951 #define RXD_PORT PORTD
00952 #define RXD_BIT 0
00953 #define PCINT16_PORT PORTD
00954 #define PCINT16_BIT 0
00955
00956 #define TXD_PORT PORTD
00957 #define TXD_BIT 1
00958 #define PCINT17_PORT PORTD
00959 #define PCINT17_BIT 1
00960
00961 #define INT0_PORT PORTD
00962 #define INT0_BIT 2
00963 #define PCINT18_PORT PORTD
00964 #define PCINT18_BIT 2
00965
00966 #define PCINT19_PORT PORTD
00967 #define PCINT19_BIT 3
00968 #define OC2B_PORT PORTD
00969 #define OC2B_BIT 3
00970 #define INT1_PORT PORTD
00971 #define INT1_BIT 3
00972
00973 #define XCK_PORT PORTD
00974 #define XCK_BIT 4
00975 #define T0_PORT PORTD
00976 #define T0_BIT 4
00977 #define PCINT20_PORT PORTD
00978 #define PCINT20_BIT 4
00979
00980 #define T1_PORT PORTD
00981 #define T1_BIT 5
00982 #define OC0B_PORT PORTD
00983 #define OC0B_BIT 5
00984 #define PCINT21_PORT PORTD
00985 #define PCINT21_BIT 5
00986
00987 #define AIN0_PORT PORTD
00988 #define AIN0_BIT 6
00989 #define OC0A_PORT PORTD
00990 #define OC0A_BIT 6
00991 #define PCINT22_PORT PORTD
00992 #define PCINT22_BIT 6
00993
00994 #define AIN1_PORT PORTD
00995 #define AIN1_BIT 7
00996 #define PCINT23_PORT PORTD
00997 #define PCINT23_BIT 7
00998
00999