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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define WDP0_REG WDTCR
00119 #define WDP1_REG WDTCR
00120 #define WDP2_REG WDTCR
00121 #define WDE_REG WDTCR
00122 #define WDCE_REG WDTCR
00123
00124
00125 #define MUX0_REG ADMUX
00126 #define MUX1_REG ADMUX
00127 #define MUX2_REG ADMUX
00128 #define MUX3_REG ADMUX
00129 #define MUX4_REG ADMUX
00130 #define ADLAR_REG ADMUX
00131 #define REFS0_REG ADMUX
00132 #define REFS1_REG ADMUX
00133
00134
00135 #define EEDR0_REG EEDR
00136 #define EEDR1_REG EEDR
00137 #define EEDR2_REG EEDR
00138 #define EEDR3_REG EEDR
00139 #define EEDR4_REG EEDR
00140 #define EEDR5_REG EEDR
00141 #define EEDR6_REG EEDR
00142 #define EEDR7_REG EEDR
00143
00144
00145 #define OCR2A0_REG OCR2A
00146 #define OCR2A1_REG OCR2A
00147 #define OCR2A2_REG OCR2A
00148 #define OCR2A3_REG OCR2A
00149 #define OCR2A4_REG OCR2A
00150 #define OCR2A5_REG OCR2A
00151 #define OCR2A6_REG OCR2A
00152 #define OCR2A7_REG OCR2A
00153
00154
00155 #define SPDR0_REG SPDR
00156 #define SPDR1_REG SPDR
00157 #define SPDR2_REG SPDR
00158 #define SPDR3_REG SPDR
00159 #define SPDR4_REG SPDR
00160 #define SPDR5_REG SPDR
00161 #define SPDR6_REG SPDR
00162 #define SPDR7_REG SPDR
00163
00164
00165 #define SPI2X_REG SPSR
00166 #define WCOL_REG SPSR
00167 #define SPIF_REG SPSR
00168
00169
00170 #define SP8_REG SPH
00171 #define SP9_REG SPH
00172 #define SP10_REG SPH
00173 #define SP11_REG SPH
00174 #define SP12_REG SPH
00175 #define SP13_REG SPH
00176 #define SP14_REG SPH
00177 #define SP15_REG SPH
00178
00179
00180 #define ICR1L0_REG ICR1L
00181 #define ICR1L1_REG ICR1L
00182 #define ICR1L2_REG ICR1L
00183 #define ICR1L3_REG ICR1L
00184 #define ICR1L4_REG ICR1L
00185 #define ICR1L5_REG ICR1L
00186 #define ICR1L6_REG ICR1L
00187 #define ICR1L7_REG ICR1L
00188
00189
00190 #define PRADC_REG PRR
00191 #define PRUSART0_REG PRR
00192 #define PRSPI_REG PRR
00193 #define PRTIM1_REG PRR
00194 #define PRLCD_REG PRR
00195
00196
00197 #define PORTJ0_REG PORTJ
00198 #define PORTJ1_REG PORTJ
00199 #define PORTJ2_REG PORTJ
00200 #define PORTJ3_REG PORTJ
00201 #define PORTJ4_REG PORTJ
00202 #define PORTJ5_REG PORTJ
00203 #define PORTJ6_REG PORTJ
00204
00205
00206 #define PORTH0_REG PORTH
00207 #define PORTH1_REG PORTH
00208 #define PORTH2_REG PORTH
00209 #define PORTH3_REG PORTH
00210 #define PORTH4_REG PORTH
00211 #define PORTH5_REG PORTH
00212 #define PORTH6_REG PORTH
00213 #define PORTH7_REG PORTH
00214
00215
00216 #define PORTF0_REG PORTF
00217 #define PORTF1_REG PORTF
00218 #define PORTF2_REG PORTF
00219 #define PORTF3_REG PORTF
00220 #define PORTF4_REG PORTF
00221 #define PORTF5_REG PORTF
00222 #define PORTF6_REG PORTF
00223 #define PORTF7_REG PORTF
00224
00225
00226 #define PORTG0_REG PORTG
00227 #define PORTG1_REG PORTG
00228 #define PORTG2_REG PORTG
00229 #define PORTG3_REG PORTG
00230 #define PORTG4_REG PORTG
00231
00232
00233 #define UCPOL0_REG UCSR0C
00234 #define UCSZ00_REG UCSR0C
00235 #define UCSZ01_REG UCSR0C
00236 #define USBS0_REG UCSR0C
00237 #define UPM00_REG UCSR0C
00238 #define UPM01_REG UCSR0C
00239 #define UMSEL0_REG UCSR0C
00240
00241
00242 #define PORTE0_REG PORTE
00243 #define PORTE1_REG PORTE
00244 #define PORTE2_REG PORTE
00245 #define PORTE3_REG PORTE
00246 #define PORTE4_REG PORTE
00247 #define PORTE5_REG PORTE
00248 #define PORTE6_REG PORTE
00249 #define PORTE7_REG PORTE
00250
00251
00252 #define TCNT1H0_REG TCNT1H
00253 #define TCNT1H1_REG TCNT1H
00254 #define TCNT1H2_REG TCNT1H
00255 #define TCNT1H3_REG TCNT1H
00256 #define TCNT1H4_REG TCNT1H
00257 #define TCNT1H5_REG TCNT1H
00258 #define TCNT1H6_REG TCNT1H
00259 #define TCNT1H7_REG TCNT1H
00260
00261
00262 #define PORTC0_REG PORTC
00263 #define PORTC1_REG PORTC
00264 #define PORTC2_REG PORTC
00265 #define PORTC3_REG PORTC
00266 #define PORTC4_REG PORTC
00267 #define PORTC5_REG PORTC
00268 #define PORTC6_REG PORTC
00269 #define PORTC7_REG PORTC
00270
00271
00272 #define PORTA0_REG PORTA
00273 #define PORTA1_REG PORTA
00274 #define PORTA2_REG PORTA
00275 #define PORTA3_REG PORTA
00276 #define PORTA4_REG PORTA
00277 #define PORTA5_REG PORTA
00278 #define PORTA6_REG PORTA
00279 #define PORTA7_REG PORTA
00280
00281
00282 #define UDR00_REG UDR0
00283 #define UDR01_REG UDR0
00284 #define UDR02_REG UDR0
00285 #define UDR03_REG UDR0
00286 #define UDR04_REG UDR0
00287 #define UDR05_REG UDR0
00288 #define UDR06_REG UDR0
00289 #define UDR07_REG UDR0
00290
00291
00292 #define ISC00_REG EICRA
00293 #define ISC01_REG EICRA
00294
00295
00296 #define ADC0D_REG DIDR0
00297 #define ADC1D_REG DIDR0
00298 #define ADC2D_REG DIDR0
00299 #define ADC3D_REG DIDR0
00300 #define ADC4D_REG DIDR0
00301 #define ADC5D_REG DIDR0
00302 #define ADC6D_REG DIDR0
00303 #define ADC7D_REG DIDR0
00304
00305
00306 #define AIN0D_REG DIDR1
00307 #define AIN1D_REG DIDR1
00308
00309
00310 #define TCR2UB_REG ASSR
00311 #define OCR2UB_REG ASSR
00312 #define TCN2UB_REG ASSR
00313 #define AS2_REG ASSR
00314 #define EXCLK_REG ASSR
00315
00316
00317 #define CLKPS0_REG CLKPR
00318 #define CLKPS1_REG CLKPR
00319 #define CLKPS2_REG CLKPR
00320 #define CLKPS3_REG CLKPR
00321 #define CLKPCE_REG CLKPR
00322
00323
00324 #define C_REG SREG
00325 #define Z_REG SREG
00326 #define N_REG SREG
00327 #define V_REG SREG
00328 #define S_REG SREG
00329 #define H_REG SREG
00330 #define T_REG SREG
00331 #define I_REG SREG
00332
00333
00334 #define DDJ0_REG DDRJ
00335 #define DDJ1_REG DDRJ
00336 #define DDJ2_REG DDRJ
00337 #define DDJ3_REG DDRJ
00338 #define DDJ4_REG DDRJ
00339 #define DDJ5_REG DDRJ
00340 #define DDJ6_REG DDRJ
00341
00342
00343 #define DDH0_REG DDRH
00344 #define DDH1_REG DDRH
00345 #define DDH2_REG DDRH
00346 #define DDH3_REG DDRH
00347 #define DDH4_REG DDRH
00348 #define DDH5_REG DDRH
00349 #define DDH6_REG DDRH
00350 #define DDH7_REG DDRH
00351
00352
00353 #define DDB0_REG DDRB
00354 #define DDB1_REG DDRB
00355 #define DDB2_REG DDRB
00356 #define DDB3_REG DDRB
00357 #define DDB4_REG DDRB
00358 #define DDB5_REG DDRB
00359 #define DDB6_REG DDRB
00360 #define DDB7_REG DDRB
00361
00362
00363 #define DDC0_REG DDRC
00364 #define DDC1_REG DDRC
00365 #define DDC2_REG DDRC
00366 #define DDC3_REG DDRC
00367 #define DDC4_REG DDRC
00368 #define DDC5_REG DDRC
00369 #define DDC6_REG DDRC
00370 #define DDC7_REG DDRC
00371
00372
00373 #define DDA0_REG DDRA
00374 #define DDA1_REG DDRA
00375 #define DDA2_REG DDRA
00376 #define DDA3_REG DDRA
00377 #define DDA4_REG DDRA
00378 #define DDA5_REG DDRA
00379 #define DDA6_REG DDRA
00380 #define DDA7_REG DDRA
00381
00382
00383 #define WGM10_REG TCCR1A
00384 #define WGM11_REG TCCR1A
00385 #define COM1B0_REG TCCR1A
00386 #define COM1B1_REG TCCR1A
00387 #define COM1A0_REG TCCR1A
00388 #define COM1A1_REG TCCR1A
00389
00390
00391 #define DDG0_REG DDRG
00392 #define DDG1_REG DDRG
00393 #define DDG2_REG DDRG
00394 #define DDG3_REG DDRG
00395 #define DDG4_REG DDRG
00396
00397
00398 #define FOC1B_REG TCCR1C
00399 #define FOC1A_REG TCCR1C
00400
00401
00402 #define CS10_REG TCCR1B
00403 #define CS11_REG TCCR1B
00404 #define CS12_REG TCCR1B
00405 #define WGM12_REG TCCR1B
00406 #define WGM13_REG TCCR1B
00407 #define ICES1_REG TCCR1B
00408 #define ICNC1_REG TCCR1B
00409
00410
00411 #define CAL0_REG OSCCAL
00412 #define CAL1_REG OSCCAL
00413 #define CAL2_REG OSCCAL
00414 #define CAL3_REG OSCCAL
00415 #define CAL4_REG OSCCAL
00416 #define CAL5_REG OSCCAL
00417 #define CAL6_REG OSCCAL
00418 #define CAL7_REG OSCCAL
00419
00420
00421 #define GPIOR10_REG GPIOR1
00422 #define GPIOR11_REG GPIOR1
00423 #define GPIOR12_REG GPIOR1
00424 #define GPIOR13_REG GPIOR1
00425 #define GPIOR14_REG GPIOR1
00426 #define GPIOR15_REG GPIOR1
00427 #define GPIOR16_REG GPIOR1
00428 #define GPIOR17_REG GPIOR1
00429
00430
00431 #define GPIOR00_REG GPIOR0
00432 #define GPIOR01_REG GPIOR0
00433 #define GPIOR02_REG GPIOR0
00434 #define GPIOR03_REG GPIOR0
00435 #define GPIOR04_REG GPIOR0
00436 #define GPIOR05_REG GPIOR0
00437 #define GPIOR06_REG GPIOR0
00438 #define GPIOR07_REG GPIOR0
00439
00440
00441 #define GPIOR20_REG GPIOR2
00442 #define GPIOR21_REG GPIOR2
00443 #define GPIOR22_REG GPIOR2
00444 #define GPIOR23_REG GPIOR2
00445 #define GPIOR24_REG GPIOR2
00446 #define GPIOR25_REG GPIOR2
00447 #define GPIOR26_REG GPIOR2
00448 #define GPIOR27_REG GPIOR2
00449
00450
00451 #define DDE0_REG DDRE
00452 #define DDE1_REG DDRE
00453 #define DDE2_REG DDRE
00454 #define DDE3_REG DDRE
00455 #define DDE4_REG DDRE
00456 #define DDE5_REG DDRE
00457 #define DDE6_REG DDRE
00458 #define DDE7_REG DDRE
00459
00460
00461 #define TCNT2_0_REG TCNT2
00462 #define TCNT2_1_REG TCNT2
00463 #define TCNT2_2_REG TCNT2
00464 #define TCNT2_3_REG TCNT2
00465 #define TCNT2_4_REG TCNT2
00466 #define TCNT2_5_REG TCNT2
00467 #define TCNT2_6_REG TCNT2
00468 #define TCNT2_7_REG TCNT2
00469
00470
00471 #define TCNT0_0_REG TCNT0
00472 #define TCNT0_1_REG TCNT0
00473 #define TCNT0_2_REG TCNT0
00474 #define TCNT0_3_REG TCNT0
00475 #define TCNT0_4_REG TCNT0
00476 #define TCNT0_5_REG TCNT0
00477 #define TCNT0_6_REG TCNT0
00478 #define TCNT0_7_REG TCNT0
00479
00480
00481 #define CS00_REG TCCR0A
00482 #define CS01_REG TCCR0A
00483 #define CS02_REG TCCR0A
00484 #define WGM01_REG TCCR0A
00485 #define COM0A0_REG TCCR0A
00486 #define COM0A1_REG TCCR0A
00487 #define WGM00_REG TCCR0A
00488 #define FOC0A_REG TCCR0A
00489
00490
00491 #define TOV2_REG TIFR2
00492 #define OCF2A_REG TIFR2
00493
00494
00495 #define TOV0_REG TIFR0
00496 #define OCF0A_REG TIFR0
00497
00498
00499 #define TOV1_REG TIFR1
00500 #define OCF1A_REG TIFR1
00501 #define OCF1B_REG TIFR1
00502 #define ICF1_REG TIFR1
00503
00504
00505 #define PSR310_REG GTCCR
00506 #define TSM_REG GTCCR
00507 #define PSR2_REG GTCCR
00508
00509
00510 #define ICR1H0_REG ICR1H
00511 #define ICR1H1_REG ICR1H
00512 #define ICR1H2_REG ICR1H
00513 #define ICR1H3_REG ICR1H
00514 #define ICR1H4_REG ICR1H
00515 #define ICR1H5_REG ICR1H
00516 #define ICR1H6_REG ICR1H
00517 #define ICR1H7_REG ICR1H
00518
00519
00520 #define OCR1BL0_REG OCR1BL
00521 #define OCR1BL1_REG OCR1BL
00522 #define OCR1BL2_REG OCR1BL
00523 #define OCR1BL3_REG OCR1BL
00524 #define OCR1BL4_REG OCR1BL
00525 #define OCR1BL5_REG OCR1BL
00526 #define OCR1BL6_REG OCR1BL
00527 #define OCR1BL7_REG OCR1BL
00528
00529
00530 #define OCR1BH0_REG OCR1BH
00531 #define OCR1BH1_REG OCR1BH
00532 #define OCR1BH2_REG OCR1BH
00533 #define OCR1BH3_REG OCR1BH
00534 #define OCR1BH4_REG OCR1BH
00535 #define OCR1BH5_REG OCR1BH
00536 #define OCR1BH6_REG OCR1BH
00537 #define OCR1BH7_REG OCR1BH
00538
00539
00540 #define SP0_REG SPL
00541 #define SP1_REG SPL
00542 #define SP2_REG SPL
00543 #define SP3_REG SPL
00544 #define SP4_REG SPL
00545 #define SP5_REG SPL
00546 #define SP6_REG SPL
00547 #define SP7_REG SPL
00548
00549
00550 #define JTRF_REG MCUSR
00551 #define PORF_REG MCUSR
00552 #define EXTRF_REG MCUSR
00553 #define BORF_REG MCUSR
00554 #define WDRF_REG MCUSR
00555
00556
00557 #define EERE_REG EECR
00558 #define EEWE_REG EECR
00559 #define EEMWE_REG EECR
00560 #define EERIE_REG EECR
00561
00562
00563 #define SE_REG SMCR
00564 #define SM0_REG SMCR
00565 #define SM1_REG SMCR
00566 #define SM2_REG SMCR
00567
00568
00569 #define CS20_REG TCCR2A
00570 #define CS21_REG TCCR2A
00571 #define CS22_REG TCCR2A
00572 #define WGM21_REG TCCR2A
00573 #define COM2A0_REG TCCR2A
00574 #define COM2A1_REG TCCR2A
00575 #define WGM20_REG TCCR2A
00576 #define FOC2A_REG TCCR2A
00577
00578
00579 #define UBRR8_REG UBRR0H
00580 #define UBRR9_REG UBRR0H
00581 #define UBRR10_REG UBRR0H
00582 #define UBRR11_REG UBRR0H
00583
00584
00585 #define UBRR0_REG UBRR0L
00586 #define UBRR1_REG UBRR0L
00587 #define UBRR2_REG UBRR0L
00588 #define UBRR3_REG UBRR0L
00589 #define UBRR4_REG UBRR0L
00590 #define UBRR5_REG UBRR0L
00591 #define UBRR6_REG UBRR0L
00592 #define UBRR7_REG UBRR0L
00593
00594
00595 #define EEAR8_REG EEARH
00596 #define EEAR9_REG EEARH
00597
00598
00599 #define EEAR00_REG EEARL
00600 #define EEAR1_REG EEARL
00601 #define EEAR2_REG EEARL
00602 #define EEAR3_REG EEARL
00603 #define EEAR4_REG EEARL
00604 #define EEAR5_REG EEARL
00605 #define EEAR6_REG EEARL
00606 #define EEAR7_REG EEARL
00607
00608
00609 #define JTD_REG MCUCR
00610 #define IVCE_REG MCUCR
00611 #define IVSEL_REG MCUCR
00612 #define PUD_REG MCUCR
00613
00614
00615 #define PINC0_REG PINC
00616 #define PINC1_REG PINC
00617 #define PINC2_REG PINC
00618 #define PINC3_REG PINC
00619 #define PINC4_REG PINC
00620 #define PINC5_REG PINC
00621 #define PINC6_REG PINC
00622 #define PINC7_REG PINC
00623
00624
00625 #define OCDR0_REG OCDR
00626 #define OCDR1_REG OCDR
00627 #define OCDR2_REG OCDR
00628 #define OCDR3_REG OCDR
00629 #define OCDR4_REG OCDR
00630 #define OCDR5_REG OCDR
00631 #define OCDR6_REG OCDR
00632 #define OCDR7_REG OCDR
00633
00634
00635 #define PINA0_REG PINA
00636 #define PINA1_REG PINA
00637 #define PINA2_REG PINA
00638 #define PINA3_REG PINA
00639 #define PINA4_REG PINA
00640 #define PINA5_REG PINA
00641 #define PINA6_REG PINA
00642 #define PINA7_REG PINA
00643
00644
00645 #define ADPS0_REG ADCSRA
00646 #define ADPS1_REG ADCSRA
00647 #define ADPS2_REG ADCSRA
00648 #define ADIE_REG ADCSRA
00649 #define ADIF_REG ADCSRA
00650 #define ADATE_REG ADCSRA
00651 #define ADSC_REG ADCSRA
00652 #define ADEN_REG ADCSRA
00653
00654
00655 #define ACME_REG ADCSRB
00656 #define ADTS0_REG ADCSRB
00657 #define ADTS1_REG ADCSRB
00658 #define ADTS2_REG ADCSRB
00659
00660
00661 #define DDF0_REG DDRF
00662 #define DDF1_REG DDRF
00663 #define DDF2_REG DDRF
00664 #define DDF3_REG DDRF
00665 #define DDF4_REG DDRF
00666 #define DDF5_REG DDRF
00667 #define DDF6_REG DDRF
00668 #define DDF7_REG DDRF
00669
00670
00671 #define OCR0A0_REG OCR0A
00672 #define OCR0A1_REG OCR0A
00673 #define OCR0A2_REG OCR0A
00674 #define OCR0A3_REG OCR0A
00675 #define OCR0A4_REG OCR0A
00676 #define OCR0A5_REG OCR0A
00677 #define OCR0A6_REG OCR0A
00678 #define OCR0A7_REG OCR0A
00679
00680
00681 #define ACIS0_REG ACSR
00682 #define ACIS1_REG ACSR
00683 #define ACIC_REG ACSR
00684 #define ACIE_REG ACSR
00685 #define ACI_REG ACSR
00686 #define ACO_REG ACSR
00687 #define ACBG_REG ACSR
00688 #define ACD_REG ACSR
00689
00690
00691 #define MPCM0_REG UCSR0A
00692 #define U2X0_REG UCSR0A
00693 #define UPE0_REG UCSR0A
00694 #define DOR0_REG UCSR0A
00695 #define FE0_REG UCSR0A
00696 #define UDRE0_REG UCSR0A
00697 #define TXC0_REG UCSR0A
00698 #define RXC0_REG UCSR0A
00699
00700
00701 #define TXB80_REG UCSR0B
00702 #define RXB80_REG UCSR0B
00703 #define UCSZ02_REG UCSR0B
00704 #define TXEN0_REG UCSR0B
00705 #define RXEN0_REG UCSR0B
00706 #define UDRIE0_REG UCSR0B
00707 #define TXCIE0_REG UCSR0B
00708 #define RXCIE0_REG UCSR0B
00709
00710
00711 #define DDD0_REG DDRD
00712 #define DDD1_REG DDRD
00713 #define DDD2_REG DDRD
00714 #define DDD3_REG DDRD
00715 #define DDD4_REG DDRD
00716 #define DDD5_REG DDRD
00717 #define DDD6_REG DDRD
00718 #define DDD7_REG DDRD
00719
00720
00721 #define USITC_REG USICR
00722 #define USICLK_REG USICR
00723 #define USICS0_REG USICR
00724 #define USICS1_REG USICR
00725 #define USIWM0_REG USICR
00726 #define USIWM1_REG USICR
00727 #define USIOIE_REG USICR
00728 #define USISIE_REG USICR
00729
00730
00731 #define PORTD0_REG PORTD
00732 #define PORTD1_REG PORTD
00733 #define PORTD2_REG PORTD
00734 #define PORTD3_REG PORTD
00735 #define PORTD4_REG PORTD
00736 #define PORTD5_REG PORTD
00737 #define PORTD6_REG PORTD
00738 #define PORTD7_REG PORTD
00739
00740
00741 #define USICNT0_REG USISR
00742 #define USICNT1_REG USISR
00743 #define USICNT2_REG USISR
00744 #define USICNT3_REG USISR
00745 #define USIDC_REG USISR
00746 #define USIPF_REG USISR
00747 #define USIOIF_REG USISR
00748 #define USISIF_REG USISR
00749
00750
00751 #define SPMEN_REG SPMCSR
00752 #define PGERS_REG SPMCSR
00753 #define PGWRT_REG SPMCSR
00754 #define BLBSET_REG SPMCSR
00755 #define RWWSRE_REG SPMCSR
00756 #define RWWSB_REG SPMCSR
00757 #define SPMIE_REG SPMCSR
00758
00759
00760 #define PORTB0_REG PORTB
00761 #define PORTB1_REG PORTB
00762 #define PORTB2_REG PORTB
00763 #define PORTB3_REG PORTB
00764 #define PORTB4_REG PORTB
00765 #define PORTB5_REG PORTB
00766 #define PORTB6_REG PORTB
00767 #define PORTB7_REG PORTB
00768
00769
00770 #define ADCL0_REG ADCL
00771 #define ADCL1_REG ADCL
00772 #define ADCL2_REG ADCL
00773 #define ADCL3_REG ADCL
00774 #define ADCL4_REG ADCL
00775 #define ADCL5_REG ADCL
00776 #define ADCL6_REG ADCL
00777 #define ADCL7_REG ADCL
00778
00779
00780 #define ADCH0_REG ADCH
00781 #define ADCH1_REG ADCH
00782 #define ADCH2_REG ADCH
00783 #define ADCH3_REG ADCH
00784 #define ADCH4_REG ADCH
00785 #define ADCH5_REG ADCH
00786 #define ADCH6_REG ADCH
00787 #define ADCH7_REG ADCH
00788
00789
00790 #define TOIE2_REG TIMSK2
00791 #define OCIE2A_REG TIMSK2
00792
00793
00794 #define INT0_REG EIMSK
00795 #define PCIE0_REG EIMSK
00796 #define PCIE1_REG EIMSK
00797 #define PCIE2_REG EIMSK
00798 #define PCIE3_REG EIMSK
00799
00800
00801 #define TOIE0_REG TIMSK0
00802 #define OCIE0A_REG TIMSK0
00803
00804
00805 #define TOIE1_REG TIMSK1
00806 #define OCIE1A_REG TIMSK1
00807 #define OCIE1B_REG TIMSK1
00808 #define ICIE1_REG TIMSK1
00809
00810
00811 #define PINJ0_REG PINJ
00812 #define PINJ1_REG PINJ
00813 #define PINJ2_REG PINJ
00814 #define PINJ3_REG PINJ
00815 #define PINJ4_REG PINJ
00816 #define PINJ5_REG PINJ
00817 #define PINJ6_REG PINJ
00818
00819
00820 #define PINH0_REG PINH
00821 #define PINH1_REG PINH
00822 #define PINH2_REG PINH
00823 #define PINH3_REG PINH
00824 #define PINH4_REG PINH
00825 #define PINH5_REG PINH
00826 #define PINH6_REG PINH
00827 #define PINH7_REG PINH
00828
00829
00830 #define PCINT0_REG PCMSK0
00831 #define PCINT1_REG PCMSK0
00832 #define PCINT2_REG PCMSK0
00833 #define PCINT3_REG PCMSK0
00834 #define PCINT4_REG PCMSK0
00835 #define PCINT5_REG PCMSK0
00836 #define PCINT6_REG PCMSK0
00837 #define PCINT7_REG PCMSK0
00838
00839
00840 #define PCINT8_REG PCMSK1
00841 #define PCINT9_REG PCMSK1
00842 #define PCINT10_REG PCMSK1
00843 #define PCINT11_REG PCMSK1
00844 #define PCINT12_REG PCMSK1
00845 #define PCINT13_REG PCMSK1
00846 #define PCINT14_REG PCMSK1
00847 #define PCINT15_REG PCMSK1
00848
00849
00850 #define PCINT16_REG PCMSK2
00851 #define PCINT17_REG PCMSK2
00852 #define PCINT18_REG PCMSK2
00853 #define PCINT19_REG PCMSK2
00854 #define PCINT20_REG PCMSK2
00855 #define PCINT21_REG PCMSK2
00856 #define PCINT22_REG PCMSK2
00857 #define PCINT23_REG PCMSK2
00858
00859
00860 #define PCINT24_REG PCMSK3
00861 #define PCINT25_REG PCMSK3
00862 #define PCINT26_REG PCMSK3
00863 #define PCINT27_REG PCMSK3
00864 #define PCINT28_REG PCMSK3
00865 #define PCINT29_REG PCMSK3
00866 #define PCINT30_REG PCMSK3
00867
00868
00869 #define TCNT1L0_REG TCNT1L
00870 #define TCNT1L1_REG TCNT1L
00871 #define TCNT1L2_REG TCNT1L
00872 #define TCNT1L3_REG TCNT1L
00873 #define TCNT1L4_REG TCNT1L
00874 #define TCNT1L5_REG TCNT1L
00875 #define TCNT1L6_REG TCNT1L
00876 #define TCNT1L7_REG TCNT1L
00877
00878
00879 #define PINB0_REG PINB
00880 #define PINB1_REG PINB
00881 #define PINB2_REG PINB
00882 #define PINB3_REG PINB
00883 #define PINB4_REG PINB
00884 #define PINB5_REG PINB
00885 #define PINB6_REG PINB
00886 #define PINB7_REG PINB
00887
00888
00889 #define INTF0_REG EIFR
00890 #define PCIF0_REG EIFR
00891 #define PCIF1_REG EIFR
00892 #define PCIF2_REG EIFR
00893 #define PCIF3_REG EIFR
00894
00895
00896 #define PING0_REG PING
00897 #define PING1_REG PING
00898 #define PING2_REG PING
00899 #define PING3_REG PING
00900 #define PING4_REG PING
00901 #define PING5_REG PING
00902
00903
00904 #define PINF0_REG PINF
00905 #define PINF1_REG PINF
00906 #define PINF2_REG PINF
00907 #define PINF3_REG PINF
00908 #define PINF4_REG PINF
00909 #define PINF5_REG PINF
00910 #define PINF6_REG PINF
00911 #define PINF7_REG PINF
00912
00913
00914 #define PINE0_REG PINE
00915 #define PINE1_REG PINE
00916 #define PINE2_REG PINE
00917 #define PINE3_REG PINE
00918 #define PINE4_REG PINE
00919 #define PINE5_REG PINE
00920 #define PINE6_REG PINE
00921 #define PINE7_REG PINE
00922
00923
00924 #define PIND0_REG PIND
00925 #define PIND1_REG PIND
00926 #define PIND2_REG PIND
00927 #define PIND3_REG PIND
00928 #define PIND4_REG PIND
00929 #define PIND5_REG PIND
00930 #define PIND6_REG PIND
00931 #define PIND7_REG PIND
00932
00933
00934 #define OCR1AH0_REG OCR1AH
00935 #define OCR1AH1_REG OCR1AH
00936 #define OCR1AH2_REG OCR1AH
00937 #define OCR1AH3_REG OCR1AH
00938 #define OCR1AH4_REG OCR1AH
00939 #define OCR1AH5_REG OCR1AH
00940 #define OCR1AH6_REG OCR1AH
00941 #define OCR1AH7_REG OCR1AH
00942
00943
00944 #define OCR1AL0_REG OCR1AL
00945 #define OCR1AL1_REG OCR1AL
00946 #define OCR1AL2_REG OCR1AL
00947 #define OCR1AL3_REG OCR1AL
00948 #define OCR1AL4_REG OCR1AL
00949 #define OCR1AL5_REG OCR1AL
00950 #define OCR1AL6_REG OCR1AL
00951 #define OCR1AL7_REG OCR1AL
00952
00953
00954 #define SPR0_REG SPCR
00955 #define SPR1_REG SPCR
00956 #define CPHA_REG SPCR
00957 #define CPOL_REG SPCR
00958 #define MSTR_REG SPCR
00959 #define DORD_REG SPCR
00960 #define SPE_REG SPCR
00961 #define SPIE_REG SPCR
00962
00963
00964 #define USIDR0_REG USIDR
00965 #define USIDR1_REG USIDR
00966 #define USIDR2_REG USIDR
00967 #define USIDR3_REG USIDR
00968 #define USIDR4_REG USIDR
00969 #define USIDR5_REG USIDR
00970 #define USIDR6_REG USIDR
00971 #define USIDR7_REG USIDR
00972
00973
00974