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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_FALL 6
00092 #define TIMER3_PRESCALER_DIV_RISE 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 -1
00101 #define TIMER3_PRESCALER_REG_7 -2
00102
00103
00104 #define TIMER4_PRESCALER_DIV_0 0
00105 #define TIMER4_PRESCALER_DIV_1 1
00106 #define TIMER4_PRESCALER_DIV_8 2
00107 #define TIMER4_PRESCALER_DIV_64 3
00108 #define TIMER4_PRESCALER_DIV_256 4
00109 #define TIMER4_PRESCALER_DIV_1024 5
00110 #define TIMER4_PRESCALER_DIV_FALL 6
00111 #define TIMER4_PRESCALER_DIV_RISE 7
00112
00113 #define TIMER4_PRESCALER_REG_0 0
00114 #define TIMER4_PRESCALER_REG_1 1
00115 #define TIMER4_PRESCALER_REG_2 8
00116 #define TIMER4_PRESCALER_REG_3 64
00117 #define TIMER4_PRESCALER_REG_4 256
00118 #define TIMER4_PRESCALER_REG_5 1024
00119 #define TIMER4_PRESCALER_REG_6 -1
00120 #define TIMER4_PRESCALER_REG_7 -2
00121
00122
00123 #define TIMER5_PRESCALER_DIV_0 0
00124 #define TIMER5_PRESCALER_DIV_1 1
00125 #define TIMER5_PRESCALER_DIV_8 2
00126 #define TIMER5_PRESCALER_DIV_64 3
00127 #define TIMER5_PRESCALER_DIV_256 4
00128 #define TIMER5_PRESCALER_DIV_1024 5
00129 #define TIMER5_PRESCALER_DIV_FALL 6
00130 #define TIMER5_PRESCALER_DIV_RISE 7
00131
00132 #define TIMER5_PRESCALER_REG_0 0
00133 #define TIMER5_PRESCALER_REG_1 1
00134 #define TIMER5_PRESCALER_REG_2 8
00135 #define TIMER5_PRESCALER_REG_3 64
00136 #define TIMER5_PRESCALER_REG_4 256
00137 #define TIMER5_PRESCALER_REG_5 1024
00138 #define TIMER5_PRESCALER_REG_6 -1
00139 #define TIMER5_PRESCALER_REG_7 -2
00140
00141
00142
00143 #define TIMER0_AVAILABLE
00144 #define TIMER0A_AVAILABLE
00145 #define TIMER0B_AVAILABLE
00146 #define TIMER1_AVAILABLE
00147 #define TIMER1A_AVAILABLE
00148 #define TIMER1B_AVAILABLE
00149 #define TIMER1C_AVAILABLE
00150 #define TIMER2_AVAILABLE
00151 #define TIMER2A_AVAILABLE
00152 #define TIMER2B_AVAILABLE
00153 #define TIMER3_AVAILABLE
00154 #define TIMER3A_AVAILABLE
00155 #define TIMER3B_AVAILABLE
00156 #define TIMER3C_AVAILABLE
00157 #define TIMER4_AVAILABLE
00158 #define TIMER4A_AVAILABLE
00159 #define TIMER4B_AVAILABLE
00160 #define TIMER4C_AVAILABLE
00161 #define TIMER5_AVAILABLE
00162 #define TIMER5A_AVAILABLE
00163 #define TIMER5B_AVAILABLE
00164 #define TIMER5C_AVAILABLE
00165
00166
00167 #define SIG_OVERFLOW0_NUM 0
00168 #define SIG_OVERFLOW1_NUM 1
00169 #define SIG_OVERFLOW2_NUM 2
00170 #define SIG_OVERFLOW3_NUM 3
00171 #define SIG_OVERFLOW4_NUM 4
00172 #define SIG_OVERFLOW5_NUM 5
00173 #define SIG_OVERFLOW_TOTAL_NUM 6
00174
00175
00176 #define SIG_OUTPUT_COMPARE0A_NUM 0
00177 #define SIG_OUTPUT_COMPARE0B_NUM 1
00178 #define SIG_OUTPUT_COMPARE1A_NUM 2
00179 #define SIG_OUTPUT_COMPARE1B_NUM 3
00180 #define SIG_OUTPUT_COMPARE1C_NUM 4
00181 #define SIG_OUTPUT_COMPARE2A_NUM 5
00182 #define SIG_OUTPUT_COMPARE2B_NUM 6
00183 #define SIG_OUTPUT_COMPARE3A_NUM 7
00184 #define SIG_OUTPUT_COMPARE3B_NUM 8
00185 #define SIG_OUTPUT_COMPARE3C_NUM 9
00186 #define SIG_OUTPUT_COMPARE4A_NUM 10
00187 #define SIG_OUTPUT_COMPARE4B_NUM 11
00188 #define SIG_OUTPUT_COMPARE4C_NUM 12
00189 #define SIG_OUTPUT_COMPARE5A_NUM 13
00190 #define SIG_OUTPUT_COMPARE5B_NUM 14
00191 #define SIG_OUTPUT_COMPARE5C_NUM 15
00192 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
00193
00194
00195 #define PWM0A_NUM 0
00196 #define PWM0B_NUM 1
00197 #define PWM1A_NUM 2
00198 #define PWM1B_NUM 3
00199 #define PWM1C_NUM 4
00200 #define PWM2A_NUM 5
00201 #define PWM2B_NUM 6
00202 #define PWM3A_NUM 7
00203 #define PWM3B_NUM 8
00204 #define PWM3C_NUM 9
00205 #define PWM4A_NUM 10
00206 #define PWM4B_NUM 11
00207 #define PWM4C_NUM 12
00208 #define PWM5A_NUM 13
00209 #define PWM5B_NUM 14
00210 #define PWM5C_NUM 15
00211 #define PWM_TOTAL_NUM 16
00212
00213
00214 #define SIG_INPUT_CAPTURE1_NUM 0
00215 #define SIG_INPUT_CAPTURE3_NUM 1
00216 #define SIG_INPUT_CAPTURE4_NUM 2
00217 #define SIG_INPUT_CAPTURE5_NUM 3
00218 #define SIG_INPUT_CAPTURE_TOTAL_NUM 4
00219
00220
00221
00222 #define OCROA_0_REG OCR0A
00223 #define OCROA_1_REG OCR0A
00224 #define OCROA_2_REG OCR0A
00225 #define OCROA_3_REG OCR0A
00226 #define OCROA_4_REG OCR0A
00227 #define OCROA_5_REG OCR0A
00228 #define OCROA_6_REG OCR0A
00229 #define OCROA_7_REG OCR0A
00230
00231
00232 #define MUX0_REG ADMUX
00233 #define MUX1_REG ADMUX
00234 #define MUX2_REG ADMUX
00235 #define MUX3_REG ADMUX
00236 #define MUX4_REG ADMUX
00237 #define ADLAR_REG ADMUX
00238 #define REFS0_REG ADMUX
00239 #define REFS1_REG ADMUX
00240
00241
00242 #define WDP0_REG WDTCSR
00243 #define WDP1_REG WDTCSR
00244 #define WDP2_REG WDTCSR
00245 #define WDE_REG WDTCSR
00246 #define WDCE_REG WDTCSR
00247 #define WDP3_REG WDTCSR
00248 #define WDIE_REG WDTCSR
00249 #define WDIF_REG WDTCSR
00250
00251
00252 #define EEDR0_REG EEDR
00253 #define EEDR1_REG EEDR
00254 #define EEDR2_REG EEDR
00255 #define EEDR3_REG EEDR
00256 #define EEDR4_REG EEDR
00257 #define EEDR5_REG EEDR
00258 #define EEDR6_REG EEDR
00259 #define EEDR7_REG EEDR
00260
00261
00262 #define ACIS0_REG ACSR
00263 #define ACIS1_REG ACSR
00264 #define ACIC_REG ACSR
00265 #define ACIE_REG ACSR
00266 #define ACI_REG ACSR
00267 #define ACO_REG ACSR
00268 #define ACBG_REG ACSR
00269 #define ACD_REG ACSR
00270
00271
00272 #define RAMPZ0_REG RAMPZ
00273 #define RAMPZ1_REG RAMPZ
00274
00275
00276 #define OCR2B_0_REG OCR2B
00277 #define OCR2B_1_REG OCR2B
00278 #define OCR2B_2_REG OCR2B
00279 #define OCR2B_3_REG OCR2B
00280 #define OCR2B_4_REG OCR2B
00281 #define OCR2B_5_REG OCR2B
00282 #define OCR2B_6_REG OCR2B
00283 #define OCR2B_7_REG OCR2B
00284
00285
00286 #define OCR2A_0_REG OCR2A
00287 #define OCR2A_1_REG OCR2A
00288 #define OCR2A_2_REG OCR2A
00289 #define OCR2A_3_REG OCR2A
00290 #define OCR2A_4_REG OCR2A
00291 #define OCR2A_5_REG OCR2A
00292 #define OCR2A_6_REG OCR2A
00293 #define OCR2A_7_REG OCR2A
00294
00295
00296 #define SPDR0_REG SPDR
00297 #define SPDR1_REG SPDR
00298 #define SPDR2_REG SPDR
00299 #define SPDR3_REG SPDR
00300 #define SPDR4_REG SPDR
00301 #define SPDR5_REG SPDR
00302 #define SPDR6_REG SPDR
00303 #define SPDR7_REG SPDR
00304
00305
00306 #define SPI2X_REG SPSR
00307 #define WCOL_REG SPSR
00308 #define SPIF_REG SPSR
00309
00310
00311 #define ICR1H0_REG ICR1H
00312 #define ICR1H1_REG ICR1H
00313 #define ICR1H2_REG ICR1H
00314 #define ICR1H3_REG ICR1H
00315 #define ICR1H4_REG ICR1H
00316 #define ICR1H5_REG ICR1H
00317 #define ICR1H6_REG ICR1H
00318 #define ICR1H7_REG ICR1H
00319
00320
00321 #define ICR1L0_REG ICR1L
00322 #define ICR1L1_REG ICR1L
00323 #define ICR1L2_REG ICR1L
00324 #define ICR1L3_REG ICR1L
00325 #define ICR1L4_REG ICR1L
00326 #define ICR1L5_REG ICR1L
00327 #define ICR1L6_REG ICR1L
00328 #define ICR1L7_REG ICR1L
00329
00330
00331 #define EEAR8_REG EEARH
00332 #define EEAR9_REG EEARH
00333 #define EEAR10_REG EEARH
00334 #define EEAR11_REG EEARH
00335
00336
00337 #define TCNT1L0_REG TCNT1L
00338 #define TCNT1L1_REG TCNT1L
00339 #define TCNT1L2_REG TCNT1L
00340 #define TCNT1L3_REG TCNT1L
00341 #define TCNT1L4_REG TCNT1L
00342 #define TCNT1L5_REG TCNT1L
00343 #define TCNT1L6_REG TCNT1L
00344 #define TCNT1L7_REG TCNT1L
00345
00346
00347 #define PORTG0_REG PORTG
00348 #define PORTG1_REG PORTG
00349 #define PORTG2_REG PORTG
00350 #define PORTG3_REG PORTG
00351 #define PORTG4_REG PORTG
00352 #define PORTG5_REG PORTG
00353
00354
00355 #define UCPOL0_REG UCSR0C
00356 #define UCSZ00_REG UCSR0C
00357 #define UCSZ01_REG UCSR0C
00358 #define USBS0_REG UCSR0C
00359 #define UPM00_REG UCSR0C
00360 #define UPM01_REG UCSR0C
00361 #define UMSEL00_REG UCSR0C
00362 #define UMSEL01_REG UCSR0C
00363
00364
00365 #define TXB80_REG UCSR0B
00366 #define RXB80_REG UCSR0B
00367 #define UCSZ02_REG UCSR0B
00368 #define TXEN0_REG UCSR0B
00369 #define RXEN0_REG UCSR0B
00370 #define UDRIE0_REG UCSR0B
00371 #define TXCIE0_REG UCSR0B
00372 #define RXCIE0_REG UCSR0B
00373
00374
00375 #define TCNT1H0_REG TCNT1H
00376 #define TCNT1H1_REG TCNT1H
00377 #define TCNT1H2_REG TCNT1H
00378 #define TCNT1H3_REG TCNT1H
00379 #define TCNT1H4_REG TCNT1H
00380 #define TCNT1H5_REG TCNT1H
00381 #define TCNT1H6_REG TCNT1H
00382 #define TCNT1H7_REG TCNT1H
00383
00384
00385 #define PORTC0_REG PORTC
00386 #define PORTC1_REG PORTC
00387 #define PORTC2_REG PORTC
00388 #define PORTC3_REG PORTC
00389 #define PORTC4_REG PORTC
00390 #define PORTC5_REG PORTC
00391 #define PORTC6_REG PORTC
00392 #define PORTC7_REG PORTC
00393
00394
00395 #define PORTA0_REG PORTA
00396 #define PORTA1_REG PORTA
00397 #define PORTA2_REG PORTA
00398 #define PORTA3_REG PORTA
00399 #define PORTA4_REG PORTA
00400 #define PORTA5_REG PORTA
00401 #define PORTA6_REG PORTA
00402 #define PORTA7_REG PORTA
00403
00404
00405 #define GPIOR10_REG GPIOR1
00406 #define GPIOR11_REG GPIOR1
00407 #define GPIOR12_REG GPIOR1
00408 #define GPIOR13_REG GPIOR1
00409 #define GPIOR14_REG GPIOR1
00410 #define GPIOR15_REG GPIOR1
00411 #define GPIOR16_REG GPIOR1
00412 #define GPIOR17_REG GPIOR1
00413
00414
00415 #define INT0_REG EIMSK
00416 #define INT1_REG EIMSK
00417 #define INT2_REG EIMSK
00418 #define INT3_REG EIMSK
00419 #define INT4_REG EIMSK
00420 #define INT5_REG EIMSK
00421 #define INT6_REG EIMSK
00422 #define INT7_REG EIMSK
00423
00424
00425 #define UDR1_0_REG UDR1
00426 #define UDR1_1_REG UDR1
00427 #define UDR1_2_REG UDR1
00428 #define UDR1_3_REG UDR1
00429 #define UDR1_4_REG UDR1
00430 #define UDR1_5_REG UDR1
00431 #define UDR1_6_REG UDR1
00432 #define UDR1_7_REG UDR1
00433
00434
00435 #define UDR0_0_REG UDR0
00436 #define UDR0_1_REG UDR0
00437 #define UDR0_2_REG UDR0
00438 #define UDR0_3_REG UDR0
00439 #define UDR0_4_REG UDR0
00440 #define UDR0_5_REG UDR0
00441 #define UDR0_6_REG UDR0
00442 #define UDR0_7_REG UDR0
00443
00444
00445 #define ISC40_REG EICRB
00446 #define ISC41_REG EICRB
00447 #define ISC50_REG EICRB
00448 #define ISC51_REG EICRB
00449 #define ISC60_REG EICRB
00450 #define ISC61_REG EICRB
00451 #define ISC70_REG EICRB
00452 #define ISC71_REG EICRB
00453
00454
00455 #define ISC00_REG EICRA
00456 #define ISC01_REG EICRA
00457 #define ISC10_REG EICRA
00458 #define ISC11_REG EICRA
00459 #define ISC20_REG EICRA
00460 #define ISC21_REG EICRA
00461 #define ISC30_REG EICRA
00462 #define ISC31_REG EICRA
00463
00464
00465 #define ADC0D_REG DIDR0
00466 #define ADC1D_REG DIDR0
00467 #define ADC2D_REG DIDR0
00468 #define ADC3D_REG DIDR0
00469 #define ADC4D_REG DIDR0
00470 #define ADC5D_REG DIDR0
00471 #define ADC6D_REG DIDR0
00472 #define ADC7D_REG DIDR0
00473
00474
00475 #define AIN0D_REG DIDR1
00476 #define AIN1D_REG DIDR1
00477
00478
00479 #define ADC8D_REG DIDR2
00480 #define ADC9D_REG DIDR2
00481 #define ADC10D_REG DIDR2
00482 #define ADC11D_REG DIDR2
00483 #define ADC12D_REG DIDR2
00484 #define ADC13D_REG DIDR2
00485 #define ADC14D_REG DIDR2
00486 #define ADC15D_REG DIDR2
00487
00488
00489 #define DDF0_REG DDRF
00490 #define DDF1_REG DDRF
00491 #define DDF2_REG DDRF
00492 #define DDF3_REG DDRF
00493 #define DDF4_REG DDRF
00494 #define DDF5_REG DDRF
00495 #define DDF6_REG DDRF
00496 #define DDF7_REG DDRF
00497
00498
00499 #define TCR2BUB_REG ASSR
00500 #define TCR2AUB_REG ASSR
00501 #define OCR2BUB_REG ASSR
00502 #define OCR2AUB_REG ASSR
00503 #define TCN2UB_REG ASSR
00504 #define AS2_REG ASSR
00505 #define EXCLK_REG ASSR
00506
00507
00508 #define CLKPS0_REG CLKPR
00509 #define CLKPS1_REG CLKPR
00510 #define CLKPS2_REG CLKPR
00511 #define CLKPS3_REG CLKPR
00512 #define CLKPCE_REG CLKPR
00513
00514
00515 #define OCR0B_0_REG OCR0B
00516 #define OCR0B_1_REG OCR0B
00517 #define OCR0B_2_REG OCR0B
00518 #define OCR0B_3_REG OCR0B
00519 #define OCR0B_4_REG OCR0B
00520 #define OCR0B_5_REG OCR0B
00521 #define OCR0B_6_REG OCR0B
00522 #define OCR0B_7_REG OCR0B
00523
00524
00525 #define C_REG SREG
00526 #define Z_REG SREG
00527 #define N_REG SREG
00528 #define V_REG SREG
00529 #define S_REG SREG
00530 #define H_REG SREG
00531 #define T_REG SREG
00532 #define I_REG SREG
00533
00534
00535 #define UBRR_0_REG UBRR1L
00536 #define UBRR_1_REG UBRR1L
00537 #define UBRR_2_REG UBRR1L
00538 #define UBRR_3_REG UBRR1L
00539 #define UBRR_4_REG UBRR1L
00540 #define UBRR_5_REG UBRR1L
00541 #define UBRR_6_REG UBRR1L
00542 #define UBRR_7_REG UBRR1L
00543
00544
00545 #define DDC0_REG DDRC
00546 #define DDC1_REG DDRC
00547 #define DDC2_REG DDRC
00548 #define DDC3_REG DDRC
00549 #define DDC4_REG DDRC
00550 #define DDC5_REG DDRC
00551 #define DDC6_REG DDRC
00552 #define DDC7_REG DDRC
00553
00554
00555 #define OCR3AL0_REG OCR3AL
00556 #define OCR3AL1_REG OCR3AL
00557 #define OCR3AL2_REG OCR3AL
00558 #define OCR3AL3_REG OCR3AL
00559 #define OCR3AL4_REG OCR3AL
00560 #define OCR3AL5_REG OCR3AL
00561 #define OCR3AL6_REG OCR3AL
00562 #define OCR3AL7_REG OCR3AL
00563
00564
00565 #define DDA0_REG DDRA
00566 #define DDA1_REG DDRA
00567 #define DDA2_REG DDRA
00568 #define DDA3_REG DDRA
00569 #define DDA4_REG DDRA
00570 #define DDA5_REG DDRA
00571 #define DDA6_REG DDRA
00572 #define DDA7_REG DDRA
00573
00574
00575 #define UBRR_8_REG UBRR1H
00576 #define UBRR_9_REG UBRR1H
00577 #define UBRR_10_REG UBRR1H
00578 #define UBRR_11_REG UBRR1H
00579
00580
00581 #define DDG0_REG DDRG
00582 #define DDG1_REG DDRG
00583 #define DDG2_REG DDRG
00584 #define DDG3_REG DDRG
00585 #define DDG4_REG DDRG
00586 #define DDG5_REG DDRG
00587
00588
00589 #define OCR3AH0_REG OCR3AH
00590 #define OCR3AH1_REG OCR3AH
00591 #define OCR3AH2_REG OCR3AH
00592 #define OCR3AH3_REG OCR3AH
00593 #define OCR3AH4_REG OCR3AH
00594 #define OCR3AH5_REG OCR3AH
00595 #define OCR3AH6_REG OCR3AH
00596 #define OCR3AH7_REG OCR3AH
00597
00598
00599 #define CS10_REG TCCR1B
00600 #define CS11_REG TCCR1B
00601 #define CS12_REG TCCR1B
00602 #define WGM12_REG TCCR1B
00603 #define WGM13_REG TCCR1B
00604 #define ICES1_REG TCCR1B
00605 #define ICNC1_REG TCCR1B
00606
00607
00608 #define CAL0_REG OSCCAL
00609 #define CAL1_REG OSCCAL
00610 #define CAL2_REG OSCCAL
00611 #define CAL3_REG OSCCAL
00612 #define CAL4_REG OSCCAL
00613 #define CAL5_REG OSCCAL
00614 #define CAL6_REG OSCCAL
00615 #define CAL7_REG OSCCAL
00616
00617
00618 #define DDD0_REG DDRD
00619 #define DDD1_REG DDRD
00620 #define DDD2_REG DDRD
00621 #define DDD3_REG DDRD
00622 #define DDD4_REG DDRD
00623 #define DDD5_REG DDRD
00624 #define DDD6_REG DDRD
00625 #define DDD7_REG DDRD
00626
00627
00628 #define TCNT5H0_REG TCNT5H
00629 #define TCNT5H1_REG TCNT5H
00630 #define TCNT5H2_REG TCNT5H
00631 #define TCNT5H3_REG TCNT5H
00632 #define TCNT5H4_REG TCNT5H
00633 #define TCNT5H5_REG TCNT5H
00634 #define TCNT5H6_REG TCNT5H
00635 #define TCNT5H7_REG TCNT5H
00636
00637
00638 #define GPIOR00_REG GPIOR0
00639 #define GPIOR01_REG GPIOR0
00640 #define GPIOR02_REG GPIOR0
00641 #define GPIOR03_REG GPIOR0
00642 #define GPIOR04_REG GPIOR0
00643 #define GPIOR05_REG GPIOR0
00644 #define GPIOR06_REG GPIOR0
00645 #define GPIOR07_REG GPIOR0
00646
00647
00648 #define GPIOR20_REG GPIOR2
00649 #define GPIOR21_REG GPIOR2
00650 #define GPIOR22_REG GPIOR2
00651 #define GPIOR23_REG GPIOR2
00652 #define GPIOR24_REG GPIOR2
00653 #define GPIOR25_REG GPIOR2
00654 #define GPIOR26_REG GPIOR2
00655 #define GPIOR27_REG GPIOR2
00656
00657
00658 #define TCNT5L0_REG TCNT5L
00659 #define TCNT5L1_REG TCNT5L
00660 #define TCNT5L2_REG TCNT5L
00661 #define TCNT5L3_REG TCNT5L
00662 #define TCNT5L4_REG TCNT5L
00663 #define TCNT5L5_REG TCNT5L
00664 #define TCNT5L6_REG TCNT5L
00665 #define TCNT5L7_REG TCNT5L
00666
00667
00668 #define PCIE0_REG PCICR
00669 #define PCIE1_REG PCICR
00670 #define PCIE2_REG PCICR
00671
00672
00673 #define TCNT2_0_REG TCNT2
00674 #define TCNT2_1_REG TCNT2
00675 #define TCNT2_2_REG TCNT2
00676 #define TCNT2_3_REG TCNT2
00677 #define TCNT2_4_REG TCNT2
00678 #define TCNT2_5_REG TCNT2
00679 #define TCNT2_6_REG TCNT2
00680 #define TCNT2_7_REG TCNT2
00681
00682
00683 #define TCNT0_0_REG TCNT0
00684 #define TCNT0_1_REG TCNT0
00685 #define TCNT0_2_REG TCNT0
00686 #define TCNT0_3_REG TCNT0
00687 #define TCNT0_4_REG TCNT0
00688 #define TCNT0_5_REG TCNT0
00689 #define TCNT0_6_REG TCNT0
00690 #define TCNT0_7_REG TCNT0
00691
00692
00693 #define TWGCE_REG TWAR
00694 #define TWA0_REG TWAR
00695 #define TWA1_REG TWAR
00696 #define TWA2_REG TWAR
00697 #define TWA3_REG TWAR
00698 #define TWA4_REG TWAR
00699 #define TWA5_REG TWAR
00700 #define TWA6_REG TWAR
00701
00702
00703 #define CS00_REG TCCR0B
00704 #define CS01_REG TCCR0B
00705 #define CS02_REG TCCR0B
00706 #define WGM02_REG TCCR0B
00707 #define FOC0B_REG TCCR0B
00708 #define FOC0A_REG TCCR0B
00709
00710
00711 #define WGM00_REG TCCR0A
00712 #define WGM01_REG TCCR0A
00713 #define COM0B0_REG TCCR0A
00714 #define COM0B1_REG TCCR0A
00715 #define COM0A0_REG TCCR0A
00716 #define COM0A1_REG TCCR0A
00717
00718
00719 #define TOV4_REG TIFR4
00720 #define OCF4A_REG TIFR4
00721 #define OCF4B_REG TIFR4
00722 #define OCF4C_REG TIFR4
00723 #define ICF4_REG TIFR4
00724
00725
00726 #define TOV5_REG TIFR5
00727 #define OCF5A_REG TIFR5
00728 #define OCF5B_REG TIFR5
00729 #define OCF5C_REG TIFR5
00730 #define ICF5_REG TIFR5
00731
00732
00733 #define TOV2_REG TIFR2
00734 #define OCF2A_REG TIFR2
00735 #define OCF2B_REG TIFR2
00736
00737
00738 #define TOV3_REG TIFR3
00739 #define OCF3A_REG TIFR3
00740 #define OCF3B_REG TIFR3
00741 #define OCF3C_REG TIFR3
00742 #define ICF3_REG TIFR3
00743
00744
00745 #define SPR0_REG SPCR
00746 #define SPR1_REG SPCR
00747 #define CPHA_REG SPCR
00748 #define CPOL_REG SPCR
00749 #define MSTR_REG SPCR
00750 #define DORD_REG SPCR
00751 #define SPE_REG SPCR
00752 #define SPIE_REG SPCR
00753
00754
00755 #define TOV1_REG TIFR1
00756 #define OCF1A_REG TIFR1
00757 #define OCF1B_REG TIFR1
00758 #define OCF1C_REG TIFR1
00759 #define ICF1_REG TIFR1
00760
00761
00762 #define OCR4AH0_REG OCR4AH
00763 #define OCR4AH1_REG OCR4AH
00764 #define OCR4AH2_REG OCR4AH
00765 #define OCR4AH3_REG OCR4AH
00766 #define OCR4AH4_REG OCR4AH
00767 #define OCR4AH5_REG OCR4AH
00768 #define OCR4AH6_REG OCR4AH
00769 #define OCR4AH7_REG OCR4AH
00770
00771
00772 #define OCR5CH0_REG OCR5CH
00773 #define OCR5CH1_REG OCR5CH
00774 #define OCR5CH2_REG OCR5CH
00775 #define OCR5CH3_REG OCR5CH
00776 #define OCR5CH4_REG OCR5CH
00777 #define OCR5CH5_REG OCR5CH
00778 #define OCR5CH6_REG OCR5CH
00779 #define OCR5CH7_REG OCR5CH
00780
00781
00782 #define OCR4AL0_REG OCR4AL
00783 #define OCR4AL1_REG OCR4AL
00784 #define OCR4AL2_REG OCR4AL
00785 #define OCR4AL3_REG OCR4AL
00786 #define OCR4AL4_REG OCR4AL
00787 #define OCR4AL5_REG OCR4AL
00788 #define OCR4AL6_REG OCR4AL
00789 #define OCR4AL7_REG OCR4AL
00790
00791
00792 #define OCR5CL0_REG OCR5CL
00793 #define OCR5CL1_REG OCR5CL
00794 #define OCR5CL2_REG OCR5CL
00795 #define OCR5CL3_REG OCR5CL
00796 #define OCR5CL4_REG OCR5CL
00797 #define OCR5CL5_REG OCR5CL
00798 #define OCR5CL6_REG OCR5CL
00799 #define OCR5CL7_REG OCR5CL
00800
00801
00802 #define OCR3CH0_REG OCR3CH
00803 #define OCR3CH1_REG OCR3CH
00804 #define OCR3CH2_REG OCR3CH
00805 #define OCR3CH3_REG OCR3CH
00806 #define OCR3CH4_REG OCR3CH
00807 #define OCR3CH5_REG OCR3CH
00808 #define OCR3CH6_REG OCR3CH
00809 #define OCR3CH7_REG OCR3CH
00810
00811
00812 #define OCR3CL0_REG OCR3CL
00813 #define OCR3CL1_REG OCR3CL
00814 #define OCR3CL2_REG OCR3CL
00815 #define OCR3CL3_REG OCR3CL
00816 #define OCR3CL4_REG OCR3CL
00817 #define OCR3CL5_REG OCR3CL
00818 #define OCR3CL6_REG OCR3CL
00819 #define OCR3CL7_REG OCR3CL
00820
00821
00822 #define PSRSYNC_REG GTCCR
00823 #define TSM_REG GTCCR
00824 #define PSRASY_REG GTCCR
00825
00826
00827 #define TWBR0_REG TWBR
00828 #define TWBR1_REG TWBR
00829 #define TWBR2_REG TWBR
00830 #define TWBR3_REG TWBR
00831 #define TWBR4_REG TWBR
00832 #define TWBR5_REG TWBR
00833 #define TWBR6_REG TWBR
00834 #define TWBR7_REG TWBR
00835
00836
00837 #define SP8_REG SPH
00838 #define SP9_REG SPH
00839 #define SP10_REG SPH
00840 #define SP11_REG SPH
00841 #define SP12_REG SPH
00842 #define SP13_REG SPH
00843 #define SP14_REG SPH
00844 #define SP15_REG SPH
00845
00846
00847 #define FOC3C_REG TCCR3C
00848 #define FOC3B_REG TCCR3C
00849 #define FOC3A_REG TCCR3C
00850
00851
00852 #define CS30_REG TCCR3B
00853 #define CS31_REG TCCR3B
00854 #define CS32_REG TCCR3B
00855 #define WGM32_REG TCCR3B
00856 #define WGM33_REG TCCR3B
00857 #define ICES3_REG TCCR3B
00858 #define ICNC3_REG TCCR3B
00859
00860
00861 #define WGM30_REG TCCR3A
00862 #define WGM31_REG TCCR3A
00863 #define COM3C0_REG TCCR3A
00864 #define COM3C1_REG TCCR3A
00865 #define COM3B0_REG TCCR3A
00866 #define COM3B1_REG TCCR3A
00867 #define COM3A0_REG TCCR3A
00868 #define COM3A1_REG TCCR3A
00869
00870
00871 #define PORTF0_REG PORTF
00872 #define PORTF1_REG PORTF
00873 #define PORTF2_REG PORTF
00874 #define PORTF3_REG PORTF
00875 #define PORTF4_REG PORTF
00876 #define PORTF5_REG PORTF
00877 #define PORTF6_REG PORTF
00878 #define PORTF7_REG PORTF
00879
00880
00881 #define PCINT8_REG PCMSK1
00882 #define PCINT9_REG PCMSK1
00883 #define PCINT10_REG PCMSK1
00884 #define PCINT11_REG PCMSK1
00885 #define PCINT12_REG PCMSK1
00886 #define PCINT13_REG PCMSK1
00887 #define PCINT14_REG PCMSK1
00888 #define PCINT15_REG PCMSK1
00889
00890
00891 #define OCR1BL0_REG OCR1BL
00892 #define OCR1BL1_REG OCR1BL
00893 #define OCR1BL2_REG OCR1BL
00894 #define OCR1BL3_REG OCR1BL
00895 #define OCR1BL4_REG OCR1BL
00896 #define OCR1BL5_REG OCR1BL
00897 #define OCR1BL6_REG OCR1BL
00898 #define OCR1BL7_REG OCR1BL
00899
00900
00901 #define TCNT3H0_REG TCNT3H
00902 #define TCNT3H1_REG TCNT3H
00903 #define TCNT3H2_REG TCNT3H
00904 #define TCNT3H3_REG TCNT3H
00905 #define TCNT3H4_REG TCNT3H
00906 #define TCNT3H5_REG TCNT3H
00907 #define TCNT3H6_REG TCNT3H
00908 #define TCNT3H7_REG TCNT3H
00909
00910
00911 #define OCR1BH0_REG OCR1BH
00912 #define OCR1BH1_REG OCR1BH
00913 #define OCR1BH2_REG OCR1BH
00914 #define OCR1BH3_REG OCR1BH
00915 #define OCR1BH4_REG OCR1BH
00916 #define OCR1BH5_REG OCR1BH
00917 #define OCR1BH6_REG OCR1BH
00918 #define OCR1BH7_REG OCR1BH
00919
00920
00921 #define TCNT3L0_REG TCNT3L
00922 #define TCNT3L1_REG TCNT3L
00923 #define TCNT3L2_REG TCNT3L
00924 #define TCNT3L3_REG TCNT3L
00925 #define TCNT3L4_REG TCNT3L
00926 #define TCNT3L5_REG TCNT3L
00927 #define TCNT3L6_REG TCNT3L
00928 #define TCNT3L7_REG TCNT3L
00929
00930
00931 #define ICR5L0_REG ICR5L
00932 #define ICR5L1_REG ICR5L
00933 #define ICR5L2_REG ICR5L
00934 #define ICR5L3_REG ICR5L
00935 #define ICR5L4_REG ICR5L
00936 #define ICR5L5_REG ICR5L
00937 #define ICR5L6_REG ICR5L
00938 #define ICR5L7_REG ICR5L
00939
00940
00941 #define SP0_REG SPL
00942 #define SP1_REG SPL
00943 #define SP2_REG SPL
00944 #define SP3_REG SPL
00945 #define SP4_REG SPL
00946 #define SP5_REG SPL
00947 #define SP6_REG SPL
00948 #define SP7_REG SPL
00949
00950
00951 #define ICR5H0_REG ICR5H
00952 #define ICR5H1_REG ICR5H
00953 #define ICR5H2_REG ICR5H
00954 #define ICR5H3_REG ICR5H
00955 #define ICR5H4_REG ICR5H
00956 #define ICR5H5_REG ICR5H
00957 #define ICR5H6_REG ICR5H
00958 #define ICR5H7_REG ICR5H
00959
00960
00961 #define JTRF_REG MCUSR
00962 #define PORF_REG MCUSR
00963 #define EXTRF_REG MCUSR
00964 #define BORF_REG MCUSR
00965 #define WDRF_REG MCUSR
00966
00967
00968 #define EERE_REG EECR
00969 #define EEPE_REG EECR
00970 #define EEMPE_REG EECR
00971 #define EERIE_REG EECR
00972 #define EEPM0_REG EECR
00973 #define EEPM1_REG EECR
00974
00975
00976 #define SE_REG SMCR
00977 #define SM0_REG SMCR
00978 #define SM1_REG SMCR
00979 #define SM2_REG SMCR
00980
00981
00982 #define TWIE_REG TWCR
00983 #define TWEN_REG TWCR
00984 #define TWWC_REG TWCR
00985 #define TWSTO_REG TWCR
00986 #define TWSTA_REG TWCR
00987 #define TWEA_REG TWCR
00988 #define TWINT_REG TWCR
00989
00990
00991 #define PCIF0_REG PCIFR
00992 #define PCIF1_REG PCIFR
00993 #define PCIF2_REG PCIFR
00994
00995
00996 #define WGM20_REG TCCR2A
00997 #define WGM21_REG TCCR2A
00998 #define COM2B0_REG TCCR2A
00999 #define COM2B1_REG TCCR2A
01000 #define COM2A0_REG TCCR2A
01001 #define COM2A1_REG TCCR2A
01002
01003
01004 #define CS20_REG TCCR2B
01005 #define CS21_REG TCCR2B
01006 #define CS22_REG TCCR2B
01007 #define WGM22_REG TCCR2B
01008 #define FOC2B_REG TCCR2B
01009 #define FOC2A_REG TCCR2B
01010
01011
01012 #define UBRR8_REG UBRR0H
01013 #define UBRR9_REG UBRR0H
01014 #define UBRR10_REG UBRR0H
01015 #define UBRR11_REG UBRR0H
01016
01017
01018 #define PING0_REG PING
01019 #define PING1_REG PING
01020 #define PING2_REG PING
01021 #define PING3_REG PING
01022 #define PING4_REG PING
01023 #define PING5_REG PING
01024
01025
01026 #define UBRR0_REG UBRR0L
01027 #define UBRR1_REG UBRR0L
01028 #define UBRR2_REG UBRR0L
01029 #define UBRR3_REG UBRR0L
01030 #define UBRR4_REG UBRR0L
01031 #define UBRR5_REG UBRR0L
01032 #define UBRR6_REG UBRR0L
01033 #define UBRR7_REG UBRR0L
01034
01035
01036 #define TWPS0_REG TWSR
01037 #define TWPS1_REG TWSR
01038 #define TWS3_REG TWSR
01039 #define TWS4_REG TWSR
01040 #define TWS5_REG TWSR
01041 #define TWS6_REG TWSR
01042 #define TWS7_REG TWSR
01043
01044
01045 #define ICR4H0_REG ICR4H
01046 #define ICR4H1_REG ICR4H
01047 #define ICR4H2_REG ICR4H
01048 #define ICR4H3_REG ICR4H
01049 #define ICR4H4_REG ICR4H
01050 #define ICR4H5_REG ICR4H
01051 #define ICR4H6_REG ICR4H
01052 #define ICR4H7_REG ICR4H
01053
01054
01055 #define EEAR0_REG EEARL
01056 #define EEAR1_REG EEARL
01057 #define EEAR2_REG EEARL
01058 #define EEAR3_REG EEARL
01059 #define EEAR4_REG EEARL
01060 #define EEAR5_REG EEARL
01061 #define EEAR6_REG EEARL
01062 #define EEAR7_REG EEARL
01063
01064
01065 #define PCINT16_REG PCMSK2
01066 #define PCINT17_REG PCMSK2
01067 #define PCINT18_REG PCMSK2
01068 #define PCINT19_REG PCMSK2
01069 #define PCINT20_REG PCMSK2
01070 #define PCINT21_REG PCMSK2
01071 #define PCINT22_REG PCMSK2
01072 #define PCINT23_REG PCMSK2
01073
01074
01075 #define ICR4L0_REG ICR4L
01076 #define ICR4L1_REG ICR4L
01077 #define ICR4L2_REG ICR4L
01078 #define ICR4L3_REG ICR4L
01079 #define ICR4L4_REG ICR4L
01080 #define ICR4L5_REG ICR4L
01081 #define ICR4L6_REG ICR4L
01082 #define ICR4L7_REG ICR4L
01083
01084
01085 #define JTD_REG MCUCR
01086 #define IVCE_REG MCUCR
01087 #define IVSEL_REG MCUCR
01088 #define PUD_REG MCUCR
01089
01090
01091 #define PINC0_REG PINC
01092 #define PINC1_REG PINC
01093 #define PINC2_REG PINC
01094 #define PINC3_REG PINC
01095 #define PINC4_REG PINC
01096 #define PINC5_REG PINC
01097 #define PINC6_REG PINC
01098 #define PINC7_REG PINC
01099
01100
01101 #define OCR1CL0_REG OCR1CL
01102 #define OCR1CL1_REG OCR1CL
01103 #define OCR1CL2_REG OCR1CL
01104 #define OCR1CL3_REG OCR1CL
01105 #define OCR1CL4_REG OCR1CL
01106 #define OCR1CL5_REG OCR1CL
01107 #define OCR1CL6_REG OCR1CL
01108 #define OCR1CL7_REG OCR1CL
01109
01110
01111 #define TCNT4L0_REG TCNT4L
01112 #define TCNT4L1_REG TCNT4L
01113 #define TCNT4L2_REG TCNT4L
01114 #define TCNT4L3_REG TCNT4L
01115 #define TCNT4L4_REG TCNT4L
01116 #define TCNT4L5_REG TCNT4L
01117 #define TCNT4L6_REG TCNT4L
01118 #define TCNT4L7_REG TCNT4L
01119
01120
01121 #define OCR1CH0_REG OCR1CH
01122 #define OCR1CH1_REG OCR1CH
01123 #define OCR1CH2_REG OCR1CH
01124 #define OCR1CH3_REG OCR1CH
01125 #define OCR1CH4_REG OCR1CH
01126 #define OCR1CH5_REG OCR1CH
01127 #define OCR1CH6_REG OCR1CH
01128 #define OCR1CH7_REG OCR1CH
01129
01130
01131 #define TCNT4H0_REG TCNT4H
01132 #define TCNT4H1_REG TCNT4H
01133 #define TCNT4H2_REG TCNT4H
01134 #define TCNT4H3_REG TCNT4H
01135 #define TCNT4H4_REG TCNT4H
01136 #define TCNT4H5_REG TCNT4H
01137 #define TCNT4H6_REG TCNT4H
01138 #define TCNT4H7_REG TCNT4H
01139
01140
01141 #define OCDR0_REG OCDR
01142 #define OCDR1_REG OCDR
01143 #define OCDR2_REG OCDR
01144 #define OCDR3_REG OCDR
01145 #define OCDR4_REG OCDR
01146 #define OCDR5_REG OCDR
01147 #define OCDR6_REG OCDR
01148 #define OCDR7_REG OCDR
01149
01150
01151 #define PINA0_REG PINA
01152 #define PINA1_REG PINA
01153 #define PINA2_REG PINA
01154 #define PINA3_REG PINA
01155 #define PINA4_REG PINA
01156 #define PINA5_REG PINA
01157 #define PINA6_REG PINA
01158 #define PINA7_REG PINA
01159
01160
01161 #define TXB81_REG UCSR1B
01162 #define RXB81_REG UCSR1B
01163 #define UCSZ12_REG UCSR1B
01164 #define TXEN1_REG UCSR1B
01165 #define RXEN1_REG UCSR1B
01166 #define UDRIE1_REG UCSR1B
01167 #define TXCIE1_REG UCSR1B
01168 #define RXCIE1_REG UCSR1B
01169
01170
01171 #define UCPOL1_REG UCSR1C
01172 #define UCSZ10_REG UCSR1C
01173 #define UCSZ11_REG UCSR1C
01174 #define USBS1_REG UCSR1C
01175 #define UPM10_REG UCSR1C
01176 #define UPM11_REG UCSR1C
01177 #define UMSEL10_REG UCSR1C
01178 #define UMSEL11_REG UCSR1C
01179
01180
01181 #define MPCM1_REG UCSR1A
01182 #define U2X1_REG UCSR1A
01183 #define UPE1_REG UCSR1A
01184 #define DOR1_REG UCSR1A
01185 #define FE1_REG UCSR1A
01186 #define UDRE1_REG UCSR1A
01187 #define TXC1_REG UCSR1A
01188 #define RXC1_REG UCSR1A
01189
01190
01191 #define DDB0_REG DDRB
01192 #define DDB1_REG DDRB
01193 #define DDB2_REG DDRB
01194 #define DDB3_REG DDRB
01195 #define DDB4_REG DDRB
01196 #define DDB5_REG DDRB
01197 #define DDB6_REG DDRB
01198 #define DDB7_REG DDRB
01199
01200
01201 #define EIND0_REG EIND
01202
01203
01204 #define TWD0_REG TWDR
01205 #define TWD1_REG TWDR
01206 #define TWD2_REG TWDR
01207 #define TWD3_REG TWDR
01208 #define TWD4_REG TWDR
01209 #define TWD5_REG TWDR
01210 #define TWD6_REG TWDR
01211 #define TWD7_REG TWDR
01212
01213
01214 #define WGM50_REG TCCR5A
01215 #define WGM51_REG TCCR5A
01216 #define COM5C0_REG TCCR5A
01217 #define COM5C1_REG TCCR5A
01218 #define COM5B0_REG TCCR5A
01219 #define COM5B1_REG TCCR5A
01220 #define COM5A0_REG TCCR5A
01221 #define COM5A1_REG TCCR5A
01222
01223
01224 #define TWAM0_REG TWAMR
01225 #define TWAM1_REG TWAMR
01226 #define TWAM2_REG TWAMR
01227 #define TWAM3_REG TWAMR
01228 #define TWAM4_REG TWAMR
01229 #define TWAM5_REG TWAMR
01230 #define TWAM6_REG TWAMR
01231
01232
01233 #define FOC5C_REG TCCR5C
01234 #define FOC5B_REG TCCR5C
01235 #define FOC5A_REG TCCR5C
01236
01237
01238 #define CS50_REG TCCR5B
01239 #define CS51_REG TCCR5B
01240 #define CS52_REG TCCR5B
01241 #define WGM52_REG TCCR5B
01242 #define WGM53_REG TCCR5B
01243 #define ICES5_REG TCCR5B
01244 #define ICNC5_REG TCCR5B
01245
01246
01247 #define ADPS0_REG ADCSRA
01248 #define ADPS1_REG ADCSRA
01249 #define ADPS2_REG ADCSRA
01250 #define ADIE_REG ADCSRA
01251 #define ADIF_REG ADCSRA
01252 #define ADATE_REG ADCSRA
01253 #define ADSC_REG ADCSRA
01254 #define ADEN_REG ADCSRA
01255
01256
01257 #define ACME_REG ADCSRB
01258 #define ADTS0_REG ADCSRB
01259 #define ADTS1_REG ADCSRB
01260 #define ADTS2_REG ADCSRB
01261 #define MUX5_REG ADCSRB
01262
01263
01264 #define OCR5AL0_REG OCR5AL
01265 #define OCR5AL1_REG OCR5AL
01266 #define OCR5AL2_REG OCR5AL
01267 #define OCR5AL3_REG OCR5AL
01268 #define OCR5AL4_REG OCR5AL
01269 #define OCR5AL5_REG OCR5AL
01270 #define OCR5AL6_REG OCR5AL
01271 #define OCR5AL7_REG OCR5AL
01272
01273
01274 #define WGM10_REG TCCR1A
01275 #define WGM11_REG TCCR1A
01276 #define COM1C0_REG TCCR1A
01277 #define COM1C1_REG TCCR1A
01278 #define COM1B0_REG TCCR1A
01279 #define COM1B1_REG TCCR1A
01280 #define COM1A0_REG TCCR1A
01281 #define COM1A1_REG TCCR1A
01282
01283
01284 #define OCR4CH0_REG OCR4CH
01285 #define OCR4CH1_REG OCR4CH
01286 #define OCR4CH2_REG OCR4CH
01287 #define OCR4CH3_REG OCR4CH
01288 #define OCR4CH4_REG OCR4CH
01289 #define OCR4CH5_REG OCR4CH
01290 #define OCR4CH6_REG OCR4CH
01291 #define OCR4CH7_REG OCR4CH
01292
01293
01294 #define OCR5AH0_REG OCR5AH
01295 #define OCR5AH1_REG OCR5AH
01296 #define OCR5AH2_REG OCR5AH
01297 #define OCR5AH3_REG OCR5AH
01298 #define OCR5AH4_REG OCR5AH
01299 #define OCR5AH5_REG OCR5AH
01300 #define OCR5AH6_REG OCR5AH
01301 #define OCR5AH7_REG OCR5AH
01302
01303
01304 #define OCR4CL0_REG OCR4CL
01305 #define OCR4CL1_REG OCR4CL
01306 #define OCR4CL2_REG OCR4CL
01307 #define OCR4CL3_REG OCR4CL
01308 #define OCR4CL4_REG OCR4CL
01309 #define OCR4CL5_REG OCR4CL
01310 #define OCR4CL6_REG OCR4CL
01311 #define OCR4CL7_REG OCR4CL
01312
01313
01314 #define MPCM0_REG UCSR0A
01315 #define U2X0_REG UCSR0A
01316 #define UPE0_REG UCSR0A
01317 #define DOR0_REG UCSR0A
01318 #define FE0_REG UCSR0A
01319 #define UDRE0_REG UCSR0A
01320 #define TXC0_REG UCSR0A
01321 #define RXC0_REG UCSR0A
01322
01323
01324 #define FOC1C_REG TCCR1C
01325 #define FOC1B_REG TCCR1C
01326 #define FOC1A_REG TCCR1C
01327
01328
01329 #define ICR3H0_REG ICR3H
01330 #define ICR3H1_REG ICR3H
01331 #define ICR3H2_REG ICR3H
01332 #define ICR3H3_REG ICR3H
01333 #define ICR3H4_REG ICR3H
01334 #define ICR3H5_REG ICR3H
01335 #define ICR3H6_REG ICR3H
01336 #define ICR3H7_REG ICR3H
01337
01338
01339 #define DDE0_REG DDRE
01340 #define DDE1_REG DDRE
01341 #define DDE2_REG DDRE
01342 #define DDE3_REG DDRE
01343 #define DDE4_REG DDRE
01344 #define DDE5_REG DDRE
01345 #define DDE6_REG DDRE
01346 #define DDE7_REG DDRE
01347
01348
01349 #define PORTD0_REG PORTD
01350 #define PORTD1_REG PORTD
01351 #define PORTD2_REG PORTD
01352 #define PORTD3_REG PORTD
01353 #define PORTD4_REG PORTD
01354 #define PORTD5_REG PORTD
01355 #define PORTD6_REG PORTD
01356 #define PORTD7_REG PORTD
01357
01358
01359 #define ICR3L0_REG ICR3L
01360 #define ICR3L1_REG ICR3L
01361 #define ICR3L2_REG ICR3L
01362 #define ICR3L3_REG ICR3L
01363 #define ICR3L4_REG ICR3L
01364 #define ICR3L5_REG ICR3L
01365 #define ICR3L6_REG ICR3L
01366 #define ICR3L7_REG ICR3L
01367
01368
01369 #define PORTE0_REG PORTE
01370 #define PORTE1_REG PORTE
01371 #define PORTE2_REG PORTE
01372 #define PORTE3_REG PORTE
01373 #define PORTE4_REG PORTE
01374 #define PORTE5_REG PORTE
01375 #define PORTE6_REG PORTE
01376 #define PORTE7_REG PORTE
01377
01378
01379 #define SPMEN_REG SPMCSR
01380 #define PGERS_REG SPMCSR
01381 #define PGWRT_REG SPMCSR
01382 #define BLBSET_REG SPMCSR
01383 #define RWWSRE_REG SPMCSR
01384 #define SIGRD_REG SPMCSR
01385 #define RWWSB_REG SPMCSR
01386 #define SPMIE_REG SPMCSR
01387
01388
01389 #define PORTB0_REG PORTB
01390 #define PORTB1_REG PORTB
01391 #define PORTB2_REG PORTB
01392 #define PORTB3_REG PORTB
01393 #define PORTB4_REG PORTB
01394 #define PORTB5_REG PORTB
01395 #define PORTB6_REG PORTB
01396 #define PORTB7_REG PORTB
01397
01398
01399 #define ADCL0_REG ADCL
01400 #define ADCL1_REG ADCL
01401 #define ADCL2_REG ADCL
01402 #define ADCL3_REG ADCL
01403 #define ADCL4_REG ADCL
01404 #define ADCL5_REG ADCL
01405 #define ADCL6_REG ADCL
01406 #define ADCL7_REG ADCL
01407
01408
01409 #define ADCH0_REG ADCH
01410 #define ADCH1_REG ADCH
01411 #define ADCH2_REG ADCH
01412 #define ADCH3_REG ADCH
01413 #define ADCH4_REG ADCH
01414 #define ADCH5_REG ADCH
01415 #define ADCH6_REG ADCH
01416 #define ADCH7_REG ADCH
01417
01418
01419 #define OCR5BH0_REG OCR5BH
01420 #define OCR5BH1_REG OCR5BH
01421 #define OCR5BH2_REG OCR5BH
01422 #define OCR5BH3_REG OCR5BH
01423 #define OCR5BH4_REG OCR5BH
01424 #define OCR5BH5_REG OCR5BH
01425 #define OCR5BH6_REG OCR5BH
01426 #define OCR5BH7_REG OCR5BH
01427
01428
01429 #define OCR3BL0_REG OCR3BL
01430 #define OCR3BL1_REG OCR3BL
01431 #define OCR3BL2_REG OCR3BL
01432 #define OCR3BL3_REG OCR3BL
01433 #define OCR3BL4_REG OCR3BL
01434 #define OCR3BL5_REG OCR3BL
01435 #define OCR3BL6_REG OCR3BL
01436 #define OCR3BL7_REG OCR3BL
01437
01438
01439 #define OCR5BL0_REG OCR5BL
01440 #define OCR5BL1_REG OCR5BL
01441 #define OCR5BL2_REG OCR5BL
01442 #define OCR5BL3_REG OCR5BL
01443 #define OCR5BL4_REG OCR5BL
01444 #define OCR5BL5_REG OCR5BL
01445 #define OCR5BL6_REG OCR5BL
01446 #define OCR5BL7_REG OCR5BL
01447
01448
01449 #define OCR3BH0_REG OCR3BH
01450 #define OCR3BH1_REG OCR3BH
01451 #define OCR3BH2_REG OCR3BH
01452 #define OCR3BH3_REG OCR3BH
01453 #define OCR3BH4_REG OCR3BH
01454 #define OCR3BH5_REG OCR3BH
01455 #define OCR3BH6_REG OCR3BH
01456 #define OCR3BH7_REG OCR3BH
01457
01458
01459 #define TOIE2_REG TIMSK2
01460 #define OCIE2A_REG TIMSK2
01461 #define OCIE2B_REG TIMSK2
01462
01463
01464 #define TOIE3_REG TIMSK3
01465 #define OCIE3A_REG TIMSK3
01466 #define OCIE3B_REG TIMSK3
01467 #define OCIE3C_REG TIMSK3
01468 #define ICIE3_REG TIMSK3
01469
01470
01471 #define TOIE0_REG TIMSK0
01472 #define OCIE0A_REG TIMSK0
01473 #define OCIE0B_REG TIMSK0
01474
01475
01476 #define TOIE1_REG TIMSK1
01477 #define OCIE1A_REG TIMSK1
01478 #define OCIE1B_REG TIMSK1
01479 #define OCIE1C_REG TIMSK1
01480 #define ICIE1_REG TIMSK1
01481
01482
01483 #define TOIE4_REG TIMSK4
01484 #define OCIE4A_REG TIMSK4
01485 #define OCIE4B_REG TIMSK4
01486 #define OCIE4C_REG TIMSK4
01487 #define ICIE4_REG TIMSK4
01488
01489
01490 #define TOIE5_REG TIMSK5
01491 #define OCIE5A_REG TIMSK5
01492 #define OCIE5B_REG TIMSK5
01493 #define OCIE5C_REG TIMSK5
01494 #define ICIE5_REG TIMSK5
01495
01496
01497 #define CS40_REG TCCR4B
01498 #define CS41_REG TCCR4B
01499 #define CS42_REG TCCR4B
01500 #define WGM42_REG TCCR4B
01501 #define WGM43_REG TCCR4B
01502 #define ICES4_REG TCCR4B
01503 #define ICNC4_REG TCCR4B
01504
01505
01506 #define FOC4C_REG TCCR4C
01507 #define FOC4B_REG TCCR4C
01508 #define FOC4A_REG TCCR4C
01509
01510
01511 #define WGM40_REG TCCR4A
01512 #define WGM41_REG TCCR4A
01513 #define COM4C0_REG TCCR4A
01514 #define COM4C1_REG TCCR4A
01515 #define COM4B0_REG TCCR4A
01516 #define COM4B1_REG TCCR4A
01517 #define COM4A0_REG TCCR4A
01518 #define COM4A1_REG TCCR4A
01519
01520
01521 #define PCINT0_REG PCMSK0
01522 #define PCINT1_REG PCMSK0
01523 #define PCINT2_REG PCMSK0
01524 #define PCINT3_REG PCMSK0
01525 #define PCINT4_REG PCMSK0
01526 #define PCINT5_REG PCMSK0
01527 #define PCINT6_REG PCMSK0
01528 #define PCINT7_REG PCMSK0
01529
01530
01531 #define XMM0_REG XMCRB
01532 #define XMM1_REG XMCRB
01533 #define XMM2_REG XMCRB
01534 #define XMBK_REG XMCRB
01535
01536
01537 #define SRW00_REG XMCRA
01538 #define SRW01_REG XMCRA
01539 #define SRW10_REG XMCRA
01540 #define SRW11_REG XMCRA
01541 #define SRL0_REG XMCRA
01542 #define SRL1_REG XMCRA
01543 #define SRL2_REG XMCRA
01544 #define SRE_REG XMCRA
01545
01546
01547 #define OCR4BL0_REG OCR4BL
01548 #define OCR4BL1_REG OCR4BL
01549 #define OCR4BL2_REG OCR4BL
01550 #define OCR4BL3_REG OCR4BL
01551 #define OCR4BL4_REG OCR4BL
01552 #define OCR4BL5_REG OCR4BL
01553 #define OCR4BL6_REG OCR4BL
01554 #define OCR4BL7_REG OCR4BL
01555
01556
01557 #define PINB0_REG PINB
01558 #define PINB1_REG PINB
01559 #define PINB2_REG PINB
01560 #define PINB3_REG PINB
01561 #define PINB4_REG PINB
01562 #define PINB5_REG PINB
01563 #define PINB6_REG PINB
01564 #define PINB7_REG PINB
01565
01566
01567 #define INTF0_REG EIFR
01568 #define INTF1_REG EIFR
01569 #define INTF2_REG EIFR
01570 #define INTF3_REG EIFR
01571 #define INTF4_REG EIFR
01572 #define INTF5_REG EIFR
01573 #define INTF6_REG EIFR
01574 #define INTF7_REG EIFR
01575
01576
01577 #define OCR4BH0_REG OCR4BH
01578 #define OCR4BH1_REG OCR4BH
01579 #define OCR4BH2_REG OCR4BH
01580 #define OCR4BH3_REG OCR4BH
01581 #define OCR4BH4_REG OCR4BH
01582 #define OCR4BH5_REG OCR4BH
01583 #define OCR4BH6_REG OCR4BH
01584 #define OCR4BH7_REG OCR4BH
01585
01586
01587 #define PINF0_REG PINF
01588 #define PINF1_REG PINF
01589 #define PINF2_REG PINF
01590 #define PINF3_REG PINF
01591 #define PINF4_REG PINF
01592 #define PINF5_REG PINF
01593 #define PINF6_REG PINF
01594 #define PINF7_REG PINF
01595
01596
01597 #define PINE0_REG PINE
01598 #define PINE1_REG PINE
01599 #define PINE2_REG PINE
01600 #define PINE3_REG PINE
01601 #define PINE4_REG PINE
01602 #define PINE5_REG PINE
01603 #define PINE6_REG PINE
01604 #define PINE7_REG PINE
01605
01606
01607 #define PIND0_REG PIND
01608 #define PIND1_REG PIND
01609 #define PIND2_REG PIND
01610 #define PIND3_REG PIND
01611 #define PIND4_REG PIND
01612 #define PIND5_REG PIND
01613 #define PIND6_REG PIND
01614 #define PIND7_REG PIND
01615
01616
01617 #define OCR1AH0_REG OCR1AH
01618 #define OCR1AH1_REG OCR1AH
01619 #define OCR1AH2_REG OCR1AH
01620 #define OCR1AH3_REG OCR1AH
01621 #define OCR1AH4_REG OCR1AH
01622 #define OCR1AH5_REG OCR1AH
01623 #define OCR1AH6_REG OCR1AH
01624 #define OCR1AH7_REG OCR1AH
01625
01626
01627 #define PRADC_REG PRR0
01628 #define PRUSART0_REG PRR0
01629 #define PRSPI_REG PRR0
01630 #define PRTIM1_REG PRR0
01631 #define PRTIM0_REG PRR0
01632 #define PRTIM2_REG PRR0
01633 #define PRTWI_REG PRR0
01634
01635
01636 #define OCR1AL0_REG OCR1AL
01637 #define OCR1AL1_REG OCR1AL
01638 #define OCR1AL2_REG OCR1AL
01639 #define OCR1AL3_REG OCR1AL
01640 #define OCR1AL4_REG OCR1AL
01641 #define OCR1AL5_REG OCR1AL
01642 #define OCR1AL6_REG OCR1AL
01643 #define OCR1AL7_REG OCR1AL
01644
01645
01646 #define TOV0_REG TIFR0
01647 #define OCF0A_REG TIFR0
01648 #define OCF0B_REG TIFR0
01649
01650
01651 #define PRUSART1_REG PRR1
01652 #define PRUSART2_REG PRR1
01653 #define PRUSART3_REG PRR1
01654 #define PRTIM3_REG PRR1
01655 #define PRTIM4_REG PRR1
01656 #define PRTIM5_REG PRR1
01657
01658
01659 #define AD0_PORT PORTA
01660 #define AD0_BIT 0
01661
01662 #define AD1_PORT PORTA
01663 #define AD1_BIT 1
01664
01665 #define AD2_PORT PORTA
01666 #define AD2_BIT 2
01667
01668 #define AD3_PORT PORTA
01669 #define AD3_BIT 3
01670
01671 #define AD4_PORT PORTA
01672 #define AD4_BIT 4
01673
01674 #define AD5_PORT PORTA
01675 #define AD5_BIT 5
01676
01677 #define AD6_PORT PORTA
01678 #define AD6_BIT 6
01679
01680 #define AD7_PORT PORTA
01681 #define AD7_BIT 7
01682
01683 #define SS_PORT PORTB
01684 #define SS_BIT 0
01685 #define PCINT0_PORT PORTB
01686 #define PCINT0_BIT 0
01687
01688 #define SCK_PORT PORTB
01689 #define SCK_BIT 1
01690 #define PCINT1_PORT PORTB
01691 #define PCINT1_BIT 1
01692
01693 #define MOSI_PORT PORTB
01694 #define MOSI_BIT 2
01695 #define PCINT2_PORT PORTB
01696 #define PCINT2_BIT 2
01697
01698 #define MISO_PORT PORTB
01699 #define MISO_BIT 3
01700 #define PCINT3_PORT PORTB
01701 #define PCINT3_BIT 3
01702
01703 #define OC2_PORT PORTB
01704 #define OC2_BIT 4
01705 #define PCINT4_PORT PORTB
01706 #define PCINT4_BIT 4
01707
01708 #define OC1A_PORT PORTB
01709 #define OC1A_BIT 5
01710 #define PCINT5_PORT PORTB
01711 #define PCINT5_BIT 5
01712
01713 #define OC1B_PORT PORTB
01714 #define OC1B_BIT 6
01715 #define PCINT6_PORT PORTB
01716 #define PCINT6_BIT 6
01717
01718 #define OC0A_PORT PORTB
01719 #define OC0A_BIT 7
01720 #define OC1C_PORT PORTB
01721 #define OC1C_BIT 7
01722 #define PCINT7_PORT PORTB
01723 #define PCINT7_BIT 7
01724
01725 #define A8_PORT PORTC
01726 #define A8_BIT 0
01727
01728 #define A9_PORT PORTC
01729 #define A9_BIT 1
01730
01731 #define A10_PORT PORTC
01732 #define A10_BIT 2
01733
01734 #define A11_PORT PORTC
01735 #define A11_BIT 3
01736
01737 #define A12_PORT PORTC
01738 #define A12_BIT 4
01739
01740 #define A13_PORT PORTC
01741 #define A13_BIT 5
01742
01743 #define A14_PORT PORTC
01744 #define A14_BIT 6
01745
01746 #define A15_PORT PORTC
01747 #define A15_BIT 7
01748
01749 #define SCL_PORT PORTD
01750 #define SCL_BIT 0
01751 #define INT0_PORT PORTD
01752 #define INT0_BIT 0
01753
01754 #define SDA_PORT PORTD
01755 #define SDA_BIT 1
01756 #define INT1_PORT PORTD
01757 #define INT1_BIT 1
01758
01759 #define RXD1_PORT PORTD
01760 #define RXD1_BIT 2
01761 #define INT2_PORT PORTD
01762 #define INT2_BIT 2
01763
01764 #define TXD1_PORT PORTD
01765 #define TXD1_BIT 3
01766 #define INT3_PORT PORTD
01767 #define INT3_BIT 3
01768
01769 #define ICP1_PORT PORTD
01770 #define ICP1_BIT 4
01771
01772 #define XCK1_PORT PORTD
01773 #define XCK1_BIT 5
01774
01775 #define T1_PORT PORTD
01776 #define T1_BIT 6
01777
01778 #define T0_PORT PORTD
01779 #define T0_BIT 7
01780
01781 #define RXD0_PORT PORTE
01782 #define RXD0_BIT 0
01783 #define PDI_PORT PORTE
01784 #define PDI_BIT 0
01785 #define PCINT8_PORT PORTE
01786 #define PCINT8_BIT 0
01787
01788 #define TXD0_PORT PORTE
01789 #define TXD0_BIT 1
01790 #define PDO_PORT PORTE
01791 #define PDO_BIT 1
01792
01793 #define XCK0_PORT PORTE
01794 #define XCK0_BIT 2
01795 #define AIN0_PORT PORTE
01796 #define AIN0_BIT 2
01797
01798 #define OC3A_PORT PORTE
01799 #define OC3A_BIT 3
01800 #define AIN1_PORT PORTE
01801 #define AIN1_BIT 3
01802
01803 #define OC3B_PORT PORTE
01804 #define OC3B_BIT 4
01805 #define INT4_PORT PORTE
01806 #define INT4_BIT 4
01807
01808 #define OC3C_PORT PORTE
01809 #define OC3C_BIT 5
01810 #define INT5_PORT PORTE
01811 #define INT5_BIT 5
01812
01813 #define T3_PORT PORTE
01814 #define T3_BIT 6
01815 #define INT6_PORT PORTE
01816 #define INT6_BIT 6
01817
01818 #define ICP3_PORT PORTE
01819 #define ICP3_BIT 7
01820 #define INT7_PORT PORTE
01821 #define INT7_BIT 7
01822 #define CLKO_PORT PORTE
01823 #define CLKO_BIT 7
01824
01825 #define ADC0_PORT PORTF
01826 #define ADC0_BIT 0
01827
01828 #define ADC1_PORT PORTF
01829 #define ADC1_BIT 1
01830
01831 #define ADC2_PORT PORTF
01832 #define ADC2_BIT 2
01833
01834 #define ADC3_PORT PORTF
01835 #define ADC3_BIT 3
01836
01837 #define ADC4_PORT PORTF
01838 #define ADC4_BIT 4
01839 #define TCK_PORT PORTF
01840 #define TCK_BIT 4
01841
01842 #define ADC5_PORT PORTF
01843 #define ADC5_BIT 5
01844 #define TMS_PORT PORTF
01845 #define TMS_BIT 5
01846
01847 #define ADC6_PORT PORTF
01848 #define ADC6_BIT 6
01849 #define TD0_PORT PORTF
01850 #define TD0_BIT 6
01851
01852 #define ADC7_PORT PORTF
01853 #define ADC7_BIT 7
01854 #define TDI_PORT PORTF
01855 #define TDI_BIT 7
01856
01857 #define WR_PORT PORTG
01858 #define WR_BIT 0
01859
01860 #define RD_PORT PORTG
01861 #define RD_BIT 1
01862
01863 #define ALE_PORT PORTG
01864 #define ALE_BIT 2
01865
01866 #define TOSC2_PORT PORTG
01867 #define TOSC2_BIT 3
01868
01869 #define TOSC1_PORT PORTG
01870 #define TOSC1_BIT 4
01871
01872 #define OC0B_PORT PORTG
01873 #define OC0B_BIT 5
01874
01875