00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define WDP0_REG WDTCR
00119 #define WDP1_REG WDTCR
00120 #define WDP2_REG WDTCR
00121 #define WDE_REG WDTCR
00122 #define WDCE_REG WDTCR
00123
00124
00125 #define MUX0_REG ADMUX
00126 #define MUX1_REG ADMUX
00127 #define MUX2_REG ADMUX
00128 #define MUX3_REG ADMUX
00129 #define MUX4_REG ADMUX
00130 #define ADLAR_REG ADMUX
00131 #define REFS0_REG ADMUX
00132 #define REFS1_REG ADMUX
00133
00134
00135 #define EEDR0_REG EEDR
00136 #define EEDR1_REG EEDR
00137 #define EEDR2_REG EEDR
00138 #define EEDR3_REG EEDR
00139 #define EEDR4_REG EEDR
00140 #define EEDR5_REG EEDR
00141 #define EEDR6_REG EEDR
00142 #define EEDR7_REG EEDR
00143
00144
00145 #define OCR2A0_REG OCR2A
00146 #define OCR2A1_REG OCR2A
00147 #define OCR2A2_REG OCR2A
00148 #define OCR2A3_REG OCR2A
00149 #define OCR2A4_REG OCR2A
00150 #define OCR2A5_REG OCR2A
00151 #define OCR2A6_REG OCR2A
00152 #define OCR2A7_REG OCR2A
00153
00154
00155 #define SPDR0_REG SPDR
00156 #define SPDR1_REG SPDR
00157 #define SPDR2_REG SPDR
00158 #define SPDR3_REG SPDR
00159 #define SPDR4_REG SPDR
00160 #define SPDR5_REG SPDR
00161 #define SPDR6_REG SPDR
00162 #define SPDR7_REG SPDR
00163
00164
00165 #define SPI2X_REG SPSR
00166 #define WCOL_REG SPSR
00167 #define SPIF_REG SPSR
00168
00169
00170 #define SP8_REG SPH
00171 #define SP9_REG SPH
00172 #define SP10_REG SPH
00173
00174
00175 #define ICR1L0_REG ICR1L
00176 #define ICR1L1_REG ICR1L
00177 #define ICR1L2_REG ICR1L
00178 #define ICR1L3_REG ICR1L
00179 #define ICR1L4_REG ICR1L
00180 #define ICR1L5_REG ICR1L
00181 #define ICR1L6_REG ICR1L
00182 #define ICR1L7_REG ICR1L
00183
00184
00185 #define PRADC_REG PRR
00186 #define PRUSART0_REG PRR
00187 #define PRSPI_REG PRR
00188 #define PRTIM1_REG PRR
00189 #define PRLCD_REG PRR
00190
00191
00192 #define MPCM0_REG UCSR0A
00193 #define U2X0_REG UCSR0A
00194 #define UPE0_REG UCSR0A
00195 #define DOR0_REG UCSR0A
00196 #define FE0_REG UCSR0A
00197 #define UDRE0_REG UCSR0A
00198 #define TXC0_REG UCSR0A
00199 #define RXC0_REG UCSR0A
00200
00201
00202 #define PORTG0_REG PORTG
00203 #define PORTG1_REG PORTG
00204 #define PORTG2_REG PORTG
00205 #define PORTG3_REG PORTG
00206 #define PORTG4_REG PORTG
00207 #define PORTG5_REG PORTG
00208
00209
00210 #define UCPOL0_REG UCSR0C
00211 #define UCSZ00_REG UCSR0C
00212 #define UCSZ01_REG UCSR0C
00213 #define USBS0_REG UCSR0C
00214 #define UPM00_REG UCSR0C
00215 #define UPM01_REG UCSR0C
00216 #define UMSEL0_REG UCSR0C
00217
00218
00219 #define USICNT0_REG USISR
00220 #define USICNT1_REG USISR
00221 #define USICNT2_REG USISR
00222 #define USICNT3_REG USISR
00223 #define USIDC_REG USISR
00224 #define USIPF_REG USISR
00225 #define USIOIF_REG USISR
00226 #define USISIF_REG USISR
00227
00228
00229 #define TCNT1H0_REG TCNT1H
00230 #define TCNT1H1_REG TCNT1H
00231 #define TCNT1H2_REG TCNT1H
00232 #define TCNT1H3_REG TCNT1H
00233 #define TCNT1H4_REG TCNT1H
00234 #define TCNT1H5_REG TCNT1H
00235 #define TCNT1H6_REG TCNT1H
00236 #define TCNT1H7_REG TCNT1H
00237
00238
00239 #define PORTC0_REG PORTC
00240 #define PORTC1_REG PORTC
00241 #define PORTC2_REG PORTC
00242 #define PORTC3_REG PORTC
00243 #define PORTC4_REG PORTC
00244 #define PORTC5_REG PORTC
00245 #define PORTC6_REG PORTC
00246 #define PORTC7_REG PORTC
00247
00248
00249 #define PORTA0_REG PORTA
00250 #define PORTA1_REG PORTA
00251 #define PORTA2_REG PORTA
00252 #define PORTA3_REG PORTA
00253 #define PORTA4_REG PORTA
00254 #define PORTA5_REG PORTA
00255 #define PORTA6_REG PORTA
00256 #define PORTA7_REG PORTA
00257
00258
00259 #define UDR00_REG UDR0
00260 #define UDR01_REG UDR0
00261 #define UDR02_REG UDR0
00262 #define UDR03_REG UDR0
00263 #define UDR04_REG UDR0
00264 #define UDR05_REG UDR0
00265 #define UDR06_REG UDR0
00266 #define UDR07_REG UDR0
00267
00268
00269 #define GPIOR20_REG GPIOR2
00270 #define GPIOR21_REG GPIOR2
00271 #define GPIOR22_REG GPIOR2
00272 #define GPIOR23_REG GPIOR2
00273 #define GPIOR24_REG GPIOR2
00274 #define GPIOR25_REG GPIOR2
00275 #define GPIOR26_REG GPIOR2
00276 #define GPIOR27_REG GPIOR2
00277
00278
00279 #define ISC00_REG EICRA
00280 #define ISC01_REG EICRA
00281
00282
00283 #define ADC0D_REG DIDR0
00284 #define ADC1D_REG DIDR0
00285 #define ADC2D_REG DIDR0
00286 #define ADC3D_REG DIDR0
00287 #define ADC4D_REG DIDR0
00288 #define ADC5D_REG DIDR0
00289 #define ADC6D_REG DIDR0
00290 #define ADC7D_REG DIDR0
00291
00292
00293 #define AIN0D_REG DIDR1
00294 #define AIN1D_REG DIDR1
00295
00296
00297 #define TCR2UB_REG ASSR
00298 #define OCR2UB_REG ASSR
00299 #define TCN2UB_REG ASSR
00300 #define AS2_REG ASSR
00301 #define EXCLK_REG ASSR
00302
00303
00304 #define CLKPS0_REG CLKPR
00305 #define CLKPS1_REG CLKPR
00306 #define CLKPS2_REG CLKPR
00307 #define CLKPS3_REG CLKPR
00308 #define CLKPCE_REG CLKPR
00309
00310
00311 #define C_REG SREG
00312 #define Z_REG SREG
00313 #define N_REG SREG
00314 #define V_REG SREG
00315 #define S_REG SREG
00316 #define H_REG SREG
00317 #define T_REG SREG
00318 #define I_REG SREG
00319
00320
00321 #define DDB0_REG DDRB
00322 #define DDB1_REG DDRB
00323 #define DDB2_REG DDRB
00324 #define DDB3_REG DDRB
00325 #define DDB4_REG DDRB
00326 #define DDB5_REG DDRB
00327 #define DDB6_REG DDRB
00328 #define DDB7_REG DDRB
00329
00330
00331 #define DDC0_REG DDRC
00332 #define DDC1_REG DDRC
00333 #define DDC2_REG DDRC
00334 #define DDC3_REG DDRC
00335 #define DDC4_REG DDRC
00336 #define DDC5_REG DDRC
00337 #define DDC6_REG DDRC
00338 #define DDC7_REG DDRC
00339
00340
00341 #define DDA0_REG DDRA
00342 #define DDA1_REG DDRA
00343 #define DDA2_REG DDRA
00344 #define DDA3_REG DDRA
00345 #define DDA4_REG DDRA
00346 #define DDA5_REG DDRA
00347 #define DDA6_REG DDRA
00348 #define DDA7_REG DDRA
00349
00350
00351 #define WGM10_REG TCCR1A
00352 #define WGM11_REG TCCR1A
00353 #define COM1B0_REG TCCR1A
00354 #define COM1B1_REG TCCR1A
00355 #define COM1A0_REG TCCR1A
00356 #define COM1A1_REG TCCR1A
00357
00358
00359 #define DDG0_REG DDRG
00360 #define DDG1_REG DDRG
00361 #define DDG2_REG DDRG
00362 #define DDG3_REG DDRG
00363 #define DDG4_REG DDRG
00364 #define DDG5_REG DDRG
00365
00366
00367 #define FOC1B_REG TCCR1C
00368 #define FOC1A_REG TCCR1C
00369
00370
00371 #define CS10_REG TCCR1B
00372 #define CS11_REG TCCR1B
00373 #define CS12_REG TCCR1B
00374 #define WGM12_REG TCCR1B
00375 #define WGM13_REG TCCR1B
00376 #define ICES1_REG TCCR1B
00377 #define ICNC1_REG TCCR1B
00378
00379
00380 #define CAL0_REG OSCCAL
00381 #define CAL1_REG OSCCAL
00382 #define CAL2_REG OSCCAL
00383 #define CAL3_REG OSCCAL
00384 #define CAL4_REG OSCCAL
00385 #define CAL5_REG OSCCAL
00386 #define CAL6_REG OSCCAL
00387 #define CAL7_REG OSCCAL
00388
00389
00390 #define SEG024_REG LCDDR3
00391
00392
00393 #define SEG016_REG LCDDR2
00394 #define SEG017_REG LCDDR2
00395 #define SEG018_REG LCDDR2
00396 #define SEG019_REG LCDDR2
00397 #define SEG020_REG LCDDR2
00398 #define SEG021_REG LCDDR2
00399 #define SEG022_REG LCDDR2
00400 #define SEG023_REG LCDDR2
00401
00402
00403 #define SEG008_REG LCDDR1
00404 #define SEG009_REG LCDDR1
00405 #define SEG010_REG LCDDR1
00406 #define SEG011_REG LCDDR1
00407 #define SEG012_REG LCDDR1
00408 #define SEG013_REG LCDDR1
00409 #define SEG014_REG LCDDR1
00410 #define SEG015_REG LCDDR1
00411
00412
00413 #define SEG000_REG LCDDR0
00414 #define SEG001_REG LCDDR0
00415 #define SEG002_REG LCDDR0
00416 #define SEG003_REG LCDDR0
00417 #define SEG004_REG LCDDR0
00418 #define SEG005_REG LCDDR0
00419 #define SEG006_REG LCDDR0
00420 #define SEG007_REG LCDDR0
00421
00422
00423 #define SEG116_REG LCDDR7
00424 #define SEG117_REG LCDDR7
00425 #define SEG118_REG LCDDR7
00426 #define SEG119_REG LCDDR7
00427 #define SEG120_REG LCDDR7
00428 #define SEG121_REG LCDDR7
00429 #define SEG122_REG LCDDR7
00430 #define SEG123_REG LCDDR7
00431
00432
00433 #define SEG108_REG LCDDR6
00434 #define SEG109_REG LCDDR6
00435 #define SEG110_REG LCDDR6
00436 #define SEG111_REG LCDDR6
00437 #define SEG112_REG LCDDR6
00438 #define SEG113_REG LCDDR6
00439 #define SEG114_REG LCDDR6
00440 #define SEG115_REG LCDDR6
00441
00442
00443 #define SEG100_REG LCDDR5
00444 #define SEG101_REG LCDDR5
00445 #define SEG102_REG LCDDR5
00446 #define SEG103_REG LCDDR5
00447 #define SEG104_REG LCDDR5
00448 #define SEG105_REG LCDDR5
00449 #define SEG106_REG LCDDR5
00450 #define SEG107_REG LCDDR5
00451
00452
00453 #define GPIOR10_REG GPIOR1
00454 #define GPIOR11_REG GPIOR1
00455 #define GPIOR12_REG GPIOR1
00456 #define GPIOR13_REG GPIOR1
00457 #define GPIOR14_REG GPIOR1
00458 #define GPIOR15_REG GPIOR1
00459 #define GPIOR16_REG GPIOR1
00460 #define GPIOR17_REG GPIOR1
00461
00462
00463 #define GPIOR00_REG GPIOR0
00464 #define GPIOR01_REG GPIOR0
00465 #define GPIOR02_REG GPIOR0
00466 #define GPIOR03_REG GPIOR0
00467 #define GPIOR04_REG GPIOR0
00468 #define GPIOR05_REG GPIOR0
00469 #define GPIOR06_REG GPIOR0
00470 #define GPIOR07_REG GPIOR0
00471
00472
00473 #define SEG124_REG LCDDR8
00474
00475
00476 #define LCDBL_REG LCDCRA
00477 #define LCDCCD_REG LCDCRA
00478 #define LCDBD_REG LCDCRA
00479 #define LCDIE_REG LCDCRA
00480 #define LCDIF_REG LCDCRA
00481 #define LCDAB_REG LCDCRA
00482 #define LCDEN_REG LCDCRA
00483
00484
00485 #define DDE0_REG DDRE
00486 #define DDE1_REG DDRE
00487 #define DDE2_REG DDRE
00488 #define DDE3_REG DDRE
00489 #define DDE4_REG DDRE
00490 #define DDE5_REG DDRE
00491 #define DDE6_REG DDRE
00492 #define DDE7_REG DDRE
00493
00494
00495 #define TCNT2_0_REG TCNT2
00496 #define TCNT2_1_REG TCNT2
00497 #define TCNT2_2_REG TCNT2
00498 #define TCNT2_3_REG TCNT2
00499 #define TCNT2_4_REG TCNT2
00500 #define TCNT2_5_REG TCNT2
00501 #define TCNT2_6_REG TCNT2
00502 #define TCNT2_7_REG TCNT2
00503
00504
00505 #define TCNT0_0_REG TCNT0
00506 #define TCNT0_1_REG TCNT0
00507 #define TCNT0_2_REG TCNT0
00508 #define TCNT0_3_REG TCNT0
00509 #define TCNT0_4_REG TCNT0
00510 #define TCNT0_5_REG TCNT0
00511 #define TCNT0_6_REG TCNT0
00512 #define TCNT0_7_REG TCNT0
00513
00514
00515 #define CS00_REG TCCR0A
00516 #define CS01_REG TCCR0A
00517 #define CS02_REG TCCR0A
00518 #define WGM01_REG TCCR0A
00519 #define COM0A0_REG TCCR0A
00520 #define COM0A1_REG TCCR0A
00521 #define WGM00_REG TCCR0A
00522 #define FOC0A_REG TCCR0A
00523
00524
00525 #define TOV2_REG TIFR2
00526 #define OCF2A_REG TIFR2
00527
00528
00529 #define SPR0_REG SPCR
00530 #define SPR1_REG SPCR
00531 #define CPHA_REG SPCR
00532 #define CPOL_REG SPCR
00533 #define MSTR_REG SPCR
00534 #define DORD_REG SPCR
00535 #define SPE_REG SPCR
00536 #define SPIE_REG SPCR
00537
00538
00539 #define TOV1_REG TIFR1
00540 #define OCF1A_REG TIFR1
00541 #define OCF1B_REG TIFR1
00542 #define ICF1_REG TIFR1
00543
00544
00545 #define PSR310_REG GTCCR
00546 #define TSM_REG GTCCR
00547 #define PSR2_REG GTCCR
00548
00549
00550 #define ICR1H0_REG ICR1H
00551 #define ICR1H1_REG ICR1H
00552 #define ICR1H2_REG ICR1H
00553 #define ICR1H3_REG ICR1H
00554 #define ICR1H4_REG ICR1H
00555 #define ICR1H5_REG ICR1H
00556 #define ICR1H6_REG ICR1H
00557 #define ICR1H7_REG ICR1H
00558
00559
00560 #define LCDPM0_REG LCDCRB
00561 #define LCDPM1_REG LCDCRB
00562 #define LCDPM2_REG LCDCRB
00563 #define LCDMUX0_REG LCDCRB
00564 #define LCDMUX1_REG LCDCRB
00565 #define LCD2B_REG LCDCRB
00566 #define LCDCS_REG LCDCRB
00567
00568
00569 #define SEG324_REG LCDDR18
00570
00571
00572 #define SEG224_REG LCDDR13
00573
00574
00575 #define SEG216_REG LCDDR12
00576 #define SEG217_REG LCDDR12
00577 #define SEG218_REG LCDDR12
00578 #define SEG219_REG LCDDR12
00579 #define SEG220_REG LCDDR12
00580 #define SEG221_REG LCDDR12
00581 #define SEG222_REG LCDDR12
00582 #define SEG223_REG LCDDR12
00583
00584
00585 #define SEG208_REG LCDDR11
00586 #define SEG209_REG LCDDR11
00587 #define SEG210_REG LCDDR11
00588 #define SEG211_REG LCDDR11
00589 #define SEG212_REG LCDDR11
00590 #define SEG213_REG LCDDR11
00591 #define SEG214_REG LCDDR11
00592 #define SEG215_REG LCDDR11
00593
00594
00595 #define SEG200_REG LCDDR10
00596 #define SEG201_REG LCDDR10
00597 #define SEG202_REG LCDDR10
00598 #define SEG203_REG LCDDR10
00599 #define SEG204_REG LCDDR10
00600 #define SEG205_REG LCDDR10
00601 #define SEG206_REG LCDDR10
00602 #define SEG207_REG LCDDR10
00603
00604
00605 #define SEG316_REG LCDDR17
00606 #define SEG317_REG LCDDR17
00607 #define SEG318_REG LCDDR17
00608 #define SEG319_REG LCDDR17
00609 #define SEG320_REG LCDDR17
00610 #define SEG321_REG LCDDR17
00611 #define SEG322_REG LCDDR17
00612 #define SEG323_REG LCDDR17
00613
00614
00615 #define SEG308_REG LCDDR16
00616 #define SEG309_REG LCDDR16
00617 #define SEG310_REG LCDDR16
00618 #define SEG311_REG LCDDR16
00619 #define SEG312_REG LCDDR16
00620 #define SEG313_REG LCDDR16
00621 #define SEG314_REG LCDDR16
00622 #define SEG315_REG LCDDR16
00623
00624
00625 #define SEG300_REG LCDDR15
00626 #define SEG301_REG LCDDR15
00627 #define SEG302_REG LCDDR15
00628 #define SEG303_REG LCDDR15
00629 #define SEG304_REG LCDDR15
00630 #define SEG305_REG LCDDR15
00631 #define SEG306_REG LCDDR15
00632 #define SEG307_REG LCDDR15
00633
00634
00635 #define OCR1BL0_REG OCR1BL
00636 #define OCR1BL1_REG OCR1BL
00637 #define OCR1BL2_REG OCR1BL
00638 #define OCR1BL3_REG OCR1BL
00639 #define OCR1BL4_REG OCR1BL
00640 #define OCR1BL5_REG OCR1BL
00641 #define OCR1BL6_REG OCR1BL
00642 #define OCR1BL7_REG OCR1BL
00643
00644
00645 #define OCR1BH0_REG OCR1BH
00646 #define OCR1BH1_REG OCR1BH
00647 #define OCR1BH2_REG OCR1BH
00648 #define OCR1BH3_REG OCR1BH
00649 #define OCR1BH4_REG OCR1BH
00650 #define OCR1BH5_REG OCR1BH
00651 #define OCR1BH6_REG OCR1BH
00652 #define OCR1BH7_REG OCR1BH
00653
00654
00655 #define SP0_REG SPL
00656 #define SP1_REG SPL
00657 #define SP2_REG SPL
00658 #define SP3_REG SPL
00659 #define SP4_REG SPL
00660 #define SP5_REG SPL
00661 #define SP6_REG SPL
00662 #define SP7_REG SPL
00663
00664
00665 #define JTRF_REG MCUSR
00666 #define PORF_REG MCUSR
00667 #define EXTRF_REG MCUSR
00668 #define BORF_REG MCUSR
00669 #define WDRF_REG MCUSR
00670
00671
00672 #define EERE_REG EECR
00673 #define EEWE_REG EECR
00674 #define EEMWE_REG EECR
00675 #define EERIE_REG EECR
00676
00677
00678 #define SE_REG SMCR
00679 #define SM0_REG SMCR
00680 #define SM1_REG SMCR
00681 #define SM2_REG SMCR
00682
00683
00684 #define CS20_REG TCCR2A
00685 #define CS21_REG TCCR2A
00686 #define CS22_REG TCCR2A
00687 #define WGM21_REG TCCR2A
00688 #define COM2A0_REG TCCR2A
00689 #define COM2A1_REG TCCR2A
00690 #define WGM20_REG TCCR2A
00691 #define FOC2A_REG TCCR2A
00692
00693
00694 #define UBRR8_REG UBRR0H
00695 #define UBRR9_REG UBRR0H
00696 #define UBRR10_REG UBRR0H
00697 #define UBRR11_REG UBRR0H
00698
00699
00700 #define UBRR0_REG UBRR0L
00701 #define UBRR1_REG UBRR0L
00702 #define UBRR2_REG UBRR0L
00703 #define UBRR3_REG UBRR0L
00704 #define UBRR4_REG UBRR0L
00705 #define UBRR5_REG UBRR0L
00706 #define UBRR6_REG UBRR0L
00707 #define UBRR7_REG UBRR0L
00708
00709
00710 #define EEAR8_REG EEARH
00711
00712
00713 #define EEAR0_REG EEARL
00714 #define EEAR1_REG EEARL
00715 #define EEAR2_REG EEARL
00716 #define EEAR3_REG EEARL
00717 #define EEAR4_REG EEARL
00718 #define EEAR5_REG EEARL
00719 #define EEAR6_REG EEARL
00720 #define EEAR7_REG EEARL
00721
00722
00723 #define JTD_REG MCUCR
00724 #define IVCE_REG MCUCR
00725 #define IVSEL_REG MCUCR
00726 #define PUD_REG MCUCR
00727
00728
00729 #define OCDR0_REG OCDR
00730 #define OCDR1_REG OCDR
00731 #define OCDR2_REG OCDR
00732 #define OCDR3_REG OCDR
00733 #define OCDR4_REG OCDR
00734 #define OCDR5_REG OCDR
00735 #define OCDR6_REG OCDR
00736 #define OCDR7_REG OCDR
00737
00738
00739 #define PINA0_REG PINA
00740 #define PINA1_REG PINA
00741 #define PINA2_REG PINA
00742 #define PINA3_REG PINA
00743 #define PINA4_REG PINA
00744 #define PINA5_REG PINA
00745 #define PINA6_REG PINA
00746 #define PINA7_REG PINA
00747
00748
00749 #define PORTE0_REG PORTE
00750 #define PORTE1_REG PORTE
00751 #define PORTE2_REG PORTE
00752 #define PORTE3_REG PORTE
00753 #define PORTE4_REG PORTE
00754 #define PORTE5_REG PORTE
00755 #define PORTE6_REG PORTE
00756 #define PORTE7_REG PORTE
00757
00758
00759 #define LCDCC0_REG LCDCCR
00760 #define LCDCC1_REG LCDCCR
00761 #define LCDCC2_REG LCDCCR
00762 #define LCDCC3_REG LCDCCR
00763 #define LCDMDT_REG LCDCCR
00764 #define LCDDC0_REG LCDCCR
00765 #define LCDDC1_REG LCDCCR
00766 #define LCDDC2_REG LCDCCR
00767
00768
00769 #define PINE0_REG PINE
00770 #define PINE1_REG PINE
00771 #define PINE2_REG PINE
00772 #define PINE3_REG PINE
00773 #define PINE4_REG PINE
00774 #define PINE5_REG PINE
00775 #define PINE6_REG PINE
00776 #define PINE7_REG PINE
00777
00778
00779 #define ADPS0_REG ADCSRA
00780 #define ADPS1_REG ADCSRA
00781 #define ADPS2_REG ADCSRA
00782 #define ADIE_REG ADCSRA
00783 #define ADIF_REG ADCSRA
00784 #define ADATE_REG ADCSRA
00785 #define ADSC_REG ADCSRA
00786 #define ADEN_REG ADCSRA
00787
00788
00789 #define ACME_REG ADCSRB
00790 #define ADTS0_REG ADCSRB
00791 #define ADTS1_REG ADCSRB
00792 #define ADTS2_REG ADCSRB
00793
00794
00795 #define DDF0_REG DDRF
00796 #define DDF1_REG DDRF
00797 #define DDF2_REG DDRF
00798 #define DDF3_REG DDRF
00799 #define DDF4_REG DDRF
00800 #define DDF5_REG DDRF
00801 #define DDF6_REG DDRF
00802 #define DDF7_REG DDRF
00803
00804
00805 #define OCR0A0_REG OCR0A
00806 #define OCR0A1_REG OCR0A
00807 #define OCR0A2_REG OCR0A
00808 #define OCR0A3_REG OCR0A
00809 #define OCR0A4_REG OCR0A
00810 #define OCR0A5_REG OCR0A
00811 #define OCR0A6_REG OCR0A
00812 #define OCR0A7_REG OCR0A
00813
00814
00815 #define ACIS0_REG ACSR
00816 #define ACIS1_REG ACSR
00817 #define ACIC_REG ACSR
00818 #define ACIE_REG ACSR
00819 #define ACI_REG ACSR
00820 #define ACO_REG ACSR
00821 #define ACBG_REG ACSR
00822 #define ACD_REG ACSR
00823
00824
00825 #define TCNT1L0_REG TCNT1L
00826 #define TCNT1L1_REG TCNT1L
00827 #define TCNT1L2_REG TCNT1L
00828 #define TCNT1L3_REG TCNT1L
00829 #define TCNT1L4_REG TCNT1L
00830 #define TCNT1L5_REG TCNT1L
00831 #define TCNT1L6_REG TCNT1L
00832 #define TCNT1L7_REG TCNT1L
00833
00834
00835 #define DDD0_REG DDRD
00836 #define DDD1_REG DDRD
00837 #define DDD2_REG DDRD
00838 #define DDD3_REG DDRD
00839 #define DDD4_REG DDRD
00840 #define DDD5_REG DDRD
00841 #define DDD6_REG DDRD
00842 #define DDD7_REG DDRD
00843
00844
00845 #define USITC_REG USICR
00846 #define USICLK_REG USICR
00847 #define USICS0_REG USICR
00848 #define USICS1_REG USICR
00849 #define USIWM0_REG USICR
00850 #define USIWM1_REG USICR
00851 #define USIOIE_REG USICR
00852 #define USISIE_REG USICR
00853
00854
00855 #define PORTD0_REG PORTD
00856 #define PORTD1_REG PORTD
00857 #define PORTD2_REG PORTD
00858 #define PORTD3_REG PORTD
00859 #define PORTD4_REG PORTD
00860 #define PORTD5_REG PORTD
00861 #define PORTD6_REG PORTD
00862 #define PORTD7_REG PORTD
00863
00864
00865 #define TXB80_REG UCSR0B
00866 #define RXB80_REG UCSR0B
00867 #define UCSZ02_REG UCSR0B
00868 #define TXEN0_REG UCSR0B
00869 #define RXEN0_REG UCSR0B
00870 #define UDRIE0_REG UCSR0B
00871 #define TXCIE0_REG UCSR0B
00872 #define RXCIE0_REG UCSR0B
00873
00874
00875 #define SPMEN_REG SPMCSR
00876 #define PGERS_REG SPMCSR
00877 #define PGWRT_REG SPMCSR
00878 #define BLBSET_REG SPMCSR
00879 #define RWWSRE_REG SPMCSR
00880 #define RWWSB_REG SPMCSR
00881 #define SPMIE_REG SPMCSR
00882
00883
00884 #define PORTB0_REG PORTB
00885 #define PORTB1_REG PORTB
00886 #define PORTB2_REG PORTB
00887 #define PORTB3_REG PORTB
00888 #define PORTB4_REG PORTB
00889 #define PORTB5_REG PORTB
00890 #define PORTB6_REG PORTB
00891 #define PORTB7_REG PORTB
00892
00893
00894 #define ADCL0_REG ADCL
00895 #define ADCL1_REG ADCL
00896 #define ADCL2_REG ADCL
00897 #define ADCL3_REG ADCL
00898 #define ADCL4_REG ADCL
00899 #define ADCL5_REG ADCL
00900 #define ADCL6_REG ADCL
00901 #define ADCL7_REG ADCL
00902
00903
00904 #define ADCH0_REG ADCH
00905 #define ADCH1_REG ADCH
00906 #define ADCH2_REG ADCH
00907 #define ADCH3_REG ADCH
00908 #define ADCH4_REG ADCH
00909 #define ADCH5_REG ADCH
00910 #define ADCH6_REG ADCH
00911 #define ADCH7_REG ADCH
00912
00913
00914 #define LCDCD0_REG LCDFRR
00915 #define LCDCD1_REG LCDFRR
00916 #define LCDCD2_REG LCDFRR
00917 #define LCDPS0_REG LCDFRR
00918 #define LCDPS1_REG LCDFRR
00919 #define LCDPS2_REG LCDFRR
00920
00921
00922 #define TOIE2_REG TIMSK2
00923 #define OCIE2A_REG TIMSK2
00924
00925
00926 #define INT0_REG EIMSK
00927 #define PCIE0_REG EIMSK
00928 #define PCIE1_REG EIMSK
00929
00930
00931 #define TOIE0_REG TIMSK0
00932 #define OCIE0A_REG TIMSK0
00933
00934
00935 #define TOIE1_REG TIMSK1
00936 #define OCIE1A_REG TIMSK1
00937 #define OCIE1B_REG TIMSK1
00938 #define ICIE1_REG TIMSK1
00939
00940
00941 #define PCINT0_REG PCMSK0
00942 #define PCINT1_REG PCMSK0
00943 #define PCINT2_REG PCMSK0
00944 #define PCINT3_REG PCMSK0
00945 #define PCINT4_REG PCMSK0
00946 #define PCINT5_REG PCMSK0
00947 #define PCINT6_REG PCMSK0
00948 #define PCINT7_REG PCMSK0
00949
00950
00951 #define PCINT8_REG PCMSK1
00952 #define PCINT9_REG PCMSK1
00953 #define PCINT10_REG PCMSK1
00954 #define PCINT11_REG PCMSK1
00955 #define PCINT12_REG PCMSK1
00956 #define PCINT13_REG PCMSK1
00957 #define PCINT14_REG PCMSK1
00958 #define PCINT15_REG PCMSK1
00959
00960
00961 #define PINC0_REG PINC
00962 #define PINC1_REG PINC
00963 #define PINC2_REG PINC
00964 #define PINC3_REG PINC
00965 #define PINC4_REG PINC
00966 #define PINC5_REG PINC
00967 #define PINC6_REG PINC
00968 #define PINC7_REG PINC
00969
00970
00971 #define PINB0_REG PINB
00972 #define PINB1_REG PINB
00973 #define PINB2_REG PINB
00974 #define PINB3_REG PINB
00975 #define PINB4_REG PINB
00976 #define PINB5_REG PINB
00977 #define PINB6_REG PINB
00978 #define PINB7_REG PINB
00979
00980
00981 #define INTF0_REG EIFR
00982 #define PCIF0_REG EIFR
00983 #define PCIF1_REG EIFR
00984
00985
00986 #define PING0_REG PING
00987 #define PING1_REG PING
00988 #define PING2_REG PING
00989 #define PING3_REG PING
00990 #define PING4_REG PING
00991 #define PING5_REG PING
00992
00993
00994 #define PINF0_REG PINF
00995 #define PINF1_REG PINF
00996 #define PINF2_REG PINF
00997 #define PINF3_REG PINF
00998 #define PINF4_REG PINF
00999 #define PINF5_REG PINF
01000 #define PINF6_REG PINF
01001 #define PINF7_REG PINF
01002
01003
01004 #define PORTF0_REG PORTF
01005 #define PORTF1_REG PORTF
01006 #define PORTF2_REG PORTF
01007 #define PORTF3_REG PORTF
01008 #define PORTF4_REG PORTF
01009 #define PORTF5_REG PORTF
01010 #define PORTF6_REG PORTF
01011 #define PORTF7_REG PORTF
01012
01013
01014 #define PIND0_REG PIND
01015 #define PIND1_REG PIND
01016 #define PIND2_REG PIND
01017 #define PIND3_REG PIND
01018 #define PIND4_REG PIND
01019 #define PIND5_REG PIND
01020 #define PIND6_REG PIND
01021 #define PIND7_REG PIND
01022
01023
01024 #define OCR1AH0_REG OCR1AH
01025 #define OCR1AH1_REG OCR1AH
01026 #define OCR1AH2_REG OCR1AH
01027 #define OCR1AH3_REG OCR1AH
01028 #define OCR1AH4_REG OCR1AH
01029 #define OCR1AH5_REG OCR1AH
01030 #define OCR1AH6_REG OCR1AH
01031 #define OCR1AH7_REG OCR1AH
01032
01033
01034 #define OCR1AL0_REG OCR1AL
01035 #define OCR1AL1_REG OCR1AL
01036 #define OCR1AL2_REG OCR1AL
01037 #define OCR1AL3_REG OCR1AL
01038 #define OCR1AL4_REG OCR1AL
01039 #define OCR1AL5_REG OCR1AL
01040 #define OCR1AL6_REG OCR1AL
01041 #define OCR1AL7_REG OCR1AL
01042
01043
01044 #define TOV0_REG TIFR0
01045 #define OCF0A_REG TIFR0
01046
01047
01048 #define USIDR0_REG USIDR
01049 #define USIDR1_REG USIDR
01050 #define USIDR2_REG USIDR
01051 #define USIDR3_REG USIDR
01052 #define USIDR4_REG USIDR
01053 #define USIDR5_REG USIDR
01054 #define USIDR6_REG USIDR
01055 #define USIDR7_REG USIDR
01056
01057
01058