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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER0A_AVAILABLE
00088 #define TIMER0B_AVAILABLE
00089 #define TIMER1_AVAILABLE
00090 #define TIMER1A_AVAILABLE
00091 #define TIMER1B_AVAILABLE
00092 #define TIMER2_AVAILABLE
00093 #define TIMER2A_AVAILABLE
00094 #define TIMER2B_AVAILABLE
00095
00096
00097 #define SIG_OVERFLOW0_NUM 0
00098 #define SIG_OVERFLOW1_NUM 1
00099 #define SIG_OVERFLOW2_NUM 2
00100 #define SIG_OVERFLOW_TOTAL_NUM 3
00101
00102
00103 #define SIG_OUTPUT_COMPARE0A_NUM 0
00104 #define SIG_OUTPUT_COMPARE0B_NUM 1
00105 #define SIG_OUTPUT_COMPARE1A_NUM 2
00106 #define SIG_OUTPUT_COMPARE1B_NUM 3
00107 #define SIG_OUTPUT_COMPARE2A_NUM 4
00108 #define SIG_OUTPUT_COMPARE2B_NUM 5
00109 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
00110
00111
00112 #define PWM0A_NUM 0
00113 #define PWM0B_NUM 1
00114 #define PWM1A_NUM 2
00115 #define PWM1B_NUM 3
00116 #define PWM2A_NUM 4
00117 #define PWM2B_NUM 5
00118 #define PWM_TOTAL_NUM 6
00119
00120
00121 #define SIG_INPUT_CAPTURE1_NUM 0
00122 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00123
00124
00125
00126 #define MUX0_REG ADMUX
00127 #define MUX1_REG ADMUX
00128 #define MUX2_REG ADMUX
00129 #define MUX3_REG ADMUX
00130 #define MUX4_REG ADMUX
00131 #define ADLAR_REG ADMUX
00132 #define REFS0_REG ADMUX
00133 #define REFS1_REG ADMUX
00134
00135
00136 #define WDP0_REG WDTCSR
00137 #define WDP1_REG WDTCSR
00138 #define WDP2_REG WDTCSR
00139 #define WDE_REG WDTCSR
00140 #define WDCE_REG WDTCSR
00141 #define WDP3_REG WDTCSR
00142 #define WDIE_REG WDTCSR
00143 #define WDIF_REG WDTCSR
00144
00145
00146 #define EEDR0_REG EEDR
00147 #define EEDR1_REG EEDR
00148 #define EEDR2_REG EEDR
00149 #define EEDR3_REG EEDR
00150 #define EEDR4_REG EEDR
00151 #define EEDR5_REG EEDR
00152 #define EEDR6_REG EEDR
00153 #define EEDR7_REG EEDR
00154
00155
00156 #define ACIS0_REG ACSR
00157 #define ACIS1_REG ACSR
00158 #define ACIC_REG ACSR
00159 #define ACIE_REG ACSR
00160 #define ACI_REG ACSR
00161 #define ACO_REG ACSR
00162 #define ACBG_REG ACSR
00163 #define ACD_REG ACSR
00164
00165
00166 #define SPR00_REG SPCR0
00167 #define SPR10_REG SPCR0
00168 #define CPHA0_REG SPCR0
00169 #define CPOL0_REG SPCR0
00170 #define MSTR0_REG SPCR0
00171 #define DORD0_REG SPCR0
00172 #define SPE0_REG SPCR0
00173 #define SPIE0_REG SPCR0
00174
00175
00176 #define RAMPZ0_REG RAMPZ
00177
00178
00179 #define OCR2B_0_REG OCR2B
00180 #define OCR2B_1_REG OCR2B
00181 #define OCR2B_2_REG OCR2B
00182 #define OCR2B_3_REG OCR2B
00183 #define OCR2B_4_REG OCR2B
00184 #define OCR2B_5_REG OCR2B
00185 #define OCR2B_6_REG OCR2B
00186 #define OCR2B_7_REG OCR2B
00187
00188
00189 #define OCR2A_0_REG OCR2A
00190 #define OCR2A_1_REG OCR2A
00191 #define OCR2A_2_REG OCR2A
00192 #define OCR2A_3_REG OCR2A
00193 #define OCR2A_4_REG OCR2A
00194 #define OCR2A_5_REG OCR2A
00195 #define OCR2A_6_REG OCR2A
00196 #define OCR2A_7_REG OCR2A
00197
00198
00199 #define SP8_REG SPH
00200 #define SP9_REG SPH
00201 #define SP10_REG SPH
00202 #define SP11_REG SPH
00203 #define SP12_REG SPH
00204
00205
00206 #define ICR1L0_REG ICR1L
00207 #define ICR1L1_REG ICR1L
00208 #define ICR1L2_REG ICR1L
00209 #define ICR1L3_REG ICR1L
00210 #define ICR1L4_REG ICR1L
00211 #define ICR1L5_REG ICR1L
00212 #define ICR1L6_REG ICR1L
00213 #define ICR1L7_REG ICR1L
00214
00215
00216 #define TWPS0_REG TWSR
00217 #define TWPS1_REG TWSR
00218 #define TWS3_REG TWSR
00219 #define TWS4_REG TWSR
00220 #define TWS5_REG TWSR
00221 #define TWS6_REG TWSR
00222 #define TWS7_REG TWSR
00223
00224
00225 #define MPCM0_REG UCSR0A
00226 #define U2X0_REG UCSR0A
00227 #define UPE0_REG UCSR0A
00228 #define DOR0_REG UCSR0A
00229 #define FE0_REG UCSR0A
00230 #define UDRE0_REG UCSR0A
00231 #define TXC0_REG UCSR0A
00232 #define RXC0_REG UCSR0A
00233
00234
00235 #define UCPOL0_REG UCSR0C
00236 #define UCSZ00_REG UCSR0C
00237 #define UCSZ01_REG UCSR0C
00238 #define USBS0_REG UCSR0C
00239 #define UPM00_REG UCSR0C
00240 #define UPM01_REG UCSR0C
00241 #define UMSEL00_REG UCSR0C
00242 #define UMSEL01_REG UCSR0C
00243
00244
00245 #define TXB80_REG UCSR0B
00246 #define RXB80_REG UCSR0B
00247 #define UCSZ02_REG UCSR0B
00248 #define TXEN0_REG UCSR0B
00249 #define RXEN0_REG UCSR0B
00250 #define UDRIE0_REG UCSR0B
00251 #define TXCIE0_REG UCSR0B
00252 #define RXCIE0_REG UCSR0B
00253
00254
00255 #define TCNT1H0_REG TCNT1H
00256 #define TCNT1H1_REG TCNT1H
00257 #define TCNT1H2_REG TCNT1H
00258 #define TCNT1H3_REG TCNT1H
00259 #define TCNT1H4_REG TCNT1H
00260 #define TCNT1H5_REG TCNT1H
00261 #define TCNT1H6_REG TCNT1H
00262 #define TCNT1H7_REG TCNT1H
00263
00264
00265 #define PORTC0_REG PORTC
00266 #define PORTC1_REG PORTC
00267 #define PORTC2_REG PORTC
00268 #define PORTC3_REG PORTC
00269 #define PORTC4_REG PORTC
00270 #define PORTC5_REG PORTC
00271 #define PORTC6_REG PORTC
00272 #define PORTC7_REG PORTC
00273
00274
00275 #define PORTA0_REG PORTA
00276 #define PORTA1_REG PORTA
00277 #define PORTA2_REG PORTA
00278 #define PORTA3_REG PORTA
00279 #define PORTA4_REG PORTA
00280 #define PORTA5_REG PORTA
00281 #define PORTA6_REG PORTA
00282 #define PORTA7_REG PORTA
00283
00284
00285 #define UDR1_0_REG UDR1
00286 #define UDR1_1_REG UDR1
00287 #define UDR1_2_REG UDR1
00288 #define UDR1_3_REG UDR1
00289 #define UDR1_4_REG UDR1
00290 #define UDR1_5_REG UDR1
00291 #define UDR1_6_REG UDR1
00292 #define UDR1_7_REG UDR1
00293
00294
00295 #define UDR0_0_REG UDR0
00296 #define UDR0_1_REG UDR0
00297 #define UDR0_2_REG UDR0
00298 #define UDR0_3_REG UDR0
00299 #define UDR0_4_REG UDR0
00300 #define UDR0_5_REG UDR0
00301 #define UDR0_6_REG UDR0
00302 #define UDR0_7_REG UDR0
00303
00304
00305 #define ISC00_REG EICRA
00306 #define ISC01_REG EICRA
00307 #define ISC10_REG EICRA
00308 #define ISC11_REG EICRA
00309 #define ISC20_REG EICRA
00310 #define ISC21_REG EICRA
00311
00312
00313 #define ADC0D_REG DIDR0
00314 #define ADC1D_REG DIDR0
00315 #define ADC2D_REG DIDR0
00316 #define ADC3D_REG DIDR0
00317 #define ADC4D_REG DIDR0
00318 #define ADC5D_REG DIDR0
00319 #define ADC6D_REG DIDR0
00320 #define ADC7D_REG DIDR0
00321
00322
00323 #define AIN0D_REG DIDR1
00324 #define AIN1D_REG DIDR1
00325
00326
00327 #define SPDRB0_REG SPDR0
00328 #define SPDRB1_REG SPDR0
00329 #define SPDRB2_REG SPDR0
00330 #define SPDRB3_REG SPDR0
00331 #define SPDRB4_REG SPDR0
00332 #define SPDRB5_REG SPDR0
00333 #define SPDRB6_REG SPDR0
00334 #define SPDRB7_REG SPDR0
00335
00336
00337 #define TCR2BUB_REG ASSR
00338 #define TCR2AUB_REG ASSR
00339 #define OCR2BUB_REG ASSR
00340 #define OCR2AUB_REG ASSR
00341 #define TCN2UB_REG ASSR
00342 #define AS2_REG ASSR
00343 #define EXCLK_REG ASSR
00344
00345
00346 #define CLKPS0_REG CLKPR
00347 #define CLKPS1_REG CLKPR
00348 #define CLKPS2_REG CLKPR
00349 #define CLKPS3_REG CLKPR
00350 #define CLKPCE_REG CLKPR
00351
00352
00353 #define C_REG SREG
00354 #define Z_REG SREG
00355 #define N_REG SREG
00356 #define V_REG SREG
00357 #define S_REG SREG
00358 #define H_REG SREG
00359 #define T_REG SREG
00360 #define I_REG SREG
00361
00362
00363 #define UBRR_0_REG UBRR1L
00364 #define UBRR_1_REG UBRR1L
00365 #define UBRR_2_REG UBRR1L
00366 #define UBRR_3_REG UBRR1L
00367 #define UBRR_4_REG UBRR1L
00368 #define UBRR_5_REG UBRR1L
00369 #define UBRR_6_REG UBRR1L
00370 #define UBRR_7_REG UBRR1L
00371
00372
00373 #define DDC0_REG DDRC
00374 #define DDC1_REG DDRC
00375 #define DDC2_REG DDRC
00376 #define DDC3_REG DDRC
00377 #define DDC4_REG DDRC
00378 #define DDC5_REG DDRC
00379 #define DDC6_REG DDRC
00380 #define DDC7_REG DDRC
00381
00382
00383 #define DDA0_REG DDRA
00384 #define DDA1_REG DDRA
00385 #define DDA2_REG DDRA
00386 #define DDA3_REG DDRA
00387 #define DDA4_REG DDRA
00388 #define DDA5_REG DDRA
00389 #define DDA6_REG DDRA
00390 #define DDA7_REG DDRA
00391
00392
00393 #define UBRR_8_REG UBRR1H
00394 #define UBRR_9_REG UBRR1H
00395 #define UBRR_10_REG UBRR1H
00396 #define UBRR_11_REG UBRR1H
00397
00398
00399 #define FOC1B_REG TCCR1C
00400 #define FOC1A_REG TCCR1C
00401
00402
00403 #define CS10_REG TCCR1B
00404 #define CS11_REG TCCR1B
00405 #define CS12_REG TCCR1B
00406 #define WGM12_REG TCCR1B
00407 #define WGM13_REG TCCR1B
00408 #define ICES1_REG TCCR1B
00409 #define ICNC1_REG TCCR1B
00410
00411
00412 #define CAL0_REG OSCCAL
00413 #define CAL1_REG OSCCAL
00414 #define CAL2_REG OSCCAL
00415 #define CAL3_REG OSCCAL
00416 #define CAL4_REG OSCCAL
00417 #define CAL5_REG OSCCAL
00418 #define CAL6_REG OSCCAL
00419 #define CAL7_REG OSCCAL
00420
00421
00422 #define GPIOR10_REG GPIOR1
00423 #define GPIOR11_REG GPIOR1
00424 #define GPIOR12_REG GPIOR1
00425 #define GPIOR13_REG GPIOR1
00426 #define GPIOR14_REG GPIOR1
00427 #define GPIOR15_REG GPIOR1
00428 #define GPIOR16_REG GPIOR1
00429 #define GPIOR17_REG GPIOR1
00430
00431
00432 #define GPIOR00_REG GPIOR0
00433 #define GPIOR01_REG GPIOR0
00434 #define GPIOR02_REG GPIOR0
00435 #define GPIOR03_REG GPIOR0
00436 #define GPIOR04_REG GPIOR0
00437 #define GPIOR05_REG GPIOR0
00438 #define GPIOR06_REG GPIOR0
00439 #define GPIOR07_REG GPIOR0
00440
00441
00442 #define GPIOR20_REG GPIOR2
00443 #define GPIOR21_REG GPIOR2
00444 #define GPIOR22_REG GPIOR2
00445 #define GPIOR23_REG GPIOR2
00446 #define GPIOR24_REG GPIOR2
00447 #define GPIOR25_REG GPIOR2
00448 #define GPIOR26_REG GPIOR2
00449 #define GPIOR27_REG GPIOR2
00450
00451
00452 #define SPI2X0_REG SPSR0
00453 #define WCOL0_REG SPSR0
00454 #define SPIF0_REG SPSR0
00455
00456
00457 #define PCIE0_REG PCICR
00458 #define PCIE1_REG PCICR
00459 #define PCIE2_REG PCICR
00460 #define PCIE3_REG PCICR
00461
00462
00463 #define TCNT2_0_REG TCNT2
00464 #define TCNT2_1_REG TCNT2
00465 #define TCNT2_2_REG TCNT2
00466 #define TCNT2_3_REG TCNT2
00467 #define TCNT2_4_REG TCNT2
00468 #define TCNT2_5_REG TCNT2
00469 #define TCNT2_6_REG TCNT2
00470 #define TCNT2_7_REG TCNT2
00471
00472
00473 #define TCNT0_0_REG TCNT0
00474 #define TCNT0_1_REG TCNT0
00475 #define TCNT0_2_REG TCNT0
00476 #define TCNT0_3_REG TCNT0
00477 #define TCNT0_4_REG TCNT0
00478 #define TCNT0_5_REG TCNT0
00479 #define TCNT0_6_REG TCNT0
00480 #define TCNT0_7_REG TCNT0
00481
00482
00483 #define TWGCE_REG TWAR
00484 #define TWA0_REG TWAR
00485 #define TWA1_REG TWAR
00486 #define TWA2_REG TWAR
00487 #define TWA3_REG TWAR
00488 #define TWA4_REG TWAR
00489 #define TWA5_REG TWAR
00490 #define TWA6_REG TWAR
00491
00492
00493 #define CS00_REG TCCR0B
00494 #define CS01_REG TCCR0B
00495 #define CS02_REG TCCR0B
00496 #define WGM02_REG TCCR0B
00497 #define FOC0B_REG TCCR0B
00498 #define FOC0A_REG TCCR0B
00499
00500
00501 #define WGM00_REG TCCR0A
00502 #define WGM01_REG TCCR0A
00503 #define COM0B0_REG TCCR0A
00504 #define COM0B1_REG TCCR0A
00505 #define COM0A0_REG TCCR0A
00506 #define COM0A1_REG TCCR0A
00507
00508
00509 #define TOV2_REG TIFR2
00510 #define OCF2A_REG TIFR2
00511 #define OCF2B_REG TIFR2
00512
00513
00514 #define TOV0_REG TIFR0
00515 #define OCF0A_REG TIFR0
00516 #define OCF0B_REG TIFR0
00517
00518
00519 #define TOV1_REG TIFR1
00520 #define OCF1A_REG TIFR1
00521 #define OCF1B_REG TIFR1
00522 #define ICF1_REG TIFR1
00523
00524
00525 #define PSRSYNC_REG GTCCR
00526 #define TSM_REG GTCCR
00527 #define PSRASY_REG GTCCR
00528
00529
00530 #define TWBR0_REG TWBR
00531 #define TWBR1_REG TWBR
00532 #define TWBR2_REG TWBR
00533 #define TWBR3_REG TWBR
00534 #define TWBR4_REG TWBR
00535 #define TWBR5_REG TWBR
00536 #define TWBR6_REG TWBR
00537 #define TWBR7_REG TWBR
00538
00539
00540 #define ICR1H0_REG ICR1H
00541 #define ICR1H1_REG ICR1H
00542 #define ICR1H2_REG ICR1H
00543 #define ICR1H3_REG ICR1H
00544 #define ICR1H4_REG ICR1H
00545 #define ICR1H5_REG ICR1H
00546 #define ICR1H6_REG ICR1H
00547 #define ICR1H7_REG ICR1H
00548
00549
00550
00551
00552
00553
00554
00555
00556
00557
00558
00559
00560 #define PCIF0_REG PCIFR
00561 #define PCIF1_REG PCIFR
00562 #define PCIF2_REG PCIFR
00563 #define PCIF3_REG PCIFR
00564
00565
00566 #define SP0_REG SPL
00567 #define SP1_REG SPL
00568 #define SP2_REG SPL
00569 #define SP3_REG SPL
00570 #define SP4_REG SPL
00571 #define SP5_REG SPL
00572 #define SP6_REG SPL
00573 #define SP7_REG SPL
00574
00575
00576
00577
00578
00579
00580
00581
00582
00583
00584
00585
00586 #define EERE_REG EECR
00587 #define EEPE_REG EECR
00588 #define EEMPE_REG EECR
00589 #define EERIE_REG EECR
00590 #define EEPM0_REG EECR
00591 #define EEPM1_REG EECR
00592
00593
00594 #define SE_REG SMCR
00595 #define SM0_REG SMCR
00596 #define SM1_REG SMCR
00597 #define SM2_REG SMCR
00598
00599
00600 #define TWIE_REG TWCR
00601 #define TWEN_REG TWCR
00602 #define TWWC_REG TWCR
00603 #define TWSTO_REG TWCR
00604 #define TWSTA_REG TWCR
00605 #define TWEA_REG TWCR
00606 #define TWINT_REG TWCR
00607
00608
00609 #define WGM20_REG TCCR2A
00610 #define WGM21_REG TCCR2A
00611 #define COM2B0_REG TCCR2A
00612 #define COM2B1_REG TCCR2A
00613 #define COM2A0_REG TCCR2A
00614 #define COM2A1_REG TCCR2A
00615
00616
00617 #define CS20_REG TCCR2B
00618 #define CS21_REG TCCR2B
00619 #define CS22_REG TCCR2B
00620 #define WGM22_REG TCCR2B
00621 #define FOC2B_REG TCCR2B
00622 #define FOC2A_REG TCCR2B
00623
00624
00625 #define UBRR8_REG UBRR0H
00626 #define UBRR9_REG UBRR0H
00627 #define UBRR10_REG UBRR0H
00628 #define UBRR11_REG UBRR0H
00629
00630
00631 #define UBRR0_REG UBRR0L
00632 #define UBRR1_REG UBRR0L
00633 #define UBRR2_REG UBRR0L
00634 #define UBRR3_REG UBRR0L
00635 #define UBRR4_REG UBRR0L
00636 #define UBRR5_REG UBRR0L
00637 #define UBRR6_REG UBRR0L
00638 #define UBRR7_REG UBRR0L
00639
00640
00641 #define EEAR8_REG EEARH
00642 #define EEAR9_REG EEARH
00643 #define EEAR10_REG EEARH
00644 #define EEAR11_REG EEARH
00645
00646
00647 #define EEAR0_REG EEARL
00648 #define EEAR1_REG EEARL
00649 #define EEAR2_REG EEARL
00650 #define EEAR3_REG EEARL
00651 #define EEAR4_REG EEARL
00652 #define EEAR5_REG EEARL
00653 #define EEAR6_REG EEARL
00654 #define EEAR7_REG EEARL
00655
00656
00657 #define JTD_REG MCUCR
00658 #define IVCE_REG MCUCR
00659 #define IVSEL_REG MCUCR
00660 #define PUD_REG MCUCR
00661 #define BODSE_REG MCUCR
00662 #define BODS_REG MCUCR
00663
00664
00665 #define JTRF_REG MCUSR
00666 #define PORF_REG MCUSR
00667 #define EXTRF_REG MCUSR
00668 #define BORF_REG MCUSR
00669 #define WDRF_REG MCUSR
00670
00671
00672 #define OCDR0_REG OCDR
00673 #define OCDR1_REG OCDR
00674 #define OCDR2_REG OCDR
00675 #define OCDR3_REG OCDR
00676 #define OCDR4_REG OCDR
00677 #define OCDR5_REG OCDR
00678 #define OCDR6_REG OCDR
00679 #define OCDR7_REG OCDR
00680
00681
00682 #define PINA0_REG PINA
00683 #define PINA1_REG PINA
00684 #define PINA2_REG PINA
00685 #define PINA3_REG PINA
00686 #define PINA4_REG PINA
00687 #define PINA5_REG PINA
00688 #define PINA6_REG PINA
00689 #define PINA7_REG PINA
00690
00691
00692 #define TXB81_REG UCSR1B
00693 #define RXB81_REG UCSR1B
00694 #define UCSZ12_REG UCSR1B
00695 #define TXEN1_REG UCSR1B
00696 #define RXEN1_REG UCSR1B
00697 #define UDRIE1_REG UCSR1B
00698 #define TXCIE1_REG UCSR1B
00699 #define RXCIE1_REG UCSR1B
00700
00701
00702 #define UCPOL1_REG UCSR1C
00703 #define UCSZ10_REG UCSR1C
00704 #define UCSZ11_REG UCSR1C
00705 #define USBS1_REG UCSR1C
00706 #define UPM10_REG UCSR1C
00707 #define UPM11_REG UCSR1C
00708 #define UMSEL10_REG UCSR1C
00709 #define UMSEL11_REG UCSR1C
00710
00711
00712 #define MPCM1_REG UCSR1A
00713 #define U2X1_REG UCSR1A
00714 #define UPE1_REG UCSR1A
00715 #define DOR1_REG UCSR1A
00716 #define FE1_REG UCSR1A
00717 #define UDRE1_REG UCSR1A
00718 #define TXC1_REG UCSR1A
00719 #define RXC1_REG UCSR1A
00720
00721
00722 #define DDB0_REG DDRB
00723 #define DDB1_REG DDRB
00724 #define DDB2_REG DDRB
00725 #define DDB3_REG DDRB
00726 #define DDB4_REG DDRB
00727 #define DDB5_REG DDRB
00728 #define DDB6_REG DDRB
00729 #define DDB7_REG DDRB
00730
00731
00732 #define TWD0_REG TWDR
00733 #define TWD1_REG TWDR
00734 #define TWD2_REG TWDR
00735 #define TWD3_REG TWDR
00736 #define TWD4_REG TWDR
00737 #define TWD5_REG TWDR
00738 #define TWD6_REG TWDR
00739 #define TWD7_REG TWDR
00740
00741
00742 #define TWAM0_REG TWAMR
00743 #define TWAM1_REG TWAMR
00744 #define TWAM2_REG TWAMR
00745 #define TWAM3_REG TWAMR
00746 #define TWAM4_REG TWAMR
00747 #define TWAM5_REG TWAMR
00748 #define TWAM6_REG TWAMR
00749
00750
00751 #define ADPS0_REG ADCSRA
00752 #define ADPS1_REG ADCSRA
00753 #define ADPS2_REG ADCSRA
00754 #define ADIE_REG ADCSRA
00755 #define ADIF_REG ADCSRA
00756 #define ADATE_REG ADCSRA
00757 #define ADSC_REG ADCSRA
00758 #define ADEN_REG ADCSRA
00759
00760
00761 #define ACME_REG ADCSRB
00762 #define ADTS0_REG ADCSRB
00763 #define ADTS1_REG ADCSRB
00764 #define ADTS2_REG ADCSRB
00765
00766
00767 #define PRADC_REG PRR0
00768 #define PRUSART0_REG PRR0
00769 #define PRSPI_REG PRR0
00770 #define PRTIM1_REG PRR0
00771 #define PRUSART1_REG PRR0
00772 #define PRTIM0_REG PRR0
00773 #define PRTIM2_REG PRR0
00774 #define PRTWI_REG PRR0
00775
00776
00777 #define WGM10_REG TCCR1A
00778 #define WGM11_REG TCCR1A
00779 #define COM1B0_REG TCCR1A
00780 #define COM1B1_REG TCCR1A
00781 #define COM1A0_REG TCCR1A
00782 #define COM1A1_REG TCCR1A
00783
00784
00785 #define OCROA_0_REG OCR0A
00786 #define OCROA_1_REG OCR0A
00787 #define OCROA_2_REG OCR0A
00788 #define OCROA_3_REG OCR0A
00789 #define OCROA_4_REG OCR0A
00790 #define OCROA_5_REG OCR0A
00791 #define OCROA_6_REG OCR0A
00792 #define OCROA_7_REG OCR0A
00793
00794
00795 #define OCR0B_0_REG OCR0B
00796 #define OCR0B_1_REG OCR0B
00797 #define OCR0B_2_REG OCR0B
00798 #define OCR0B_3_REG OCR0B
00799 #define OCR0B_4_REG OCR0B
00800 #define OCR0B_5_REG OCR0B
00801 #define OCR0B_6_REG OCR0B
00802 #define OCR0B_7_REG OCR0B
00803
00804
00805 #define TCNT1L0_REG TCNT1L
00806 #define TCNT1L1_REG TCNT1L
00807 #define TCNT1L2_REG TCNT1L
00808 #define TCNT1L3_REG TCNT1L
00809 #define TCNT1L4_REG TCNT1L
00810 #define TCNT1L5_REG TCNT1L
00811 #define TCNT1L6_REG TCNT1L
00812 #define TCNT1L7_REG TCNT1L
00813
00814
00815 #define DDD0_REG DDRD
00816 #define DDD1_REG DDRD
00817 #define DDD2_REG DDRD
00818 #define DDD3_REG DDRD
00819 #define DDD4_REG DDRD
00820 #define DDD5_REG DDRD
00821 #define DDD6_REG DDRD
00822 #define DDD7_REG DDRD
00823
00824
00825 #define PORTD0_REG PORTD
00826 #define PORTD1_REG PORTD
00827 #define PORTD2_REG PORTD
00828 #define PORTD3_REG PORTD
00829 #define PORTD4_REG PORTD
00830 #define PORTD5_REG PORTD
00831 #define PORTD6_REG PORTD
00832 #define PORTD7_REG PORTD
00833
00834
00835 #define SPMEN_REG SPMCSR
00836 #define PGERS_REG SPMCSR
00837 #define PGWRT_REG SPMCSR
00838 #define BLBSET_REG SPMCSR
00839 #define RWWSRE_REG SPMCSR
00840 #define SIGRD_REG SPMCSR
00841 #define RWWSB_REG SPMCSR
00842 #define SPMIE_REG SPMCSR
00843
00844
00845 #define PORTB0_REG PORTB
00846 #define PORTB1_REG PORTB
00847 #define PORTB2_REG PORTB
00848 #define PORTB3_REG PORTB
00849 #define PORTB4_REG PORTB
00850 #define PORTB5_REG PORTB
00851 #define PORTB6_REG PORTB
00852 #define PORTB7_REG PORTB
00853
00854
00855 #define ADCL0_REG ADCL
00856 #define ADCL1_REG ADCL
00857 #define ADCL2_REG ADCL
00858 #define ADCL3_REG ADCL
00859 #define ADCL4_REG ADCL
00860 #define ADCL5_REG ADCL
00861 #define ADCL6_REG ADCL
00862 #define ADCL7_REG ADCL
00863
00864
00865 #define ADCH0_REG ADCH
00866 #define ADCH1_REG ADCH
00867 #define ADCH2_REG ADCH
00868 #define ADCH3_REG ADCH
00869 #define ADCH4_REG ADCH
00870 #define ADCH5_REG ADCH
00871 #define ADCH6_REG ADCH
00872 #define ADCH7_REG ADCH
00873
00874
00875 #define TOIE2_REG TIMSK2
00876 #define OCIE2A_REG TIMSK2
00877 #define OCIE2B_REG TIMSK2
00878
00879
00880 #define INT0_REG EIMSK
00881 #define INT1_REG EIMSK
00882 #define INT2_REG EIMSK
00883
00884
00885 #define TOIE0_REG TIMSK0
00886 #define OCIE0A_REG TIMSK0
00887 #define OCIE0B_REG TIMSK0
00888
00889
00890 #define TOIE1_REG TIMSK1
00891 #define OCIE1A_REG TIMSK1
00892 #define OCIE1B_REG TIMSK1
00893 #define ICIE1_REG TIMSK1
00894
00895
00896 #define PCINT0_REG PCMSK0
00897 #define PCINT1_REG PCMSK0
00898 #define PCINT2_REG PCMSK0
00899 #define PCINT3_REG PCMSK0
00900 #define PCINT4_REG PCMSK0
00901 #define PCINT5_REG PCMSK0
00902 #define PCINT6_REG PCMSK0
00903 #define PCINT7_REG PCMSK0
00904
00905
00906 #define PCINT8_REG PCMSK1
00907 #define PCINT9_REG PCMSK1
00908 #define PCINT10_REG PCMSK1
00909 #define PCINT11_REG PCMSK1
00910 #define PCINT12_REG PCMSK1
00911 #define PCINT13_REG PCMSK1
00912 #define PCINT14_REG PCMSK1
00913 #define PCINT15_REG PCMSK1
00914
00915
00916 #define PCINT16_REG PCMSK2
00917 #define PCINT17_REG PCMSK2
00918 #define PCINT18_REG PCMSK2
00919 #define PCINT19_REG PCMSK2
00920 #define PCINT20_REG PCMSK2
00921 #define PCINT21_REG PCMSK2
00922 #define PCINT22_REG PCMSK2
00923 #define PCINT23_REG PCMSK2
00924
00925
00926 #define PCINT24_REG PCMSK3
00927 #define PCINT25_REG PCMSK3
00928 #define PCINT26_REG PCMSK3
00929 #define PCINT27_REG PCMSK3
00930 #define PCINT28_REG PCMSK3
00931 #define PCINT29_REG PCMSK3
00932 #define PCINT30_REG PCMSK3
00933 #define PCINT31_REG PCMSK3
00934
00935
00936 #define PINC0_REG PINC
00937 #define PINC1_REG PINC
00938 #define PINC2_REG PINC
00939 #define PINC3_REG PINC
00940 #define PINC4_REG PINC
00941 #define PINC5_REG PINC
00942 #define PINC6_REG PINC
00943 #define PINC7_REG PINC
00944
00945
00946 #define PINB0_REG PINB
00947 #define PINB1_REG PINB
00948 #define PINB2_REG PINB
00949 #define PINB3_REG PINB
00950 #define PINB4_REG PINB
00951 #define PINB5_REG PINB
00952 #define PINB6_REG PINB
00953 #define PINB7_REG PINB
00954
00955
00956 #define INTF0_REG EIFR
00957 #define INTF1_REG EIFR
00958 #define INTF2_REG EIFR
00959
00960
00961 #define PIND0_REG PIND
00962 #define PIND1_REG PIND
00963 #define PIND2_REG PIND
00964 #define PIND3_REG PIND
00965 #define PIND4_REG PIND
00966 #define PIND5_REG PIND
00967 #define PIND6_REG PIND
00968 #define PIND7_REG PIND
00969
00970
00971
00972
00973
00974
00975
00976
00977
00978
00979
00980
00981
00982
00983
00984
00985
00986
00987
00988
00989
00990
00991 #define ADC0_PORT PORTA
00992 #define ADC0_BIT 0
00993 #define PCINT0_PORT PORTA
00994 #define PCINT0_BIT 0
00995
00996 #define ADC1_PORT PORTA
00997 #define ADC1_BIT 1
00998 #define PCINT1_PORT PORTA
00999 #define PCINT1_BIT 1
01000
01001 #define ADC2_PORT PORTA
01002 #define ADC2_BIT 2
01003 #define PCINT2_PORT PORTA
01004 #define PCINT2_BIT 2
01005
01006 #define ADC3_PORT PORTA
01007 #define ADC3_BIT 3
01008 #define PCINT3_PORT PORTA
01009 #define PCINT3_BIT 3
01010
01011 #define ADC4_PORT PORTA
01012 #define ADC4_BIT 4
01013 #define PCINT4_PORT PORTA
01014 #define PCINT4_BIT 4
01015
01016 #define ADC5_PORT PORTA
01017 #define ADC5_BIT 5
01018 #define PCINT5_PORT PORTA
01019 #define PCINT5_BIT 5
01020
01021 #define ADC6_PORT PORTA
01022 #define ADC6_BIT 6
01023 #define PCINT6_PORT PORTA
01024 #define PCINT6_BIT 6
01025
01026 #define ADC7_PORT PORTA
01027 #define ADC7_BIT 7
01028 #define PCINT7_PORT PORTA
01029 #define PCINT7_BIT 7
01030
01031 #define XCK_PORT PORTB
01032 #define XCK_BIT 0
01033 #define T0_PORT PORTB
01034 #define T0_BIT 0
01035 #define PCINT9_PORT PORTB
01036 #define PCINT9_BIT 0
01037
01038 #define T1_PORT PORTB
01039 #define T1_BIT 1
01040 #define CLKO_PORT PORTB
01041 #define CLKO_BIT 1
01042 #define PCINT9_PORT PORTB
01043 #define PCINT9_BIT 1
01044
01045 #define AIN0_PORT PORTB
01046 #define AIN0_BIT 2
01047 #define INT2_PORT PORTB
01048 #define INT2_BIT 2
01049 #define PCINT10_PORT PORTB
01050 #define PCINT10_BIT 2
01051
01052 #define AIN1_PORT PORTB
01053 #define AIN1_BIT 3
01054 #define OC0A_PORT PORTB
01055 #define OC0A_BIT 3
01056 #define PCINT11_PORT PORTB
01057 #define PCINT11_BIT 3
01058
01059 #define SS_PORT PORTB
01060 #define SS_BIT 4
01061 #define OC0B_PORT PORTB
01062 #define OC0B_BIT 4
01063 #define PCINT12_PORT PORTB
01064 #define PCINT12_BIT 4
01065
01066 #define MOSI_PORT PORTB
01067 #define MOSI_BIT 5
01068 #define PCINT13_PORT PORTB
01069 #define PCINT13_BIT 5
01070
01071 #define MISO_PORT PORTB
01072 #define MISO_BIT 6
01073 #define PCINT14_PORT PORTB
01074 #define PCINT14_BIT 6
01075
01076 #define SCK_PORT PORTB
01077 #define SCK_BIT 7
01078 #define PCINT15_PORT PORTB
01079 #define PCINT15_BIT 7
01080
01081 #define SCL_PORT PORTC
01082 #define SCL_BIT 0
01083 #define PCINT16_PORT PORTC
01084 #define PCINT16_BIT 0
01085
01086 #define SDA_PORT PORTC
01087 #define SDA_BIT 1
01088 #define PCINT17_PORT PORTC
01089 #define PCINT17_BIT 1
01090
01091 #define TCK_PORT PORTC
01092 #define TCK_BIT 2
01093 #define PCINT18_PORT PORTC
01094 #define PCINT18_BIT 2
01095
01096 #define TMS_PORT PORTC
01097 #define TMS_BIT 3
01098 #define PCINT19_PORT PORTC
01099 #define PCINT19_BIT 3
01100
01101 #define TDO_PORT PORTC
01102 #define TDO_BIT 4
01103 #define PCINT20_PORT PORTC
01104 #define PCINT20_BIT 4
01105
01106 #define TDI_PORT PORTC
01107 #define TDI_BIT 5
01108 #define PCINT21_PORT PORTC
01109 #define PCINT21_BIT 5
01110
01111 #define TOSC1_PORT PORTC
01112 #define TOSC1_BIT 6
01113 #define PCINT22_PORT PORTC
01114 #define PCINT22_BIT 6
01115
01116 #define TOSC2_PORT PORTC
01117 #define TOSC2_BIT 7
01118 #define PCINT23_PORT PORTC
01119 #define PCINT23_BIT 7
01120
01121 #define RXD_PORT PORTD
01122 #define RXD_BIT 0
01123 #define PCINT24_PORT PORTD
01124 #define PCINT24_BIT 0
01125
01126 #define TXD_PORT PORTD
01127 #define TXD_BIT 1
01128 #define PCINT25_PORT PORTD
01129 #define PCINT25_BIT 1
01130
01131 #define INT0_PORT PORTD
01132 #define INT0_BIT 2
01133 #define PCINT26_PORT PORTD
01134 #define PCINT26_BIT 2
01135
01136 #define INT1_PORT PORTD
01137 #define INT1_BIT 3
01138 #define PCINT27_PORT PORTD
01139 #define PCINT27_BIT 3
01140
01141 #define OC1B_PORT PORTD
01142 #define OC1B_BIT 4
01143 #define PCINT28_PORT PORTD
01144 #define PCINT28_BIT 4
01145
01146 #define OC1A_PORT PORTD
01147 #define OC1A_BIT 5
01148 #define PCINT29_PORT PORTD
01149 #define PCINT29_BIT 5
01150
01151 #define ICP_PORT PORTD
01152 #define ICP_BIT 6
01153 #define OC2B_PORT PORTD
01154 #define OC2B_BIT 6
01155 #define PCINT30_PORT PORTD
01156 #define PCINT30_BIT 6
01157
01158 #define OC2A_PORT PORTD
01159 #define OC2A_BIT 7
01160 #define PCINT31_PORT PORTD
01161 #define PCINT31_BIT 7
01162
01163