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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_16 6
00092 #define TIMER3_PRESCALER_DIV_32 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 16
00101 #define TIMER3_PRESCALER_REG_7 32
00102
00103
00104
00105 #define TIMER0_AVAILABLE
00106 #define TIMER1_AVAILABLE
00107 #define TIMER1A_AVAILABLE
00108 #define TIMER1B_AVAILABLE
00109 #define TIMER2_AVAILABLE
00110 #define TIMER3_AVAILABLE
00111 #define TIMER3A_AVAILABLE
00112 #define TIMER3B_AVAILABLE
00113
00114
00115 #define SIG_OVERFLOW0_NUM 0
00116 #define SIG_OVERFLOW1_NUM 1
00117 #define SIG_OVERFLOW2_NUM 2
00118 #define SIG_OVERFLOW3_NUM 3
00119 #define SIG_OVERFLOW_TOTAL_NUM 4
00120
00121
00122 #define SIG_OUTPUT_COMPARE0_NUM 0
00123 #define SIG_OUTPUT_COMPARE1A_NUM 1
00124 #define SIG_OUTPUT_COMPARE1B_NUM 2
00125 #define SIG_OUTPUT_COMPARE2_NUM 3
00126 #define SIG_OUTPUT_COMPARE3A_NUM 4
00127 #define SIG_OUTPUT_COMPARE3B_NUM 5
00128 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 6
00129
00130
00131 #define PWM0_NUM 0
00132 #define PWM1A_NUM 1
00133 #define PWM1B_NUM 2
00134 #define PWM2_NUM 3
00135 #define PWM3A_NUM 4
00136 #define PWM3B_NUM 5
00137 #define PWM_TOTAL_NUM 6
00138
00139
00140 #define SIG_INPUT_CAPTURE1_NUM 0
00141 #define SIG_INPUT_CAPTURE3_NUM 1
00142 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00143
00144
00145
00146 #define SPDR0_REG SPDR
00147 #define SPDR1_REG SPDR
00148 #define SPDR2_REG SPDR
00149 #define SPDR3_REG SPDR
00150 #define SPDR4_REG SPDR
00151 #define SPDR5_REG SPDR
00152 #define SPDR6_REG SPDR
00153 #define SPDR7_REG SPDR
00154
00155
00156 #define CLKPS0_REG CLKPR
00157 #define CLKPS1_REG CLKPR
00158 #define CLKPS2_REG CLKPR
00159 #define CLKPS3_REG CLKPR
00160 #define CLKPCE_REG CLKPR
00161
00162
00163 #define WDP0_REG WDTCR
00164 #define WDP1_REG WDTCR
00165 #define WDP2_REG WDTCR
00166 #define WDE_REG WDTCR
00167 #define WDCE_REG WDTCR
00168
00169
00170 #define ICR1H0_REG ICR1H
00171 #define ICR1H1_REG ICR1H
00172 #define ICR1H2_REG ICR1H
00173 #define ICR1H3_REG ICR1H
00174 #define ICR1H4_REG ICR1H
00175 #define ICR1H5_REG ICR1H
00176 #define ICR1H6_REG ICR1H
00177 #define ICR1H7_REG ICR1H
00178
00179
00180 #define TXB81_REG UCSR1B
00181 #define RXB81_REG UCSR1B
00182 #define UCSZ12_REG UCSR1B
00183 #define TXEN1_REG UCSR1B
00184 #define RXEN1_REG UCSR1B
00185 #define UDRIE1_REG UCSR1B
00186 #define TXCIE1_REG UCSR1B
00187 #define RXCIE1_REG UCSR1B
00188
00189
00190 #define UCPOL1_REG UCSR1C
00191 #define UCSZ10_REG UCSR1C
00192 #define UCSZ11_REG UCSR1C
00193 #define USBS1_REG UCSR1C
00194 #define UPM10_REG UCSR1C
00195 #define UPM11_REG UCSR1C
00196 #define UMSEL1_REG UCSR1C
00197 #define URSEL1_REG UCSR1C
00198
00199
00200 #define MPCM1_REG UCSR1A
00201 #define U2X1_REG UCSR1A
00202 #define UPE1_REG UCSR1A
00203 #define DOR1_REG UCSR1A
00204 #define FE1_REG UCSR1A
00205 #define UDRE1_REG UCSR1A
00206 #define TXC1_REG UCSR1A
00207 #define RXC1_REG UCSR1A
00208
00209
00210 #define CS00_REG TCCR0
00211 #define CS01_REG TCCR0
00212 #define CS02_REG TCCR0
00213 #define WGM01_REG TCCR0
00214 #define COM00_REG TCCR0
00215 #define COM01_REG TCCR0
00216 #define WGM00_REG TCCR0
00217 #define FOC0_REG TCCR0
00218
00219
00220 #define C_REG SREG
00221 #define Z_REG SREG
00222 #define N_REG SREG
00223 #define V_REG SREG
00224 #define S_REG SREG
00225 #define H_REG SREG
00226 #define T_REG SREG
00227 #define I_REG SREG
00228
00229
00230 #define DDB0_REG DDRB
00231 #define DDB1_REG DDRB
00232 #define DDB2_REG DDRB
00233 #define DDB3_REG DDRB
00234 #define DDB4_REG DDRB
00235 #define DDB5_REG DDRB
00236 #define DDB6_REG DDRB
00237 #define DDB7_REG DDRB
00238
00239
00240 #define IVCE_REG GICR
00241 #define IVSEL_REG GICR
00242 #define PCIE0_REG GICR
00243 #define PCIE1_REG GICR
00244 #define INT2_REG GICR
00245 #define INT0_REG GICR
00246 #define INT1_REG GICR
00247
00248
00249 #define SPI2X_REG SPSR
00250 #define WCOL_REG SPSR
00251 #define SPIF_REG SPSR
00252
00253
00254 #define DDC0_REG DDRC
00255 #define DDC1_REG DDRC
00256 #define DDC2_REG DDRC
00257 #define DDC3_REG DDRC
00258 #define DDC4_REG DDRC
00259 #define DDC5_REG DDRC
00260 #define DDC6_REG DDRC
00261 #define DDC7_REG DDRC
00262
00263
00264 #define EEDR0_REG EEDR
00265 #define EEDR1_REG EEDR
00266 #define EEDR2_REG EEDR
00267 #define EEDR3_REG EEDR
00268 #define EEDR4_REG EEDR
00269 #define EEDR5_REG EEDR
00270 #define EEDR6_REG EEDR
00271 #define EEDR7_REG EEDR
00272
00273
00274 #define TOIE3_REG ETIMSK
00275 #define OCIE3B_REG ETIMSK
00276 #define OCIE3A_REG ETIMSK
00277 #define TICIE3_REG ETIMSK
00278
00279
00280 #define OCR3AL0_REG OCR3AL
00281 #define OCR3AL1_REG OCR3AL
00282 #define OCR3AL2_REG OCR3AL
00283 #define OCR3AL3_REG OCR3AL
00284 #define OCR3AL4_REG OCR3AL
00285 #define OCR3AL5_REG OCR3AL
00286 #define OCR3AL6_REG OCR3AL
00287 #define OCR3AL7_REG OCR3AL
00288
00289
00290 #define DDA0_REG DDRA
00291 #define DDA1_REG DDRA
00292 #define DDA2_REG DDRA
00293 #define DDA3_REG DDRA
00294 #define DDA4_REG DDRA
00295 #define DDA5_REG DDRA
00296 #define DDA6_REG DDRA
00297 #define DDA7_REG DDRA
00298
00299
00300
00301
00302
00303
00304
00305
00306 #define OCR3AH0_REG OCR3AH
00307 #define OCR3AH1_REG OCR3AH
00308 #define OCR3AH2_REG OCR3AH
00309 #define OCR3AH3_REG OCR3AH
00310 #define OCR3AH4_REG OCR3AH
00311 #define OCR3AH5_REG OCR3AH
00312 #define OCR3AH6_REG OCR3AH
00313 #define OCR3AH7_REG OCR3AH
00314
00315
00316 #define CS10_REG TCCR1B
00317 #define CS11_REG TCCR1B
00318 #define CS12_REG TCCR1B
00319 #define WGM12_REG TCCR1B
00320 #define WGM13_REG TCCR1B
00321 #define ICES1_REG TCCR1B
00322 #define ICNC1_REG TCCR1B
00323
00324
00325 #define PCIF0_REG GIFR
00326 #define PCIF1_REG GIFR
00327 #define INTF2_REG GIFR
00328 #define INTF0_REG GIFR
00329 #define INTF1_REG GIFR
00330
00331
00332 #define TICIE1_REG TIMSK
00333 #define OCIE1B_REG TIMSK
00334 #define OCIE1A_REG TIMSK
00335 #define TOIE1_REG TIMSK
00336 #define TOIE2_REG TIMSK
00337 #define OCIE2_REG TIMSK
00338 #define OCIE0_REG TIMSK
00339 #define TOIE0_REG TIMSK
00340
00341
00342
00343
00344
00345
00346
00347
00348
00349 #define CS30_REG TCCR3B
00350 #define CS31_REG TCCR3B
00351 #define CS32_REG TCCR3B
00352 #define WGM32_REG TCCR3B
00353 #define WGM33_REG TCCR3B
00354 #define ICES3_REG TCCR3B
00355 #define ICNC3_REG TCCR3B
00356
00357
00358 #define WGM30_REG TCCR3A
00359 #define WGM31_REG TCCR3A
00360 #define FOC3B_REG TCCR3A
00361 #define FOC3A_REG TCCR3A
00362 #define COM3B0_REG TCCR3A
00363 #define COM3B1_REG TCCR3A
00364 #define COM3A0_REG TCCR3A
00365 #define COM3A1_REG TCCR3A
00366
00367
00368 #define WGM10_REG TCCR1A
00369 #define WGM11_REG TCCR1A
00370 #define FOC1B_REG TCCR1A
00371 #define FOC1A_REG TCCR1A
00372 #define COM1B0_REG TCCR1A
00373 #define COM1B1_REG TCCR1A
00374 #define COM1A0_REG TCCR1A
00375 #define COM1A1_REG TCCR1A
00376
00377
00378 #define ICR1L0_REG ICR1L
00379 #define ICR1L1_REG ICR1L
00380 #define ICR1L2_REG ICR1L
00381 #define ICR1L3_REG ICR1L
00382 #define ICR1L4_REG ICR1L
00383 #define ICR1L5_REG ICR1L
00384 #define ICR1L6_REG ICR1L
00385 #define ICR1L7_REG ICR1L
00386
00387
00388 #define PSR310_REG SFIOR
00389 #define PSR2_REG SFIOR
00390 #define PUD_REG SFIOR
00391 #define XMM0_REG SFIOR
00392 #define XMM1_REG SFIOR
00393 #define XMM2_REG SFIOR
00394 #define XMBK_REG SFIOR
00395 #define TSM_REG SFIOR
00396
00397
00398 #define UDR0_0_REG UDR0
00399 #define UDR0_1_REG UDR0
00400 #define UDR0_2_REG UDR0
00401 #define UDR0_3_REG UDR0
00402 #define UDR0_4_REG UDR0
00403 #define UDR0_5_REG UDR0
00404 #define UDR0_6_REG UDR0
00405 #define UDR0_7_REG UDR0
00406
00407
00408 #define SP8_REG SPH
00409 #define SP9_REG SPH
00410 #define SP10_REG SPH
00411 #define SP11_REG SPH
00412 #define SP12_REG SPH
00413 #define SP13_REG SPH
00414 #define SP14_REG SPH
00415 #define SP15_REG SPH
00416
00417
00418 #define OCR1BL0_REG OCR1BL
00419 #define OCR1BL1_REG OCR1BL
00420 #define OCR1BL2_REG OCR1BL
00421 #define OCR1BL3_REG OCR1BL
00422 #define OCR1BL4_REG OCR1BL
00423 #define OCR1BL5_REG OCR1BL
00424 #define OCR1BL6_REG OCR1BL
00425 #define OCR1BL7_REG OCR1BL
00426
00427
00428 #define TCNT3H0_REG TCNT3H
00429 #define TCNT3H1_REG TCNT3H
00430 #define TCNT3H2_REG TCNT3H
00431 #define TCNT3H3_REG TCNT3H
00432 #define TCNT3H4_REG TCNT3H
00433 #define TCNT3H5_REG TCNT3H
00434 #define TCNT3H6_REG TCNT3H
00435 #define TCNT3H7_REG TCNT3H
00436
00437
00438 #define ISC2_REG EMCUCR
00439 #define SRW11_REG EMCUCR
00440 #define SRW00_REG EMCUCR
00441 #define SRW01_REG EMCUCR
00442 #define SRL0_REG EMCUCR
00443 #define SRL1_REG EMCUCR
00444 #define SRL2_REG EMCUCR
00445 #define SM0_REG EMCUCR
00446
00447
00448 #define SP0_REG SPL
00449 #define SP1_REG SPL
00450 #define SP2_REG SPL
00451 #define SP3_REG SPL
00452 #define SP4_REG SPL
00453 #define SP5_REG SPL
00454 #define SP6_REG SPL
00455 #define SP7_REG SPL
00456
00457
00458 #define OCR1BH0_REG OCR1BH
00459 #define OCR1BH1_REG OCR1BH
00460 #define OCR1BH2_REG OCR1BH
00461 #define OCR1BH3_REG OCR1BH
00462 #define OCR1BH4_REG OCR1BH
00463 #define OCR1BH5_REG OCR1BH
00464 #define OCR1BH6_REG OCR1BH
00465 #define OCR1BH7_REG OCR1BH
00466
00467
00468 #define TCNT3L0_REG TCNT3L
00469 #define TCNT3L1_REG TCNT3L
00470 #define TCNT3L2_REG TCNT3L
00471 #define TCNT3L3_REG TCNT3L
00472 #define TCNT3L4_REG TCNT3L
00473 #define TCNT3L5_REG TCNT3L
00474 #define TCNT3L6_REG TCNT3L
00475 #define TCNT3L7_REG TCNT3L
00476
00477
00478 #define PIND0_REG PIND
00479 #define PIND1_REG PIND
00480 #define PIND2_REG PIND
00481 #define PIND3_REG PIND
00482 #define PIND4_REG PIND
00483 #define PIND5_REG PIND
00484 #define PIND6_REG PIND
00485 #define PIND7_REG PIND
00486
00487
00488 #define DDD0_REG DDRD
00489 #define DDD1_REG DDRD
00490 #define DDD2_REG DDRD
00491 #define DDD3_REG DDRD
00492 #define DDD4_REG DDRD
00493 #define DDD5_REG DDRD
00494 #define DDD6_REG DDRD
00495 #define DDD7_REG DDRD
00496
00497
00498 #define SPMEN_REG SPMCR
00499 #define PGERS_REG SPMCR
00500 #define PGWRT_REG SPMCR
00501 #define BLBSET_REG SPMCR
00502 #define RWWSRE_REG SPMCR
00503 #define RWWSB_REG SPMCR
00504 #define SPMIE_REG SPMCR
00505
00506
00507 #define ICR3H0_REG ICR3H
00508 #define ICR3H1_REG ICR3H
00509 #define ICR3H2_REG ICR3H
00510 #define ICR3H3_REG ICR3H
00511 #define ICR3H4_REG ICR3H
00512 #define ICR3H5_REG ICR3H
00513 #define ICR3H6_REG ICR3H
00514 #define ICR3H7_REG ICR3H
00515
00516
00517 #define DDE0_REG DDRE
00518 #define DDE1_REG DDRE
00519 #define DDE2_REG DDRE
00520
00521
00522 #define PORTD0_REG PORTD
00523 #define PORTD1_REG PORTD
00524 #define PORTD2_REG PORTD
00525 #define PORTD3_REG PORTD
00526 #define PORTD4_REG PORTD
00527 #define PORTD5_REG PORTD
00528 #define PORTD6_REG PORTD
00529 #define PORTD7_REG PORTD
00530
00531
00532 #define ICR3L0_REG ICR3L
00533 #define ICR3L1_REG ICR3L
00534 #define ICR3L2_REG ICR3L
00535 #define ICR3L3_REG ICR3L
00536 #define ICR3L4_REG ICR3L
00537 #define ICR3L5_REG ICR3L
00538 #define ICR3L6_REG ICR3L
00539 #define ICR3L7_REG ICR3L
00540
00541
00542 #define ACIS0_REG ACSR
00543 #define ACIS1_REG ACSR
00544 #define ACIC_REG ACSR
00545 #define ACIE_REG ACSR
00546 #define ACI_REG ACSR
00547 #define ACO_REG ACSR
00548 #define ACBG_REG ACSR
00549 #define ACD_REG ACSR
00550
00551
00552 #define EERE_REG EECR
00553 #define EEWE_REG EECR
00554 #define EEMWE_REG EECR
00555 #define EERIE_REG EECR
00556
00557
00558 #define PORTE0_REG PORTE
00559 #define PORTE1_REG PORTE
00560 #define PORTE2_REG PORTE
00561
00562
00563 #define CAL0_REG OSCCAL
00564 #define CAL1_REG OSCCAL
00565 #define CAL2_REG OSCCAL
00566 #define CAL3_REG OSCCAL
00567 #define CAL4_REG OSCCAL
00568 #define CAL5_REG OSCCAL
00569 #define CAL6_REG OSCCAL
00570
00571
00572 #define TCNT1L0_REG TCNT1L
00573 #define TCNT1L1_REG TCNT1L
00574 #define TCNT1L2_REG TCNT1L
00575 #define TCNT1L3_REG TCNT1L
00576 #define TCNT1L4_REG TCNT1L
00577 #define TCNT1L5_REG TCNT1L
00578 #define TCNT1L6_REG TCNT1L
00579 #define TCNT1L7_REG TCNT1L
00580
00581
00582 #define PORTB0_REG PORTB
00583 #define PORTB1_REG PORTB
00584 #define PORTB2_REG PORTB
00585 #define PORTB3_REG PORTB
00586 #define PORTB4_REG PORTB
00587 #define PORTB5_REG PORTB
00588 #define PORTB6_REG PORTB
00589 #define PORTB7_REG PORTB
00590
00591
00592 #define UCPOL0_REG UCSR0C
00593 #define UCSZ00_REG UCSR0C
00594 #define UCSZ01_REG UCSR0C
00595 #define USBS0_REG UCSR0C
00596 #define UPM00_REG UCSR0C
00597 #define UPM01_REG UCSR0C
00598 #define UMSEL0_REG UCSR0C
00599
00600
00601
00602 #define TXB80_REG UCSR0B
00603 #define RXB80_REG UCSR0B
00604 #define UCSZ02_REG UCSR0B
00605 #define TXEN0_REG UCSR0B
00606 #define RXEN0_REG UCSR0B
00607 #define UDRIE0_REG UCSR0B
00608 #define TXCIE0_REG UCSR0B
00609 #define RXCIE0_REG UCSR0B
00610
00611
00612 #define TCNT1H0_REG TCNT1H
00613 #define TCNT1H1_REG TCNT1H
00614 #define TCNT1H2_REG TCNT1H
00615 #define TCNT1H3_REG TCNT1H
00616 #define TCNT1H4_REG TCNT1H
00617 #define TCNT1H5_REG TCNT1H
00618 #define TCNT1H6_REG TCNT1H
00619 #define TCNT1H7_REG TCNT1H
00620
00621
00622 #define PORTC0_REG PORTC
00623 #define PORTC1_REG PORTC
00624 #define PORTC2_REG PORTC
00625 #define PORTC3_REG PORTC
00626 #define PORTC4_REG PORTC
00627 #define PORTC5_REG PORTC
00628 #define PORTC6_REG PORTC
00629 #define PORTC7_REG PORTC
00630
00631
00632 #define PORTA0_REG PORTA
00633 #define PORTA1_REG PORTA
00634 #define PORTA2_REG PORTA
00635 #define PORTA3_REG PORTA
00636 #define PORTA4_REG PORTA
00637 #define PORTA5_REG PORTA
00638 #define PORTA6_REG PORTA
00639 #define PORTA7_REG PORTA
00640
00641
00642 #define TCNT2_0_REG TCNT2
00643 #define TCNT2_1_REG TCNT2
00644 #define TCNT2_2_REG TCNT2
00645 #define TCNT2_3_REG TCNT2
00646 #define TCNT2_4_REG TCNT2
00647 #define TCNT2_5_REG TCNT2
00648 #define TCNT2_6_REG TCNT2
00649 #define TCNT2_7_REG TCNT2
00650
00651
00652 #define TCNT0_0_REG TCNT0
00653 #define TCNT0_1_REG TCNT0
00654 #define TCNT0_2_REG TCNT0
00655 #define TCNT0_3_REG TCNT0
00656 #define TCNT0_4_REG TCNT0
00657 #define TCNT0_5_REG TCNT0
00658 #define TCNT0_6_REG TCNT0
00659 #define TCNT0_7_REG TCNT0
00660
00661
00662 #define OCR3BL0_REG OCR3BL
00663 #define OCR3BL1_REG OCR3BL
00664 #define OCR3BL2_REG OCR3BL
00665 #define OCR3BL3_REG OCR3BL
00666 #define OCR3BL4_REG OCR3BL
00667 #define OCR3BL5_REG OCR3BL
00668 #define OCR3BL6_REG OCR3BL
00669 #define OCR3BL7_REG OCR3BL
00670
00671
00672 #define PORF_REG MCUCSR
00673 #define EXTRF_REG MCUCSR
00674 #define BORF_REG MCUCSR
00675 #define WDRF_REG MCUCSR
00676 #define JTRF_REG MCUCSR
00677 #define SM2_REG MCUCSR
00678 #define JDT_REG MCUCSR
00679 #define JTD_REG MCUCSR
00680
00681
00682 #define OCR3BH0_REG OCR3BH
00683 #define OCR3BH1_REG OCR3BH
00684 #define OCR3BH2_REG OCR3BH
00685 #define OCR3BH3_REG OCR3BH
00686 #define OCR3BH4_REG OCR3BH
00687 #define OCR3BH5_REG OCR3BH
00688 #define OCR3BH6_REG OCR3BH
00689 #define OCR3BH7_REG OCR3BH
00690
00691
00692 #define MPCM0_REG UCSR0A
00693 #define U2X0_REG UCSR0A
00694 #define UPE0_REG UCSR0A
00695 #define DOR0_REG UCSR0A
00696 #define FE0_REG UCSR0A
00697 #define UDRE0_REG UCSR0A
00698 #define TXC0_REG UCSR0A
00699 #define RXC0_REG UCSR0A
00700
00701
00702 #define EEAR0_REG EEARL
00703 #define EEAR1_REG EEARL
00704 #define EEAR2_REG EEARL
00705 #define EEAR3_REG EEARL
00706 #define EEAR4_REG EEARL
00707 #define EEAR5_REG EEARL
00708 #define EEAR6_REG EEARL
00709 #define EEAR7_REG EEARL
00710
00711
00712 #define UBRR1L0_REG UBRR1L
00713 #define UBRR1L1_REG UBRR1L
00714 #define UBRR1L2_REG UBRR1L
00715 #define UBRR1L3_REG UBRR1L
00716 #define UBRR1L4_REG UBRR1L
00717 #define UBRR1L5_REG UBRR1L
00718 #define UBRR1L6_REG UBRR1L
00719 #define UBRR1L7_REG UBRR1L
00720
00721
00722 #define CS20_REG TCCR2
00723 #define CS21_REG TCCR2
00724 #define CS22_REG TCCR2
00725 #define WGM21_REG TCCR2
00726 #define COM20_REG TCCR2
00727 #define COM21_REG TCCR2
00728 #define WGM20_REG TCCR2
00729 #define FOC2_REG TCCR2
00730
00731
00732 #define UDR1_0_REG UDR1
00733 #define UDR1_1_REG UDR1
00734 #define UDR1_2_REG UDR1
00735 #define UDR1_3_REG UDR1
00736 #define UDR1_4_REG UDR1
00737 #define UDR1_5_REG UDR1
00738 #define UDR1_6_REG UDR1
00739 #define UDR1_7_REG UDR1
00740
00741
00742 #define ICF1_REG TIFR
00743 #define OCF1B_REG TIFR
00744 #define OCF1A_REG TIFR
00745 #define TOV1_REG TIFR
00746 #define TOV2_REG TIFR
00747 #define OCF2_REG TIFR
00748 #define OCF0_REG TIFR
00749 #define TOV0_REG TIFR
00750
00751
00752 #define UBRR0_REG UBRR0L
00753 #define UBRR1_REG UBRR0L
00754 #define UBRR2_REG UBRR0L
00755 #define UBRR3_REG UBRR0L
00756 #define UBRR4_REG UBRR0L
00757 #define UBRR5_REG UBRR0L
00758 #define UBRR6_REG UBRR0L
00759 #define UBRR7_REG UBRR0L
00760
00761
00762 #define EEAR8_REG EEARH
00763
00764
00765 #define OCDR0_REG OCDR
00766 #define OCDR1_REG OCDR
00767 #define OCDR2_REG OCDR
00768 #define OCDR3_REG OCDR
00769 #define OCDR4_REG OCDR
00770 #define OCDR5_REG OCDR
00771 #define OCDR6_REG OCDR
00772 #define OCDR7_REG OCDR
00773
00774
00775 #define PCINT0_REG PCMSK0
00776 #define PCINT1_REG PCMSK0
00777 #define PCINT2_REG PCMSK0
00778 #define PCINT3_REG PCMSK0
00779 #define PCINT4_REG PCMSK0
00780 #define PCINT5_REG PCMSK0
00781 #define PCINT6_REG PCMSK0
00782 #define PCINT7_REG PCMSK0
00783
00784
00785 #define PCINT8_REG PCMSK1
00786 #define PCINT9_REG PCMSK1
00787 #define PCINT10_REG PCMSK1
00788 #define PCINT11_REG PCMSK1
00789 #define PCINT12_REG PCMSK1
00790 #define PCINT13_REG PCMSK1
00791 #define PCINT14_REG PCMSK1
00792 #define PCINT15_REG PCMSK1
00793
00794
00795 #define PINC0_REG PINC
00796 #define PINC1_REG PINC
00797 #define PINC2_REG PINC
00798 #define PINC3_REG PINC
00799 #define PINC4_REG PINC
00800 #define PINC5_REG PINC
00801 #define PINC6_REG PINC
00802 #define PINC7_REG PINC
00803
00804
00805 #define PINB0_REG PINB
00806 #define PINB1_REG PINB
00807 #define PINB2_REG PINB
00808 #define PINB3_REG PINB
00809 #define PINB4_REG PINB
00810 #define PINB5_REG PINB
00811 #define PINB6_REG PINB
00812 #define PINB7_REG PINB
00813
00814
00815 #define PINA0_REG PINA
00816 #define PINA1_REG PINA
00817 #define PINA2_REG PINA
00818 #define PINA3_REG PINA
00819 #define PINA4_REG PINA
00820 #define PINA5_REG PINA
00821 #define PINA6_REG PINA
00822 #define PINA7_REG PINA
00823
00824
00825 #define PINE0_REG PINE
00826 #define PINE1_REG PINE
00827 #define PINE2_REG PINE
00828 #define PINE3_REG PINE
00829
00830
00831 #define ISC00_REG MCUCR
00832 #define ISC01_REG MCUCR
00833 #define ISC10_REG MCUCR
00834 #define ISC11_REG MCUCR
00835 #define SM1_REG MCUCR
00836 #define SE_REG MCUCR
00837 #define SRW10_REG MCUCR
00838 #define SRE_REG MCUCR
00839
00840
00841 #define OCR1AH0_REG OCR1AH
00842 #define OCR1AH1_REG OCR1AH
00843 #define OCR1AH2_REG OCR1AH
00844 #define OCR1AH3_REG OCR1AH
00845 #define OCR1AH4_REG OCR1AH
00846 #define OCR1AH5_REG OCR1AH
00847 #define OCR1AH6_REG OCR1AH
00848 #define OCR1AH7_REG OCR1AH
00849
00850
00851 #define OCR1AL0_REG OCR1AL
00852 #define OCR1AL1_REG OCR1AL
00853 #define OCR1AL2_REG OCR1AL
00854 #define OCR1AL3_REG OCR1AL
00855 #define OCR1AL4_REG OCR1AL
00856 #define OCR1AL5_REG OCR1AL
00857 #define OCR1AL6_REG OCR1AL
00858 #define OCR1AL7_REG OCR1AL
00859
00860
00861 #define SPR0_REG SPCR
00862 #define SPR1_REG SPCR
00863 #define CPHA_REG SPCR
00864 #define CPOL_REG SPCR
00865 #define MSTR_REG SPCR
00866 #define DORD_REG SPCR
00867 #define SPE_REG SPCR
00868 #define SPIE_REG SPCR
00869
00870
00871 #define OCR0_0_REG OCR0
00872 #define OCR0_1_REG OCR0
00873 #define OCR0_2_REG OCR0
00874 #define OCR0_3_REG OCR0
00875 #define OCR0_4_REG OCR0
00876 #define OCR0_5_REG OCR0
00877 #define OCR0_6_REG OCR0
00878 #define OCR0_7_REG OCR0
00879
00880
00881 #define TOV3_REG ETIFR
00882 #define OCF3B_REG ETIFR
00883 #define OCF3A_REG ETIFR
00884 #define ICF3_REG ETIFR
00885
00886
00887 #define OCR2_0_REG OCR2
00888 #define OCR2_1_REG OCR2
00889 #define OCR2_2_REG OCR2
00890 #define OCR2_3_REG OCR2
00891 #define OCR2_4_REG OCR2
00892 #define OCR2_5_REG OCR2
00893 #define OCR2_6_REG OCR2
00894 #define OCR2_7_REG OCR2
00895
00896
00897 #define TCR2UB_REG ASSR
00898 #define OCR2UB_REG ASSR
00899 #define TCN2UB_REG ASSR
00900 #define AS2_REG ASSR
00901
00902
00903 #define PCINT0_PORT PORTA
00904 #define PCINT0_BIT 0
00905 #define AD0_PORT PORTA
00906 #define AD0_BIT 0
00907
00908 #define PCINT1_PORT PORTA
00909 #define PCINT1_BIT 1
00910 #define AD1_PORT PORTA
00911 #define AD1_BIT 1
00912
00913 #define PCINT2_PORT PORTA
00914 #define PCINT2_BIT 2
00915 #define AD2_PORT PORTA
00916 #define AD2_BIT 2
00917
00918 #define PCINT3_PORT PORTA
00919 #define PCINT3_BIT 3
00920 #define AD3_PORT PORTA
00921 #define AD3_BIT 3
00922
00923 #define PCINT4_PORT PORTA
00924 #define PCINT4_BIT 4
00925 #define AD4_PORT PORTA
00926 #define AD4_BIT 4
00927
00928 #define PCINT5_PORT PORTA
00929 #define PCINT5_BIT 5
00930 #define AD5_PORT PORTA
00931 #define AD5_BIT 5
00932
00933 #define PCINT6_PORT PORTA
00934 #define PCINT6_BIT 6
00935 #define AD6_PORT PORTA
00936 #define AD6_BIT 6
00937
00938 #define PCINT7_PORT PORTA
00939 #define PCINT7_BIT 7
00940 #define AD7_PORT PORTA
00941 #define AD7_BIT 7
00942
00943 #define OC0_PORT PORTB
00944 #define OC0_BIT 0
00945 #define T0_PORT PORTB
00946 #define T0_BIT 0
00947
00948 #define OC2_PORT PORTB
00949 #define OC2_BIT 1
00950 #define T1_PORT PORTB
00951 #define T1_BIT 1
00952
00953 #define RXD1_PORT PORTB
00954 #define RXD1_BIT 2
00955 #define AIN0_PORT PORTB
00956 #define AIN0_BIT 2
00957
00958 #define TXD1_PORT PORTB
00959 #define TXD1_BIT 3
00960 #define AIN1_PORT PORTB
00961 #define AIN1_BIT 3
00962
00963 #define OC3B_PORT PORTB
00964 #define OC3B_BIT 4
00965 #define SS_PORT PORTB
00966 #define SS_BIT 4
00967
00968 #define MOSI_PORT PORTB
00969 #define MOSI_BIT 5
00970
00971 #define MISO_PORT PORTB
00972 #define MISO_BIT 6
00973
00974
00975 #define PCINT8_PORT PORTC
00976 #define PCINT8_BIT 0
00977 #define A8_PORT PORTC
00978 #define A8_BIT 0
00979
00980 #define PCINT9_PORT PORTC
00981 #define PCINT9_BIT 1
00982 #define A9_PORT PORTC
00983 #define A9_BIT 1
00984
00985 #define PCINT10_PORT PORTC
00986 #define PCINT10_BIT 2
00987 #define A10_PORT PORTC
00988 #define A10_BIT 2
00989
00990 #define PCINT11_PORT PORTC
00991 #define PCINT11_BIT 3
00992 #define A11_PORT PORTC
00993 #define A11_BIT 3
00994
00995 #define PCINT12_PORT PORTC
00996 #define PCINT12_BIT 4
00997 #define A12_PORT PORTC
00998 #define A12_BIT 4
00999 #define TCK_PORT PORTC
01000 #define TCK_BIT 4
01001
01002 #define PCINT13_PORT PORTC
01003 #define PCINT13_BIT 5
01004 #define A13_PORT PORTC
01005 #define A13_BIT 5
01006 #define TMS_PORT PORTC
01007 #define TMS_BIT 5
01008
01009 #define PCINT14_PORT PORTC
01010 #define PCINT14_BIT 6
01011 #define A14_PORT PORTC
01012 #define A14_BIT 6
01013 #define TDO_PORT PORTC
01014 #define TDO_BIT 6
01015
01016 #define PCINT15_PORT PORTC
01017 #define PCINT15_BIT 7
01018 #define A15_PORT PORTC
01019 #define A15_BIT 7
01020 #define TDI_PORT PORTC
01021 #define TDI_BIT 7
01022
01023 #define TXD0_PORT PORTD
01024 #define TXD0_BIT 1
01025
01026 #define INT0_PORT PORTD
01027 #define INT0_BIT 2
01028 #define XCK1_PORT PORTD
01029 #define XCK1_BIT 2
01030
01031 #define INT1_PORT PORTD
01032 #define INT1_BIT 3
01033 #define XCK1_PORT PORTD
01034 #define XCK1_BIT 3
01035
01036 #define TOSC1_PORT PORTD
01037 #define TOSC1_BIT 4
01038 #define XCK0_PORT PORTD
01039 #define XCK0_BIT 4
01040 #define OC3A_PORT PORTD
01041 #define OC3A_BIT 4
01042
01043 #define OC1A_PORT PORTD
01044 #define OC1A_BIT 5
01045 #define TOSC2_PORT PORTD
01046 #define TOSC2_BIT 5
01047
01048 #define WR_PORT PORTD
01049 #define WR_BIT 6
01050
01051 #define RD_PORT PORTD
01052 #define RD_BIT 7
01053
01054 #define ICP1_PORT PORTE
01055 #define ICP1_BIT 0
01056 #define INT2_PORT PORTE
01057 #define INT2_BIT 0
01058
01059 #define ALE_PORT PORTE
01060 #define ALE_BIT 1
01061
01062 #define OC1B_PORT PORTE
01063 #define OC1B_BIT 2
01064
01065