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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define SPDR0_REG SPDR
00119 #define SPDR1_REG SPDR
00120 #define SPDR2_REG SPDR
00121 #define SPDR3_REG SPDR
00122 #define SPDR4_REG SPDR
00123 #define SPDR5_REG SPDR
00124 #define SPDR6_REG SPDR
00125 #define SPDR7_REG SPDR
00126
00127
00128 #define CLKPS0_REG CLKPR
00129 #define CLKPS1_REG CLKPR
00130 #define CLKPS2_REG CLKPR
00131 #define CLKPS3_REG CLKPR
00132 #define CLKPCE_REG CLKPR
00133
00134
00135 #define WDP0_REG WDTCR
00136 #define WDP1_REG WDTCR
00137 #define WDP2_REG WDTCR
00138 #define WDE_REG WDTCR
00139 #define WDTOE_REG WDTCR
00140
00141
00142 #define ICR1H0_REG ICR1H
00143 #define ICR1H1_REG ICR1H
00144 #define ICR1H2_REG ICR1H
00145 #define ICR1H3_REG ICR1H
00146 #define ICR1H4_REG ICR1H
00147 #define ICR1H5_REG ICR1H
00148 #define ICR1H6_REG ICR1H
00149 #define ICR1H7_REG ICR1H
00150
00151
00152 #define TXB81_REG UCSR1B
00153 #define RXB81_REG UCSR1B
00154 #define UCSZ12_REG UCSR1B
00155 #define TXEN1_REG UCSR1B
00156 #define RXEN1_REG UCSR1B
00157 #define UDRIE1_REG UCSR1B
00158 #define TXCIE1_REG UCSR1B
00159 #define RXCIE1_REG UCSR1B
00160
00161
00162 #define UCPOL1_REG UCSR1C
00163 #define UCSZ10_REG UCSR1C
00164 #define UCSZ11_REG UCSR1C
00165 #define USBS1_REG UCSR1C
00166 #define UPM10_REG UCSR1C
00167 #define UPM11_REG UCSR1C
00168 #define UMSEL1_REG UCSR1C
00169 #define URSEL1_REG UCSR1C
00170
00171
00172 #define MPCM1_REG UCSR1A
00173 #define U2X1_REG UCSR1A
00174 #define UPE1_REG UCSR1A
00175 #define DOR1_REG UCSR1A
00176 #define FE1_REG UCSR1A
00177 #define UDRE1_REG UCSR1A
00178 #define TXC1_REG UCSR1A
00179 #define RXC1_REG UCSR1A
00180
00181
00182 #define CS00_REG TCCR0
00183 #define CS01_REG TCCR0
00184 #define CS02_REG TCCR0
00185 #define WGM01_REG TCCR0
00186 #define COM00_REG TCCR0
00187 #define COM01_REG TCCR0
00188 #define WGM00_REG TCCR0
00189 #define FOC0_REG TCCR0
00190
00191
00192 #define C_REG SREG
00193 #define Z_REG SREG
00194 #define N_REG SREG
00195 #define V_REG SREG
00196 #define S_REG SREG
00197 #define H_REG SREG
00198 #define T_REG SREG
00199 #define I_REG SREG
00200
00201
00202 #define DDB0_REG DDRB
00203 #define DDB1_REG DDRB
00204 #define DDB2_REG DDRB
00205 #define DDB3_REG DDRB
00206 #define DDB4_REG DDRB
00207 #define DDB5_REG DDRB
00208 #define DDB6_REG DDRB
00209 #define DDB7_REG DDRB
00210
00211
00212 #define IVCE_REG GICR
00213 #define IVSEL_REG GICR
00214 #define PCIE0_REG GICR
00215 #define PCIE1_REG GICR
00216 #define INT2_REG GICR
00217 #define INT0_REG GICR
00218 #define INT1_REG GICR
00219
00220
00221 #define SPI2X_REG SPSR
00222 #define WCOL_REG SPSR
00223 #define SPIF_REG SPSR
00224
00225
00226 #define EEDR0_REG EEDR
00227 #define EEDR1_REG EEDR
00228 #define EEDR2_REG EEDR
00229 #define EEDR3_REG EEDR
00230 #define EEDR4_REG EEDR
00231 #define EEDR5_REG EEDR
00232 #define EEDR6_REG EEDR
00233 #define EEDR7_REG EEDR
00234
00235
00236 #define DDC0_REG DDRC
00237 #define DDC1_REG DDRC
00238 #define DDC2_REG DDRC
00239 #define DDC3_REG DDRC
00240 #define DDC4_REG DDRC
00241 #define DDC5_REG DDRC
00242 #define DDC6_REG DDRC
00243 #define DDC7_REG DDRC
00244
00245
00246 #define DDA0_REG DDRA
00247 #define DDA1_REG DDRA
00248 #define DDA2_REG DDRA
00249 #define DDA3_REG DDRA
00250 #define DDA4_REG DDRA
00251 #define DDA5_REG DDRA
00252 #define DDA6_REG DDRA
00253 #define DDA7_REG DDRA
00254
00255
00256 #define WGM10_REG TCCR1A
00257 #define WGM11_REG TCCR1A
00258 #define FOC1B_REG TCCR1A
00259 #define FOC1A_REG TCCR1A
00260 #define COM1B0_REG TCCR1A
00261 #define COM1B1_REG TCCR1A
00262 #define COM1A0_REG TCCR1A
00263 #define COM1A1_REG TCCR1A
00264
00265
00266 #define DDD0_REG DDRD
00267 #define DDD1_REG DDRD
00268 #define DDD2_REG DDRD
00269 #define DDD3_REG DDRD
00270 #define DDD4_REG DDRD
00271 #define DDD5_REG DDRD
00272 #define DDD6_REG DDRD
00273 #define DDD7_REG DDRD
00274
00275
00276 #define CS10_REG TCCR1B
00277 #define CS11_REG TCCR1B
00278 #define CS12_REG TCCR1B
00279 #define CTC1_REG TCCR1B
00280 #define ICES1_REG TCCR1B
00281 #define ICNC1_REG TCCR1B
00282
00283
00284 #define PCIF0_REG GIFR
00285 #define PCIF1_REG GIFR
00286 #define INTF2_REG GIFR
00287 #define INTF0_REG GIFR
00288 #define INTF1_REG GIFR
00289
00290
00291 #define OCIE0_REG TIMSK
00292 #define TOIE0_REG TIMSK
00293 #define TICIE1_REG TIMSK
00294 #define OCIE1B_REG TIMSK
00295 #define OCIE1A_REG TIMSK
00296 #define TOIE1_REG TIMSK
00297 #define TOIE2_REG TIMSK
00298 #define OCIE2_REG TIMSK
00299
00300
00301
00302
00303
00304
00305
00306
00307
00308
00309
00310
00311
00312
00313
00314 #define ICR1L0_REG ICR1L
00315 #define ICR1L1_REG ICR1L
00316 #define ICR1L2_REG ICR1L
00317 #define ICR1L3_REG ICR1L
00318 #define ICR1L4_REG ICR1L
00319 #define ICR1L5_REG ICR1L
00320 #define ICR1L6_REG ICR1L
00321 #define ICR1L7_REG ICR1L
00322
00323
00324 #define PSR10_REG SFIOR
00325 #define PSR310_REG SFIOR
00326 #define PSR2_REG SFIOR
00327 #define PUD_REG SFIOR
00328 #define XMM0_REG SFIOR
00329 #define XMM1_REG SFIOR
00330 #define XMM2_REG SFIOR
00331 #define XMBK_REG SFIOR
00332 #define TSM_REG SFIOR
00333
00334
00335 #define UDR0_0_REG UDR0
00336 #define UDR0_1_REG UDR0
00337 #define UDR0_2_REG UDR0
00338 #define UDR0_3_REG UDR0
00339 #define UDR0_4_REG UDR0
00340 #define UDR0_5_REG UDR0
00341 #define UDR0_6_REG UDR0
00342 #define UDR0_7_REG UDR0
00343
00344
00345 #define SP8_REG SPH
00346 #define SP9_REG SPH
00347 #define SP10_REG SPH
00348 #define SP11_REG SPH
00349 #define SP12_REG SPH
00350 #define SP13_REG SPH
00351 #define SP14_REG SPH
00352 #define SP15_REG SPH
00353
00354
00355 #define OCR1BL0_REG OCR1BL
00356 #define OCR1BL1_REG OCR1BL
00357 #define OCR1BL2_REG OCR1BL
00358 #define OCR1BL3_REG OCR1BL
00359 #define OCR1BL4_REG OCR1BL
00360 #define OCR1BL5_REG OCR1BL
00361 #define OCR1BL6_REG OCR1BL
00362 #define OCR1BL7_REG OCR1BL
00363
00364
00365 #define ISC2_REG EMCUCR
00366 #define SRW11_REG EMCUCR
00367 #define SRW00_REG EMCUCR
00368 #define SRW01_REG EMCUCR
00369 #define SRL0_REG EMCUCR
00370 #define SRL1_REG EMCUCR
00371 #define SRL2_REG EMCUCR
00372 #define SM0_REG EMCUCR
00373
00374
00375 #define SP0_REG SPL
00376 #define SP1_REG SPL
00377 #define SP2_REG SPL
00378 #define SP3_REG SPL
00379 #define SP4_REG SPL
00380 #define SP5_REG SPL
00381 #define SP6_REG SPL
00382 #define SP7_REG SPL
00383
00384
00385 #define OCR1BH0_REG OCR1BH
00386 #define OCR1BH1_REG OCR1BH
00387 #define OCR1BH2_REG OCR1BH
00388 #define OCR1BH3_REG OCR1BH
00389 #define OCR1BH4_REG OCR1BH
00390 #define OCR1BH5_REG OCR1BH
00391 #define OCR1BH6_REG OCR1BH
00392 #define OCR1BH7_REG OCR1BH
00393
00394
00395 #define PIND0_REG PIND
00396 #define PIND1_REG PIND
00397 #define PIND2_REG PIND
00398 #define PIND3_REG PIND
00399 #define PIND4_REG PIND
00400 #define PIND5_REG PIND
00401 #define PIND6_REG PIND
00402 #define PIND7_REG PIND
00403
00404
00405 #define SPMEN_REG SPMCR
00406 #define PGERS_REG SPMCR
00407 #define PGWRT_REG SPMCR
00408 #define BLBSET_REG SPMCR
00409 #define RWWSRE_REG SPMCR
00410 #define RWWSB_REG SPMCR
00411 #define SPMIE_REG SPMCR
00412
00413
00414 #define DDE0_REG DDRE
00415 #define DDE1_REG DDRE
00416 #define DDE2_REG DDRE
00417
00418
00419 #define PORTD0_REG PORTD
00420 #define PORTD1_REG PORTD
00421 #define PORTD2_REG PORTD
00422 #define PORTD3_REG PORTD
00423 #define PORTD4_REG PORTD
00424 #define PORTD5_REG PORTD
00425 #define PORTD6_REG PORTD
00426 #define PORTD7_REG PORTD
00427
00428
00429 #define ACIS0_REG ACSR
00430 #define ACIS1_REG ACSR
00431 #define ACIC_REG ACSR
00432 #define ACIE_REG ACSR
00433 #define ACI_REG ACSR
00434 #define ACO_REG ACSR
00435 #define ACBG_REG ACSR
00436 #define ACD_REG ACSR
00437
00438
00439 #define EERE_REG EECR
00440 #define EEWE_REG EECR
00441 #define EEMWE_REG EECR
00442 #define EERIE_REG EECR
00443
00444
00445 #define PORTE0_REG PORTE
00446 #define PORTE1_REG PORTE
00447 #define PORTE2_REG PORTE
00448
00449
00450 #define CAL0_REG OSCCAL
00451 #define CAL1_REG OSCCAL
00452 #define CAL2_REG OSCCAL
00453 #define CAL3_REG OSCCAL
00454 #define CAL4_REG OSCCAL
00455 #define CAL5_REG OSCCAL
00456 #define CAL6_REG OSCCAL
00457
00458
00459 #define TCNT1L0_REG TCNT1L
00460 #define TCNT1L1_REG TCNT1L
00461 #define TCNT1L2_REG TCNT1L
00462 #define TCNT1L3_REG TCNT1L
00463 #define TCNT1L4_REG TCNT1L
00464 #define TCNT1L5_REG TCNT1L
00465 #define TCNT1L6_REG TCNT1L
00466 #define TCNT1L7_REG TCNT1L
00467
00468
00469 #define PORTB0_REG PORTB
00470 #define PORTB1_REG PORTB
00471 #define PORTB2_REG PORTB
00472 #define PORTB3_REG PORTB
00473 #define PORTB4_REG PORTB
00474 #define PORTB5_REG PORTB
00475 #define PORTB6_REG PORTB
00476 #define PORTB7_REG PORTB
00477
00478
00479 #define UCPOL0_REG UCSR0C
00480 #define UCSZ00_REG UCSR0C
00481 #define UCSZ01_REG UCSR0C
00482 #define USBS0_REG UCSR0C
00483 #define UPM00_REG UCSR0C
00484 #define UPM01_REG UCSR0C
00485 #define UMSEL0_REG UCSR0C
00486
00487
00488
00489 #define TXB80_REG UCSR0B
00490 #define RXB80_REG UCSR0B
00491 #define UCSZ02_REG UCSR0B
00492 #define TXEN0_REG UCSR0B
00493 #define RXEN0_REG UCSR0B
00494 #define UDRIE0_REG UCSR0B
00495 #define TXCIE0_REG UCSR0B
00496 #define RXCIE0_REG UCSR0B
00497
00498
00499 #define TCNT1H0_REG TCNT1H
00500 #define TCNT1H1_REG TCNT1H
00501 #define TCNT1H2_REG TCNT1H
00502 #define TCNT1H3_REG TCNT1H
00503 #define TCNT1H4_REG TCNT1H
00504 #define TCNT1H5_REG TCNT1H
00505 #define TCNT1H6_REG TCNT1H
00506 #define TCNT1H7_REG TCNT1H
00507
00508
00509 #define PORTC0_REG PORTC
00510 #define PORTC1_REG PORTC
00511 #define PORTC2_REG PORTC
00512 #define PORTC3_REG PORTC
00513 #define PORTC4_REG PORTC
00514 #define PORTC5_REG PORTC
00515 #define PORTC6_REG PORTC
00516 #define PORTC7_REG PORTC
00517
00518
00519 #define PORTA0_REG PORTA
00520 #define PORTA1_REG PORTA
00521 #define PORTA2_REG PORTA
00522 #define PORTA3_REG PORTA
00523 #define PORTA4_REG PORTA
00524 #define PORTA5_REG PORTA
00525 #define PORTA6_REG PORTA
00526 #define PORTA7_REG PORTA
00527
00528
00529 #define TCNT2_0_REG TCNT2
00530 #define TCNT2_1_REG TCNT2
00531 #define TCNT2_2_REG TCNT2
00532 #define TCNT2_3_REG TCNT2
00533 #define TCNT2_4_REG TCNT2
00534 #define TCNT2_5_REG TCNT2
00535 #define TCNT2_6_REG TCNT2
00536 #define TCNT2_7_REG TCNT2
00537
00538
00539 #define TCNT0_0_REG TCNT0
00540 #define TCNT0_1_REG TCNT0
00541 #define TCNT0_2_REG TCNT0
00542 #define TCNT0_3_REG TCNT0
00543 #define TCNT0_4_REG TCNT0
00544 #define TCNT0_5_REG TCNT0
00545 #define TCNT0_6_REG TCNT0
00546 #define TCNT0_7_REG TCNT0
00547
00548
00549 #define PORF_REG MCUCSR
00550 #define EXTRF_REG MCUCSR
00551 #define BORF_REG MCUCSR
00552 #define WDRF_REG MCUCSR
00553 #define JTRF_REG MCUCSR
00554 #define SM2_REG MCUCSR
00555 #define JDT_REG MCUCSR
00556
00557
00558 #define MPCM0_REG UCSR0A
00559 #define U2X0_REG UCSR0A
00560 #define UPE0_REG UCSR0A
00561 #define DOR0_REG UCSR0A
00562 #define FE0_REG UCSR0A
00563 #define UDRE0_REG UCSR0A
00564 #define TXC0_REG UCSR0A
00565 #define RXC0_REG UCSR0A
00566
00567
00568 #define EEAR0_REG EEARL
00569 #define EEAR1_REG EEARL
00570 #define EEAR2_REG EEARL
00571 #define EEAR3_REG EEARL
00572 #define EEAR4_REG EEARL
00573 #define EEAR5_REG EEARL
00574 #define EEAR6_REG EEARL
00575 #define EEAR7_REG EEARL
00576
00577
00578 #define UBRR1L0_REG UBRR1L
00579 #define UBRR1L1_REG UBRR1L
00580 #define UBRR1L2_REG UBRR1L
00581 #define UBRR1L3_REG UBRR1L
00582 #define UBRR1L4_REG UBRR1L
00583 #define UBRR1L5_REG UBRR1L
00584 #define UBRR1L6_REG UBRR1L
00585 #define UBRR1L7_REG UBRR1L
00586
00587
00588 #define CS20_REG TCCR2
00589 #define CS21_REG TCCR2
00590 #define CS22_REG TCCR2
00591 #define WGM21_REG TCCR2
00592 #define COM20_REG TCCR2
00593 #define COM21_REG TCCR2
00594 #define WGM20_REG TCCR2
00595 #define FOC2_REG TCCR2
00596
00597
00598 #define UDR1_0_REG UDR1
00599 #define UDR1_1_REG UDR1
00600 #define UDR1_2_REG UDR1
00601 #define UDR1_3_REG UDR1
00602 #define UDR1_4_REG UDR1
00603 #define UDR1_5_REG UDR1
00604 #define UDR1_6_REG UDR1
00605 #define UDR1_7_REG UDR1
00606
00607
00608 #define OCF0_REG TIFR
00609 #define TOV0_REG TIFR
00610 #define ICF1_REG TIFR
00611 #define OCF1B_REG TIFR
00612 #define OCF1A_REG TIFR
00613 #define TOV1_REG TIFR
00614 #define TOV2_REG TIFR
00615 #define OCF2_REG TIFR
00616
00617
00618 #define UBRR0_REG UBRR0L
00619 #define UBRR1_REG UBRR0L
00620 #define UBRR2_REG UBRR0L
00621 #define UBRR3_REG UBRR0L
00622 #define UBRR4_REG UBRR0L
00623 #define UBRR5_REG UBRR0L
00624 #define UBRR6_REG UBRR0L
00625 #define UBRR7_REG UBRR0L
00626
00627
00628 #define EEAR8_REG EEARH
00629
00630
00631 #define PCINT0_REG PCMSK0
00632 #define PCINT1_REG PCMSK0
00633 #define PCINT2_REG PCMSK0
00634 #define PCINT3_REG PCMSK0
00635 #define PCINT4_REG PCMSK0
00636 #define PCINT5_REG PCMSK0
00637 #define PCINT6_REG PCMSK0
00638 #define PCINT7_REG PCMSK0
00639
00640
00641 #define PCINT8_REG PCMSK1
00642 #define PCINT9_REG PCMSK1
00643 #define PCINT10_REG PCMSK1
00644 #define PCINT11_REG PCMSK1
00645 #define PCINT12_REG PCMSK1
00646 #define PCINT13_REG PCMSK1
00647 #define PCINT14_REG PCMSK1
00648 #define PCINT15_REG PCMSK1
00649
00650
00651 #define PINC0_REG PINC
00652 #define PINC1_REG PINC
00653 #define PINC2_REG PINC
00654 #define PINC3_REG PINC
00655 #define PINC4_REG PINC
00656 #define PINC5_REG PINC
00657 #define PINC6_REG PINC
00658 #define PINC7_REG PINC
00659
00660
00661 #define PINB0_REG PINB
00662 #define PINB1_REG PINB
00663 #define PINB2_REG PINB
00664 #define PINB3_REG PINB
00665 #define PINB4_REG PINB
00666 #define PINB5_REG PINB
00667 #define PINB6_REG PINB
00668 #define PINB7_REG PINB
00669
00670
00671 #define PINA0_REG PINA
00672 #define PINA1_REG PINA
00673 #define PINA2_REG PINA
00674 #define PINA3_REG PINA
00675 #define PINA4_REG PINA
00676 #define PINA5_REG PINA
00677 #define PINA6_REG PINA
00678 #define PINA7_REG PINA
00679
00680
00681 #define PINE0_REG PINE
00682 #define PINE1_REG PINE
00683 #define PINE2_REG PINE
00684
00685
00686 #define ISC00_REG MCUCR
00687 #define ISC01_REG MCUCR
00688 #define ISC10_REG MCUCR
00689 #define ISC11_REG MCUCR
00690 #define SM1_REG MCUCR
00691 #define SE_REG MCUCR
00692 #define SRW10_REG MCUCR
00693 #define SRE_REG MCUCR
00694
00695
00696 #define OCR1AH0_REG OCR1AH
00697 #define OCR1AH1_REG OCR1AH
00698 #define OCR1AH2_REG OCR1AH
00699 #define OCR1AH3_REG OCR1AH
00700 #define OCR1AH4_REG OCR1AH
00701 #define OCR1AH5_REG OCR1AH
00702 #define OCR1AH6_REG OCR1AH
00703 #define OCR1AH7_REG OCR1AH
00704
00705
00706 #define OCR1AL0_REG OCR1AL
00707 #define OCR1AL1_REG OCR1AL
00708 #define OCR1AL2_REG OCR1AL
00709 #define OCR1AL3_REG OCR1AL
00710 #define OCR1AL4_REG OCR1AL
00711 #define OCR1AL5_REG OCR1AL
00712 #define OCR1AL6_REG OCR1AL
00713 #define OCR1AL7_REG OCR1AL
00714
00715
00716 #define SPR0_REG SPCR
00717 #define SPR1_REG SPCR
00718 #define CPHA_REG SPCR
00719 #define CPOL_REG SPCR
00720 #define MSTR_REG SPCR
00721 #define DORD_REG SPCR
00722 #define SPE_REG SPCR
00723 #define SPIE_REG SPCR
00724
00725
00726 #define OCR0_0_REG OCR0
00727 #define OCR0_1_REG OCR0
00728 #define OCR0_2_REG OCR0
00729 #define OCR0_3_REG OCR0
00730 #define OCR0_4_REG OCR0
00731 #define OCR0_5_REG OCR0
00732 #define OCR0_6_REG OCR0
00733 #define OCR0_7_REG OCR0
00734
00735
00736 #define OCR2_0_REG OCR2
00737 #define OCR2_1_REG OCR2
00738 #define OCR2_2_REG OCR2
00739 #define OCR2_3_REG OCR2
00740 #define OCR2_4_REG OCR2
00741 #define OCR2_5_REG OCR2
00742 #define OCR2_6_REG OCR2
00743 #define OCR2_7_REG OCR2
00744
00745
00746 #define TCR2UB_REG ASSR
00747 #define OCR2UB_REG ASSR
00748 #define TCN2UB_REG ASSR
00749 #define AS2_REG ASSR
00750
00751
00752 #define AD0_PORT PORTA
00753 #define AD0_BIT 0
00754
00755 #define AD1_PORT PORTA
00756 #define AD1_BIT 1
00757
00758 #define AD2_PORT PORTA
00759 #define AD2_BIT 2
00760
00761 #define AD3_PORT PORTA
00762 #define AD3_BIT 3
00763
00764 #define AD4_PORT PORTA
00765 #define AD4_BIT 4
00766
00767 #define AD5_PORT PORTA
00768 #define AD5_BIT 5
00769
00770 #define AD6_PORT PORTA
00771 #define AD6_BIT 6
00772
00773 #define AD7_PORT PORTA
00774 #define AD7_BIT 7
00775
00776 #define OC0/T0_PORT PORTB
00777 #define OC0/T0_BIT 0
00778
00779 #define OC2/T1_PORT PORTB
00780 #define OC2/T1_BIT 1
00781
00782 #define RXD1_PORT PORTB
00783 #define RXD1_BIT 2
00784 #define AIN0_PORT PORTB
00785 #define AIN0_BIT 2
00786
00787 #define TXD1_PORT PORTB
00788 #define TXD1_BIT 3
00789 #define AIN1_PORT PORTB
00790 #define AIN1_BIT 3
00791
00792 #define SS_PORT PORTB
00793 #define SS_BIT 4
00794
00795 #define MOSI_PORT PORTB
00796 #define MOSI_BIT 5
00797
00798 #define MISO_PORT PORTB
00799 #define MISO_BIT 6
00800
00801 #define SCK_PORT PORTB
00802 #define SCK_BIT 7
00803
00804 #define A8_PORT PORTC
00805 #define A8_BIT 0
00806
00807 #define A9_PORT PORTC
00808 #define A9_BIT 1
00809
00810 #define A10_PORT PORTC
00811 #define A10_BIT 2
00812
00813 #define A11_PORT PORTC
00814 #define A11_BIT 3
00815
00816 #define A12_PORT PORTC
00817 #define A12_BIT 4
00818
00819 #define A13_PORT PORTC
00820 #define A13_BIT 5
00821
00822 #define A14_PORT PORTC
00823 #define A14_BIT 6
00824
00825 #define A15_PORT PORTC
00826 #define A15_BIT 7
00827
00828 #define RXD_PORT PORTD
00829 #define RXD_BIT 0
00830
00831 #define TXD_PORT PORTD
00832 #define TXD_BIT 1
00833
00834 #define INT0_PORT PORTD
00835 #define INT0_BIT 2
00836
00837 #define INT1_PORT PORTD
00838 #define INT1_BIT 3
00839
00840
00841 #define OC1A_PORT PORTD
00842 #define OC1A_BIT 5
00843 #define TOSC2_PORT PORTD
00844 #define TOSC2_BIT 5
00845
00846 #define WR_PORT PORTD
00847 #define WR_BIT 6
00848
00849 #define RD_PORT PORTD
00850 #define RD_BIT 7
00851
00852 #define ICP/INT2_PORT PORTE
00853 #define ICP/INT2_BIT 0
00854
00855 #define ALE_PORT PORTE
00856 #define ALE_BIT 1
00857
00858 #define OC1B_PORT PORTE
00859 #define OC1B_BIT 2
00860
00861