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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define SPDR0_REG SPDR
00119 #define SPDR1_REG SPDR
00120 #define SPDR2_REG SPDR
00121 #define SPDR3_REG SPDR
00122 #define SPDR4_REG SPDR
00123 #define SPDR5_REG SPDR
00124 #define SPDR6_REG SPDR
00125 #define SPDR7_REG SPDR
00126
00127
00128 #define WDP0_REG WDTCR
00129 #define WDP1_REG WDTCR
00130 #define WDP2_REG WDTCR
00131 #define WDE_REG WDTCR
00132 #define WDTOE_REG WDTCR
00133
00134
00135 #define INT2_REG GIMSK
00136 #define INT0_REG GIMSK
00137 #define INT1_REG GIMSK
00138
00139
00140 #define ICR1H0_REG ICR1H
00141 #define ICR1H1_REG ICR1H
00142 #define ICR1H2_REG ICR1H
00143 #define ICR1H3_REG ICR1H
00144 #define ICR1H4_REG ICR1H
00145 #define ICR1H5_REG ICR1H
00146 #define ICR1H6_REG ICR1H
00147 #define ICR1H7_REG ICR1H
00148
00149
00150 #define TXB81_REG UCSR1B
00151 #define RXB81_REG UCSR1B
00152 #define CHR91_REG UCSR1B
00153 #define TXEN1_REG UCSR1B
00154 #define RXEN1_REG UCSR1B
00155 #define UDR1IE1_REG UCSR1B
00156 #define TXCIE1_REG UCSR1B
00157 #define RXCIE1_REG UCSR1B
00158
00159
00160 #define MPCM1_REG UCSR1A
00161 #define U2X1_REG UCSR1A
00162 #define OR1_REG UCSR1A
00163 #define FE1_REG UCSR1A
00164 #define UDRE1_REG UCSR1A
00165 #define TXC1_REG UCSR1A
00166 #define RXC1_REG UCSR1A
00167
00168
00169 #define CS00_REG TCCR0
00170 #define CS01_REG TCCR0
00171 #define CS02_REG TCCR0
00172 #define WGM01_REG TCCR0
00173 #define COM00_REG TCCR0
00174 #define COM01_REG TCCR0
00175 #define WGM00_REG TCCR0
00176 #define FOC0_REG TCCR0
00177
00178
00179 #define C_REG SREG
00180 #define Z_REG SREG
00181 #define N_REG SREG
00182 #define V_REG SREG
00183 #define S_REG SREG
00184 #define H_REG SREG
00185 #define T_REG SREG
00186 #define I_REG SREG
00187
00188
00189 #define DDB0_REG DDRB
00190 #define DDB1_REG DDRB
00191 #define DDB2_REG DDRB
00192 #define DDB3_REG DDRB
00193 #define DDB4_REG DDRB
00194 #define DDB5_REG DDRB
00195 #define DDB6_REG DDRB
00196 #define DDB7_REG DDRB
00197
00198
00199 #define UBRR10_REG UBRR1
00200 #define UBRR11_REG UBRR1
00201 #define UBRR12_REG UBRR1
00202 #define UBRR13_REG UBRR1
00203 #define UBRR14_REG UBRR1
00204 #define UBRR15_REG UBRR1
00205 #define UBRR16_REG UBRR1
00206 #define UBRR17_REG UBRR1
00207
00208
00209 #define SPI2X_REG SPSR
00210 #define WCOL_REG SPSR
00211 #define SPIF_REG SPSR
00212
00213
00214 #define EEDR0_REG EEDR
00215 #define EEDR1_REG EEDR
00216 #define EEDR2_REG EEDR
00217 #define EEDR3_REG EEDR
00218 #define EEDR4_REG EEDR
00219 #define EEDR5_REG EEDR
00220 #define EEDR6_REG EEDR
00221 #define EEDR7_REG EEDR
00222
00223
00224 #define DDC0_REG DDRC
00225 #define DDC1_REG DDRC
00226 #define DDC2_REG DDRC
00227 #define DDC3_REG DDRC
00228 #define DDC4_REG DDRC
00229 #define DDC5_REG DDRC
00230 #define DDC6_REG DDRC
00231 #define DDC7_REG DDRC
00232
00233
00234 #define DDA0_REG DDRA
00235 #define DDA1_REG DDRA
00236 #define DDA2_REG DDRA
00237 #define DDA3_REG DDRA
00238 #define DDA4_REG DDRA
00239 #define DDA5_REG DDRA
00240 #define DDA6_REG DDRA
00241 #define DDA7_REG DDRA
00242
00243
00244 #define WGM10_REG TCCR1A
00245 #define WGM11_REG TCCR1A
00246 #define FOC1B_REG TCCR1A
00247 #define FOC1A_REG TCCR1A
00248 #define COM1B0_REG TCCR1A
00249 #define COM1B1_REG TCCR1A
00250 #define COM1A0_REG TCCR1A
00251 #define COM1A1_REG TCCR1A
00252
00253
00254 #define DDD0_REG DDRD
00255 #define DDD1_REG DDRD
00256 #define DDD2_REG DDRD
00257 #define DDD3_REG DDRD
00258 #define DDD4_REG DDRD
00259 #define DDD5_REG DDRD
00260 #define DDD6_REG DDRD
00261 #define DDD7_REG DDRD
00262
00263
00264 #define CS10_REG TCCR1B
00265 #define CS11_REG TCCR1B
00266 #define CS12_REG TCCR1B
00267 #define CTC1_REG TCCR1B
00268 #define ICES1_REG TCCR1B
00269 #define ICNC1_REG TCCR1B
00270
00271
00272 #define INTF2_REG GIFR
00273 #define INTF0_REG GIFR
00274 #define INTF1_REG GIFR
00275
00276
00277 #define OCIE0_REG TIMSK
00278 #define TOIE0_REG TIMSK
00279 #define OCIE2_REG TIMSK
00280 #define TOIE2_REG TIMSK
00281 #define TICIE1_REG TIMSK
00282 #define OCIE1B_REG TIMSK
00283 #define OCIE1A_REG TIMSK
00284 #define TOIE1_REG TIMSK
00285
00286
00287 #define ICR1L0_REG ICR1L
00288 #define ICR1L1_REG ICR1L
00289 #define ICR1L2_REG ICR1L
00290 #define ICR1L3_REG ICR1L
00291 #define ICR1L4_REG ICR1L
00292 #define ICR1L5_REG ICR1L
00293 #define ICR1L6_REG ICR1L
00294 #define ICR1L7_REG ICR1L
00295
00296
00297 #define PSR10_REG SFIOR
00298 #define PSR2_REG SFIOR
00299
00300
00301 #define UDR00_REG UDR0
00302 #define UDR01_REG UDR0
00303 #define UDR02_REG UDR0
00304 #define UDR03_REG UDR0
00305 #define UDR04_REG UDR0
00306 #define UDR05_REG UDR0
00307 #define UDR06_REG UDR0
00308 #define UDR07_REG UDR0
00309
00310
00311 #define SP8_REG SPH
00312 #define SP9_REG SPH
00313 #define SP10_REG SPH
00314 #define SP11_REG SPH
00315 #define SP12_REG SPH
00316 #define SP13_REG SPH
00317 #define SP14_REG SPH
00318 #define SP15_REG SPH
00319
00320
00321 #define OCR1BL0_REG OCR1BL
00322 #define OCR1BL1_REG OCR1BL
00323 #define OCR1BL2_REG OCR1BL
00324 #define OCR1BL3_REG OCR1BL
00325 #define OCR1BL4_REG OCR1BL
00326 #define OCR1BL5_REG OCR1BL
00327 #define OCR1BL6_REG OCR1BL
00328 #define OCR1BL7_REG OCR1BL
00329
00330
00331 #define UBRRHI00_REG UBRRHI
00332 #define UBRRHI01_REG UBRRHI
00333 #define UBRRHI02_REG UBRRHI
00334 #define UBRRHI03_REG UBRRHI
00335 #define UBRRHI10_REG UBRRHI
00336 #define UBRRHI11_REG UBRRHI
00337 #define UBRRHI12_REG UBRRHI
00338 #define UBRRHI13_REG UBRRHI
00339
00340
00341 #define ISC2_REG EMCUCR
00342 #define SRW11_REG EMCUCR
00343 #define SRW00_REG EMCUCR
00344 #define SRW01_REG EMCUCR
00345 #define SRL0_REG EMCUCR
00346 #define SRL1_REG EMCUCR
00347 #define SRL2_REG EMCUCR
00348 #define SM0_REG EMCUCR
00349
00350
00351 #define SP0_REG SPL
00352 #define SP1_REG SPL
00353 #define SP2_REG SPL
00354 #define SP3_REG SPL
00355 #define SP4_REG SPL
00356 #define SP5_REG SPL
00357 #define SP6_REG SPL
00358 #define SP7_REG SPL
00359
00360
00361 #define OCR1BH0_REG OCR1BH
00362 #define OCR1BH1_REG OCR1BH
00363 #define OCR1BH2_REG OCR1BH
00364 #define OCR1BH3_REG OCR1BH
00365 #define OCR1BH4_REG OCR1BH
00366 #define OCR1BH5_REG OCR1BH
00367 #define OCR1BH6_REG OCR1BH
00368 #define OCR1BH7_REG OCR1BH
00369
00370
00371 #define PIND0_REG PIND
00372 #define PIND1_REG PIND
00373 #define PIND2_REG PIND
00374 #define PIND3_REG PIND
00375 #define PIND4_REG PIND
00376 #define PIND5_REG PIND
00377 #define PIND6_REG PIND
00378 #define PIND7_REG PIND
00379
00380
00381 #define SPMEN_REG SPMCR
00382 #define PGERS_REG SPMCR
00383 #define PGWRT_REG SPMCR
00384 #define BLBSET_REG SPMCR
00385
00386
00387 #define DDE0_REG DDRE
00388 #define DDE1_REG DDRE
00389 #define DDE2_REG DDRE
00390
00391
00392 #define PORF_REG MCUSR
00393 #define EXTRF_REG MCUSR
00394 #define BORF_REG MCUSR
00395 #define WDRF_REG MCUSR
00396
00397
00398 #define ACIS0_REG ACSR
00399 #define ACIS1_REG ACSR
00400 #define ACIC_REG ACSR
00401 #define ACIE_REG ACSR
00402 #define ACI_REG ACSR
00403 #define ACO_REG ACSR
00404 #define AINBG_REG ACSR
00405 #define ACD_REG ACSR
00406
00407
00408 #define EERE_REG EECR
00409 #define EEWE_REG EECR
00410 #define EEMWE_REG EECR
00411 #define EERIE_REG EECR
00412
00413
00414 #define UBRR00_REG UBRR0
00415 #define UBRR01_REG UBRR0
00416 #define UBRR02_REG UBRR0
00417 #define UBRR03_REG UBRR0
00418 #define UBRR04_REG UBRR0
00419 #define UBRR05_REG UBRR0
00420 #define UBRR06_REG UBRR0
00421 #define UBRR07_REG UBRR0
00422
00423
00424 #define PORTE0_REG PORTE
00425 #define PORTE1_REG PORTE
00426 #define PORTE2_REG PORTE
00427
00428
00429 #define TCNT1L0_REG TCNT1L
00430 #define TCNT1L1_REG TCNT1L
00431 #define TCNT1L2_REG TCNT1L
00432 #define TCNT1L3_REG TCNT1L
00433 #define TCNT1L4_REG TCNT1L
00434 #define TCNT1L5_REG TCNT1L
00435 #define TCNT1L6_REG TCNT1L
00436 #define TCNT1L7_REG TCNT1L
00437
00438
00439 #define PORTB0_REG PORTB
00440 #define PORTB1_REG PORTB
00441 #define PORTB2_REG PORTB
00442 #define PORTB3_REG PORTB
00443 #define PORTB4_REG PORTB
00444 #define PORTB5_REG PORTB
00445 #define PORTB6_REG PORTB
00446 #define PORTB7_REG PORTB
00447
00448
00449 #define PORTD0_REG PORTD
00450 #define PORTD1_REG PORTD
00451 #define PORTD2_REG PORTD
00452 #define PORTD3_REG PORTD
00453 #define PORTD4_REG PORTD
00454 #define PORTD5_REG PORTD
00455 #define PORTD6_REG PORTD
00456 #define PORTD7_REG PORTD
00457
00458
00459 #define TXB80_REG UCSR0B
00460 #define RXB80_REG UCSR0B
00461 #define CHR90_REG UCSR0B
00462 #define TXEN0_REG UCSR0B
00463 #define RXEN0_REG UCSR0B
00464 #define UDR0IE0_REG UCSR0B
00465 #define TXCIE0_REG UCSR0B
00466 #define RXCIE0_REG UCSR0B
00467
00468
00469 #define TCNT1H0_REG TCNT1H
00470 #define TCNT1H1_REG TCNT1H
00471 #define TCNT1H2_REG TCNT1H
00472 #define TCNT1H3_REG TCNT1H
00473 #define TCNT1H4_REG TCNT1H
00474 #define TCNT1H5_REG TCNT1H
00475 #define TCNT1H6_REG TCNT1H
00476 #define TCNT1H7_REG TCNT1H
00477
00478
00479 #define PORTC0_REG PORTC
00480 #define PORTC1_REG PORTC
00481 #define PORTC2_REG PORTC
00482 #define PORTC3_REG PORTC
00483 #define PORTC4_REG PORTC
00484 #define PORTC5_REG PORTC
00485 #define PORTC6_REG PORTC
00486 #define PORTC7_REG PORTC
00487
00488
00489 #define PORTA0_REG PORTA
00490 #define PORTA1_REG PORTA
00491 #define PORTA2_REG PORTA
00492 #define PORTA3_REG PORTA
00493 #define PORTA4_REG PORTA
00494 #define PORTA5_REG PORTA
00495 #define PORTA6_REG PORTA
00496 #define PORTA7_REG PORTA
00497
00498
00499 #define TCNT2_0_REG TCNT2
00500 #define TCNT2_1_REG TCNT2
00501 #define TCNT2_2_REG TCNT2
00502 #define TCNT2_3_REG TCNT2
00503 #define TCNT2_4_REG TCNT2
00504 #define TCNT2_5_REG TCNT2
00505 #define TCNT2_6_REG TCNT2
00506 #define TCNT2_7_REG TCNT2
00507
00508
00509 #define TCNT0_0_REG TCNT0
00510 #define TCNT0_1_REG TCNT0
00511 #define TCNT0_2_REG TCNT0
00512 #define TCNT0_3_REG TCNT0
00513 #define TCNT0_4_REG TCNT0
00514 #define TCNT0_5_REG TCNT0
00515 #define TCNT0_6_REG TCNT0
00516 #define TCNT0_7_REG TCNT0
00517
00518
00519 #define MPCM0_REG UCSR0A
00520 #define U2X0_REG UCSR0A
00521 #define OR0_REG UCSR0A
00522 #define FE0_REG UCSR0A
00523 #define UDRE0_REG UCSR0A
00524 #define TXC0_REG UCSR0A
00525 #define RXC0_REG UCSR0A
00526
00527
00528 #define CS20_REG TCCR2
00529 #define CS21_REG TCCR2
00530 #define CS22_REG TCCR2
00531 #define CTC2_REG TCCR2
00532 #define COM20_REG TCCR2
00533 #define COM21_REG TCCR2
00534 #define PWM2_REG TCCR2
00535 #define FOC2_REG TCCR2
00536
00537
00538 #define UDR10_REG UDR1
00539 #define UDR11_REG UDR1
00540 #define UDR12_REG UDR1
00541 #define UDR13_REG UDR1
00542 #define UDR14_REG UDR1
00543 #define UDR15_REG UDR1
00544 #define UDR16_REG UDR1
00545 #define UDR17_REG UDR1
00546
00547
00548 #define OCF0_REG TIFR
00549 #define TOV0_REG TIFR
00550 #define OCF2_REG TIFR
00551 #define TOV2_REG TIFR
00552 #define ICF1_REG TIFR
00553 #define OCF1B_REG TIFR
00554 #define OCF1A_REG TIFR
00555 #define TOV1_REG TIFR
00556
00557
00558 #define EEAR8_REG EEARH
00559
00560
00561 #define EEAR0_REG EEARL
00562 #define EEAR1_REG EEARL
00563 #define EEAR2_REG EEARL
00564 #define EEAR3_REG EEARL
00565 #define EEAR4_REG EEARL
00566 #define EEAR5_REG EEARL
00567 #define EEAR6_REG EEARL
00568 #define EEAR7_REG EEARL
00569
00570
00571 #define PINC0_REG PINC
00572 #define PINC1_REG PINC
00573 #define PINC2_REG PINC
00574 #define PINC3_REG PINC
00575 #define PINC4_REG PINC
00576 #define PINC5_REG PINC
00577 #define PINC6_REG PINC
00578 #define PINC7_REG PINC
00579
00580
00581 #define PINB0_REG PINB
00582 #define PINB1_REG PINB
00583 #define PINB2_REG PINB
00584 #define PINB3_REG PINB
00585 #define PINB4_REG PINB
00586 #define PINB5_REG PINB
00587 #define PINB6_REG PINB
00588 #define PINB7_REG PINB
00589
00590
00591 #define PINA0_REG PINA
00592 #define PINA1_REG PINA
00593 #define PINA2_REG PINA
00594 #define PINA3_REG PINA
00595 #define PINA4_REG PINA
00596 #define PINA5_REG PINA
00597 #define PINA6_REG PINA
00598 #define PINA7_REG PINA
00599
00600
00601 #define PINE0_REG PINE
00602 #define PINE1_REG PINE
00603 #define PINE2_REG PINE
00604
00605
00606 #define ISC00_REG MCUCR
00607 #define ISC01_REG MCUCR
00608 #define ISC10_REG MCUCR
00609 #define ISC11_REG MCUCR
00610 #define SM1_REG MCUCR
00611 #define SE_REG MCUCR
00612 #define SRW10_REG MCUCR
00613 #define SRE_REG MCUCR
00614
00615
00616 #define OCR1AH0_REG OCR1AH
00617 #define OCR1AH1_REG OCR1AH
00618 #define OCR1AH2_REG OCR1AH
00619 #define OCR1AH3_REG OCR1AH
00620 #define OCR1AH4_REG OCR1AH
00621 #define OCR1AH5_REG OCR1AH
00622 #define OCR1AH6_REG OCR1AH
00623 #define OCR1AH7_REG OCR1AH
00624
00625
00626 #define OCR1AL0_REG OCR1AL
00627 #define OCR1AL1_REG OCR1AL
00628 #define OCR1AL2_REG OCR1AL
00629 #define OCR1AL3_REG OCR1AL
00630 #define OCR1AL4_REG OCR1AL
00631 #define OCR1AL5_REG OCR1AL
00632 #define OCR1AL6_REG OCR1AL
00633 #define OCR1AL7_REG OCR1AL
00634
00635
00636 #define SPR0_REG SPCR
00637 #define SPR1_REG SPCR
00638 #define CPHA_REG SPCR
00639 #define CPOL_REG SPCR
00640 #define MSTR_REG SPCR
00641 #define DORD_REG SPCR
00642 #define SPE_REG SPCR
00643 #define SPIE_REG SPCR
00644
00645
00646 #define OCR0_0_REG OCR0
00647 #define OCR0_1_REG OCR0
00648 #define OCR0_2_REG OCR0
00649 #define OCR0_3_REG OCR0
00650 #define OCR0_4_REG OCR0
00651 #define OCR0_5_REG OCR0
00652 #define OCR0_6_REG OCR0
00653 #define OCR0_7_REG OCR0
00654
00655
00656 #define OCR2_0_REG OCR2
00657 #define OCR2_1_REG OCR2
00658 #define OCR2_2_REG OCR2
00659 #define OCR2_3_REG OCR2
00660 #define OCR2_4_REG OCR2
00661 #define OCR2_5_REG OCR2
00662 #define OCR2_6_REG OCR2
00663 #define OCR2_7_REG OCR2
00664
00665
00666 #define TCR2UB_REG ASSR
00667 #define OCR2UB_REG ASSR
00668 #define TCN2UB_REG ASSR
00669 #define AS2_REG ASSR
00670
00671
00672 #define AD0_PORT PORTA
00673 #define AD0_BIT 0
00674
00675 #define AD1_PORT PORTA
00676 #define AD1_BIT 1
00677
00678 #define AD2_PORT PORTA
00679 #define AD2_BIT 2
00680
00681 #define AD3_PORT PORTA
00682 #define AD3_BIT 3
00683
00684 #define AD4_PORT PORTA
00685 #define AD4_BIT 4
00686
00687 #define AD5_PORT PORTA
00688 #define AD5_BIT 5
00689
00690 #define AD6_PORT PORTA
00691 #define AD6_BIT 6
00692
00693 #define AD7_PORT PORTA
00694 #define AD7_BIT 7
00695
00696 #define OC0/T0_PORT PORTB
00697 #define OC0/T0_BIT 0
00698
00699 #define OC2/T1_PORT PORTB
00700 #define OC2/T1_BIT 1
00701
00702 #define RXD1_PORT PORTB
00703 #define RXD1_BIT 2
00704 #define AIN0_PORT PORTB
00705 #define AIN0_BIT 2
00706
00707 #define TXD1_PORT PORTB
00708 #define TXD1_BIT 3
00709 #define AIN1_PORT PORTB
00710 #define AIN1_BIT 3
00711
00712 #define SS_PORT PORTB
00713 #define SS_BIT 4
00714
00715 #define MOSI_PORT PORTB
00716 #define MOSI_BIT 5
00717
00718 #define MISO_PORT PORTB
00719 #define MISO_BIT 6
00720
00721 #define SCK_PORT PORTB
00722 #define SCK_BIT 7
00723
00724 #define A8_PORT PORTC
00725 #define A8_BIT 0
00726
00727 #define A9_PORT PORTC
00728 #define A9_BIT 1
00729
00730 #define A10_PORT PORTC
00731 #define A10_BIT 2
00732
00733 #define A11_PORT PORTC
00734 #define A11_BIT 3
00735
00736 #define A12_PORT PORTC
00737 #define A12_BIT 4
00738
00739 #define A13_PORT PORTC
00740 #define A13_BIT 5
00741
00742 #define A14_PORT PORTC
00743 #define A14_BIT 6
00744
00745 #define A15_PORT PORTC
00746 #define A15_BIT 7
00747
00748 #define RXD_PORT PORTD
00749 #define RXD_BIT 0
00750
00751 #define TXD_PORT PORTD
00752 #define TXD_BIT 1
00753
00754 #define INT0_PORT PORTD
00755 #define INT0_BIT 2
00756
00757 #define INT1_PORT PORTD
00758 #define INT1_BIT 3
00759
00760
00761 #define OC1A_PORT PORTD
00762 #define OC1A_BIT 5
00763 #define TOSC2_PORT PORTD
00764 #define TOSC2_BIT 5
00765
00766 #define WR_PORT PORTD
00767 #define WR_BIT 6
00768
00769 #define RD_PORT PORTD
00770 #define RD_BIT 7
00771
00772 #define ICP/INT2_PORT PORTE
00773 #define ICP/INT2_BIT 0
00774
00775 #define ALE_PORT PORTE
00776 #define ALE_BIT 1
00777
00778 #define OC1B_PORT PORTE
00779 #define OC1B_BIT 2
00780
00781