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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_FALL 6
00092 #define TIMER3_PRESCALER_DIV_RISE 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 -1
00101 #define TIMER3_PRESCALER_REG_7 -2
00102
00103
00104
00105 #define TIMER0_AVAILABLE
00106 #define TIMER0A_AVAILABLE
00107 #define TIMER0B_AVAILABLE
00108 #define TIMER1_AVAILABLE
00109 #define TIMER1A_AVAILABLE
00110 #define TIMER1B_AVAILABLE
00111 #define TIMER2_AVAILABLE
00112 #define TIMER2A_AVAILABLE
00113 #define TIMER2B_AVAILABLE
00114 #define TIMER3_AVAILABLE
00115 #define TIMER3A_AVAILABLE
00116 #define TIMER3B_AVAILABLE
00117
00118
00119 #define SIG_OVERFLOW0_NUM 0
00120 #define SIG_OVERFLOW1_NUM 1
00121 #define SIG_OVERFLOW2_NUM 2
00122 #define SIG_OVERFLOW3_NUM 3
00123 #define SIG_OVERFLOW_TOTAL_NUM 4
00124
00125
00126 #define SIG_OUTPUT_COMPARE0A_NUM 0
00127 #define SIG_OUTPUT_COMPARE0B_NUM 1
00128 #define SIG_OUTPUT_COMPARE1A_NUM 2
00129 #define SIG_OUTPUT_COMPARE1B_NUM 3
00130 #define SIG_OUTPUT_COMPARE2A_NUM 4
00131 #define SIG_OUTPUT_COMPARE2B_NUM 5
00132 #define SIG_OUTPUT_COMPARE3A_NUM 6
00133 #define SIG_OUTPUT_COMPARE3B_NUM 7
00134 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
00135
00136
00137 #define PWM0A_NUM 0
00138 #define PWM0B_NUM 1
00139 #define PWM1A_NUM 2
00140 #define PWM1B_NUM 3
00141 #define PWM2A_NUM 4
00142 #define PWM2B_NUM 5
00143 #define PWM3A_NUM 6
00144 #define PWM3B_NUM 7
00145 #define PWM_TOTAL_NUM 8
00146
00147
00148 #define SIG_INPUT_CAPTURE1_NUM 0
00149 #define SIG_INPUT_CAPTURE3_NUM 1
00150 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00151
00152
00153
00154 #define MUX0_REG ADMUX
00155 #define MUX1_REG ADMUX
00156 #define MUX2_REG ADMUX
00157 #define MUX3_REG ADMUX
00158 #define MUX4_REG ADMUX
00159 #define ADLAR_REG ADMUX
00160 #define REFS0_REG ADMUX
00161 #define REFS1_REG ADMUX
00162
00163
00164 #define WDP0_REG WDTCSR
00165 #define WDP1_REG WDTCSR
00166 #define WDP2_REG WDTCSR
00167 #define WDE_REG WDTCSR
00168 #define WDCE_REG WDTCSR
00169 #define WDP3_REG WDTCSR
00170 #define WDIE_REG WDTCSR
00171 #define WDIF_REG WDTCSR
00172
00173
00174 #define EEDR0_REG EEDR
00175 #define EEDR1_REG EEDR
00176 #define EEDR2_REG EEDR
00177 #define EEDR3_REG EEDR
00178 #define EEDR4_REG EEDR
00179 #define EEDR5_REG EEDR
00180 #define EEDR6_REG EEDR
00181 #define EEDR7_REG EEDR
00182
00183
00184 #define ACIS0_REG ACSR
00185 #define ACIS1_REG ACSR
00186 #define ACIC_REG ACSR
00187 #define ACIE_REG ACSR
00188 #define ACI_REG ACSR
00189 #define ACO_REG ACSR
00190 #define ACBG_REG ACSR
00191 #define ACD_REG ACSR
00192
00193
00194 #define RAMPZ0_REG RAMPZ
00195
00196
00197 #define OCR2B_0_REG OCR2B
00198 #define OCR2B_1_REG OCR2B
00199 #define OCR2B_2_REG OCR2B
00200 #define OCR2B_3_REG OCR2B
00201 #define OCR2B_4_REG OCR2B
00202 #define OCR2B_5_REG OCR2B
00203 #define OCR2B_6_REG OCR2B
00204 #define OCR2B_7_REG OCR2B
00205
00206
00207 #define OCR2A_0_REG OCR2A
00208 #define OCR2A_1_REG OCR2A
00209 #define OCR2A_2_REG OCR2A
00210 #define OCR2A_3_REG OCR2A
00211 #define OCR2A_4_REG OCR2A
00212 #define OCR2A_5_REG OCR2A
00213 #define OCR2A_6_REG OCR2A
00214 #define OCR2A_7_REG OCR2A
00215
00216
00217 #define SPDR0_REG SPDR
00218 #define SPDR1_REG SPDR
00219 #define SPDR2_REG SPDR
00220 #define SPDR3_REG SPDR
00221 #define SPDR4_REG SPDR
00222 #define SPDR5_REG SPDR
00223 #define SPDR6_REG SPDR
00224 #define SPDR7_REG SPDR
00225
00226
00227 #define SPI2X_REG SPSR
00228 #define WCOL_REG SPSR
00229 #define SPIF_REG SPSR
00230
00231
00232 #define SP8_REG SPH
00233 #define SP9_REG SPH
00234 #define SP10_REG SPH
00235 #define SP11_REG SPH
00236 #define SP12_REG SPH
00237 #define SP13_REG SPH
00238 #define SP14_REG SPH
00239 #define SP15_REG SPH
00240
00241
00242 #define ICR1L0_REG ICR1L
00243 #define ICR1L1_REG ICR1L
00244 #define ICR1L2_REG ICR1L
00245 #define ICR1L3_REG ICR1L
00246 #define ICR1L4_REG ICR1L
00247 #define ICR1L5_REG ICR1L
00248 #define ICR1L6_REG ICR1L
00249 #define ICR1L7_REG ICR1L
00250
00251
00252 #define EEAR8_REG EEARH
00253 #define EEAR9_REG EEARH
00254 #define EEAR10_REG EEARH
00255 #define EEAR11_REG EEARH
00256
00257
00258 #define MPCM0_REG UCSR0A
00259 #define U2X0_REG UCSR0A
00260 #define UPE0_REG UCSR0A
00261 #define DOR0_REG UCSR0A
00262 #define FE0_REG UCSR0A
00263 #define UDRE0_REG UCSR0A
00264 #define TXC0_REG UCSR0A
00265 #define RXC0_REG UCSR0A
00266
00267
00268 #define UCPOL0_REG UCSR0C
00269 #define UCSZ00_REG UCSR0C
00270 #define UCSZ01_REG UCSR0C
00271 #define USBS0_REG UCSR0C
00272 #define UPM00_REG UCSR0C
00273 #define UPM01_REG UCSR0C
00274 #define UMSEL00_REG UCSR0C
00275 #define UMSEL01_REG UCSR0C
00276
00277
00278 #define TXB80_REG UCSR0B
00279 #define RXB80_REG UCSR0B
00280 #define UCSZ02_REG UCSR0B
00281 #define TXEN0_REG UCSR0B
00282 #define RXEN0_REG UCSR0B
00283 #define UDRIE0_REG UCSR0B
00284 #define TXCIE0_REG UCSR0B
00285 #define RXCIE0_REG UCSR0B
00286
00287
00288 #define TCNT1H0_REG TCNT1H
00289 #define TCNT1H1_REG TCNT1H
00290 #define TCNT1H2_REG TCNT1H
00291 #define TCNT1H3_REG TCNT1H
00292 #define TCNT1H4_REG TCNT1H
00293 #define TCNT1H5_REG TCNT1H
00294 #define TCNT1H6_REG TCNT1H
00295 #define TCNT1H7_REG TCNT1H
00296
00297
00298 #define PORTC0_REG PORTC
00299 #define PORTC1_REG PORTC
00300 #define PORTC2_REG PORTC
00301 #define PORTC3_REG PORTC
00302 #define PORTC4_REG PORTC
00303 #define PORTC5_REG PORTC
00304 #define PORTC6_REG PORTC
00305 #define PORTC7_REG PORTC
00306
00307
00308 #define PORTA0_REG PORTA
00309 #define PORTA1_REG PORTA
00310 #define PORTA2_REG PORTA
00311 #define PORTA3_REG PORTA
00312 #define PORTA4_REG PORTA
00313 #define PORTA5_REG PORTA
00314 #define PORTA6_REG PORTA
00315 #define PORTA7_REG PORTA
00316
00317
00318 #define INT0_REG EIMSK
00319 #define INT1_REG EIMSK
00320 #define INT2_REG EIMSK
00321
00322
00323 #define UDR1_0_REG UDR1
00324 #define UDR1_1_REG UDR1
00325 #define UDR1_2_REG UDR1
00326 #define UDR1_3_REG UDR1
00327 #define UDR1_4_REG UDR1
00328 #define UDR1_5_REG UDR1
00329 #define UDR1_6_REG UDR1
00330 #define UDR1_7_REG UDR1
00331
00332
00333 #define UDR0_0_REG UDR0
00334 #define UDR0_1_REG UDR0
00335 #define UDR0_2_REG UDR0
00336 #define UDR0_3_REG UDR0
00337 #define UDR0_4_REG UDR0
00338 #define UDR0_5_REG UDR0
00339 #define UDR0_6_REG UDR0
00340 #define UDR0_7_REG UDR0
00341
00342
00343 #define ISC00_REG EICRA
00344 #define ISC01_REG EICRA
00345 #define ISC10_REG EICRA
00346 #define ISC11_REG EICRA
00347 #define ISC20_REG EICRA
00348 #define ISC21_REG EICRA
00349
00350
00351 #define ADC0D_REG DIDR0
00352 #define ADC1D_REG DIDR0
00353 #define ADC2D_REG DIDR0
00354 #define ADC3D_REG DIDR0
00355 #define ADC4D_REG DIDR0
00356 #define ADC5D_REG DIDR0
00357 #define ADC6D_REG DIDR0
00358 #define ADC7D_REG DIDR0
00359
00360
00361 #define AIN0D_REG DIDR1
00362 #define AIN1D_REG DIDR1
00363
00364
00365 #define TCR2BUB_REG ASSR
00366 #define TCR2AUB_REG ASSR
00367 #define OCR2BUB_REG ASSR
00368 #define OCR2AUB_REG ASSR
00369 #define TCN2UB_REG ASSR
00370 #define AS2_REG ASSR
00371 #define EXCLK_REG ASSR
00372
00373
00374 #define CLKPS0_REG CLKPR
00375 #define CLKPS1_REG CLKPR
00376 #define CLKPS2_REG CLKPR
00377 #define CLKPS3_REG CLKPR
00378 #define CLKPCE_REG CLKPR
00379
00380
00381 #define C_REG SREG
00382 #define Z_REG SREG
00383 #define N_REG SREG
00384 #define V_REG SREG
00385 #define S_REG SREG
00386 #define H_REG SREG
00387 #define T_REG SREG
00388 #define I_REG SREG
00389
00390
00391 #define UBRR_0_REG UBRR1L
00392 #define UBRR_1_REG UBRR1L
00393 #define UBRR_2_REG UBRR1L
00394 #define UBRR_3_REG UBRR1L
00395 #define UBRR_4_REG UBRR1L
00396 #define UBRR_5_REG UBRR1L
00397 #define UBRR_6_REG UBRR1L
00398 #define UBRR_7_REG UBRR1L
00399
00400
00401 #define DDC0_REG DDRC
00402 #define DDC1_REG DDRC
00403 #define DDC2_REG DDRC
00404 #define DDC3_REG DDRC
00405 #define DDC4_REG DDRC
00406 #define DDC5_REG DDRC
00407 #define DDC6_REG DDRC
00408 #define DDC7_REG DDRC
00409
00410
00411
00412
00413
00414
00415
00416
00417
00418
00419
00420
00421 #define DDA0_REG DDRA
00422 #define DDA1_REG DDRA
00423 #define DDA2_REG DDRA
00424 #define DDA3_REG DDRA
00425 #define DDA4_REG DDRA
00426 #define DDA5_REG DDRA
00427 #define DDA6_REG DDRA
00428 #define DDA7_REG DDRA
00429
00430
00431 #define UBRR_8_REG UBRR1H
00432 #define UBRR_9_REG UBRR1H
00433 #define UBRR_10_REG UBRR1H
00434 #define UBRR_11_REG UBRR1H
00435
00436
00437
00438
00439
00440
00441
00442
00443
00444
00445
00446
00447 #define CS10_REG TCCR1B
00448 #define CS11_REG TCCR1B
00449 #define CS12_REG TCCR1B
00450 #define WGM12_REG TCCR1B
00451 #define WGM13_REG TCCR1B
00452 #define ICES1_REG TCCR1B
00453 #define ICNC1_REG TCCR1B
00454
00455
00456 #define CAL0_REG OSCCAL
00457 #define CAL1_REG OSCCAL
00458 #define CAL2_REG OSCCAL
00459 #define CAL3_REG OSCCAL
00460 #define CAL4_REG OSCCAL
00461 #define CAL5_REG OSCCAL
00462 #define CAL6_REG OSCCAL
00463 #define CAL7_REG OSCCAL
00464
00465
00466 #define DDD0_REG DDRD
00467 #define DDD1_REG DDRD
00468 #define DDD2_REG DDRD
00469 #define DDD3_REG DDRD
00470 #define DDD4_REG DDRD
00471 #define DDD5_REG DDRD
00472 #define DDD6_REG DDRD
00473 #define DDD7_REG DDRD
00474
00475
00476 #define GPIOR10_REG GPIOR1
00477 #define GPIOR11_REG GPIOR1
00478 #define GPIOR12_REG GPIOR1
00479 #define GPIOR13_REG GPIOR1
00480 #define GPIOR14_REG GPIOR1
00481 #define GPIOR15_REG GPIOR1
00482 #define GPIOR16_REG GPIOR1
00483 #define GPIOR17_REG GPIOR1
00484
00485
00486 #define GPIOR00_REG GPIOR0
00487 #define GPIOR01_REG GPIOR0
00488 #define GPIOR02_REG GPIOR0
00489 #define GPIOR03_REG GPIOR0
00490 #define GPIOR04_REG GPIOR0
00491 #define GPIOR05_REG GPIOR0
00492 #define GPIOR06_REG GPIOR0
00493 #define GPIOR07_REG GPIOR0
00494
00495
00496 #define GPIOR20_REG GPIOR2
00497 #define GPIOR21_REG GPIOR2
00498 #define GPIOR22_REG GPIOR2
00499 #define GPIOR23_REG GPIOR2
00500 #define GPIOR24_REG GPIOR2
00501 #define GPIOR25_REG GPIOR2
00502 #define GPIOR26_REG GPIOR2
00503 #define GPIOR27_REG GPIOR2
00504
00505
00506 #define PCIE0_REG PCICR
00507 #define PCIE1_REG PCICR
00508 #define PCIE2_REG PCICR
00509 #define PCIE3_REG PCICR
00510
00511
00512 #define TCNT2_0_REG TCNT2
00513 #define TCNT2_1_REG TCNT2
00514 #define TCNT2_2_REG TCNT2
00515 #define TCNT2_3_REG TCNT2
00516 #define TCNT2_4_REG TCNT2
00517 #define TCNT2_5_REG TCNT2
00518 #define TCNT2_6_REG TCNT2
00519 #define TCNT2_7_REG TCNT2
00520
00521
00522 #define TCNT0_0_REG TCNT0
00523 #define TCNT0_1_REG TCNT0
00524 #define TCNT0_2_REG TCNT0
00525 #define TCNT0_3_REG TCNT0
00526 #define TCNT0_4_REG TCNT0
00527 #define TCNT0_5_REG TCNT0
00528 #define TCNT0_6_REG TCNT0
00529 #define TCNT0_7_REG TCNT0
00530
00531
00532 #define TWGCE_REG TWAR
00533 #define TWA0_REG TWAR
00534 #define TWA1_REG TWAR
00535 #define TWA2_REG TWAR
00536 #define TWA3_REG TWAR
00537 #define TWA4_REG TWAR
00538 #define TWA5_REG TWAR
00539 #define TWA6_REG TWAR
00540
00541
00542 #define CS00_REG TCCR0B
00543 #define CS01_REG TCCR0B
00544 #define CS02_REG TCCR0B
00545 #define WGM02_REG TCCR0B
00546 #define FOC0B_REG TCCR0B
00547 #define FOC0A_REG TCCR0B
00548
00549
00550 #define WGM00_REG TCCR0A
00551 #define WGM01_REG TCCR0A
00552 #define COM0B0_REG TCCR0A
00553 #define COM0B1_REG TCCR0A
00554 #define COM0A0_REG TCCR0A
00555 #define COM0A1_REG TCCR0A
00556
00557
00558 #define TOV2_REG TIFR2
00559 #define OCF2A_REG TIFR2
00560 #define OCF2B_REG TIFR2
00561
00562
00563 #define TOV3_REG TIFR3
00564 #define OCF3A_REG TIFR3
00565 #define OCF3B_REG TIFR3
00566 #define ICF3_REG TIFR3
00567
00568
00569 #define SPR0_REG SPCR
00570 #define SPR1_REG SPCR
00571 #define CPHA_REG SPCR
00572 #define CPOL_REG SPCR
00573 #define MSTR_REG SPCR
00574 #define DORD_REG SPCR
00575 #define SPE_REG SPCR
00576 #define SPIE_REG SPCR
00577
00578
00579 #define TOV1_REG TIFR1
00580 #define OCF1A_REG TIFR1
00581 #define OCF1B_REG TIFR1
00582 #define ICF1_REG TIFR1
00583
00584
00585 #define PSRSYNC_REG GTCCR
00586 #define TSM_REG GTCCR
00587 #define PSRASY_REG GTCCR
00588
00589
00590 #define TWBR0_REG TWBR
00591 #define TWBR1_REG TWBR
00592 #define TWBR2_REG TWBR
00593 #define TWBR3_REG TWBR
00594 #define TWBR4_REG TWBR
00595 #define TWBR5_REG TWBR
00596 #define TWBR6_REG TWBR
00597 #define TWBR7_REG TWBR
00598
00599
00600 #define ICR1H0_REG ICR1H
00601 #define ICR1H1_REG ICR1H
00602 #define ICR1H2_REG ICR1H
00603 #define ICR1H3_REG ICR1H
00604 #define ICR1H4_REG ICR1H
00605 #define ICR1H5_REG ICR1H
00606 #define ICR1H6_REG ICR1H
00607 #define ICR1H7_REG ICR1H
00608
00609
00610 #define FOC3B_REG TCCR3C
00611 #define FOC3A_REG TCCR3C
00612
00613
00614 #define CS30_REG TCCR3B
00615 #define CS31_REG TCCR3B
00616 #define CS32_REG TCCR3B
00617 #define WGM32_REG TCCR3B
00618 #define WGM33_REG TCCR3B
00619 #define ICES3_REG TCCR3B
00620 #define ICNC3_REG TCCR3B
00621
00622
00623 #define WGM30_REG TCCR3A
00624 #define WGM31_REG TCCR3A
00625 #define COM3B0_REG TCCR3A
00626 #define COM3B1_REG TCCR3A
00627 #define COM3A0_REG TCCR3A
00628 #define COM3A1_REG TCCR3A
00629
00630
00631
00632
00633
00634
00635
00636
00637
00638
00639
00640
00641 #define TCNT3H0_REG TCNT3H
00642 #define TCNT3H1_REG TCNT3H
00643 #define TCNT3H2_REG TCNT3H
00644 #define TCNT3H3_REG TCNT3H
00645 #define TCNT3H4_REG TCNT3H
00646 #define TCNT3H5_REG TCNT3H
00647 #define TCNT3H6_REG TCNT3H
00648 #define TCNT3H7_REG TCNT3H
00649
00650
00651
00652
00653
00654
00655
00656
00657
00658
00659
00660
00661 #define TCNT3L0_REG TCNT3L
00662 #define TCNT3L1_REG TCNT3L
00663 #define TCNT3L2_REG TCNT3L
00664 #define TCNT3L3_REG TCNT3L
00665 #define TCNT3L4_REG TCNT3L
00666 #define TCNT3L5_REG TCNT3L
00667 #define TCNT3L6_REG TCNT3L
00668 #define TCNT3L7_REG TCNT3L
00669
00670
00671 #define SP0_REG SPL
00672 #define SP1_REG SPL
00673 #define SP2_REG SPL
00674 #define SP3_REG SPL
00675 #define SP4_REG SPL
00676 #define SP5_REG SPL
00677 #define SP6_REG SPL
00678 #define SP7_REG SPL
00679
00680
00681 #define JTRF_REG MCUSR
00682 #define PORF_REG MCUSR
00683 #define EXTRF_REG MCUSR
00684 #define BORF_REG MCUSR
00685 #define WDRF_REG MCUSR
00686
00687
00688 #define EERE_REG EECR
00689 #define EEPE_REG EECR
00690 #define EEMPE_REG EECR
00691 #define EERIE_REG EECR
00692 #define EEPM0_REG EECR
00693 #define EEPM1_REG EECR
00694
00695
00696 #define SE_REG SMCR
00697 #define SM0_REG SMCR
00698 #define SM1_REG SMCR
00699 #define SM2_REG SMCR
00700
00701
00702 #define TWIE_REG TWCR
00703 #define TWEN_REG TWCR
00704 #define TWWC_REG TWCR
00705 #define TWSTO_REG TWCR
00706 #define TWSTA_REG TWCR
00707 #define TWEA_REG TWCR
00708 #define TWINT_REG TWCR
00709
00710
00711 #define PCIF0_REG PCIFR
00712 #define PCIF1_REG PCIFR
00713 #define PCIF2_REG PCIFR
00714 #define PCIF3_REG PCIFR
00715
00716
00717 #define WGM20_REG TCCR2A
00718 #define WGM21_REG TCCR2A
00719 #define COM2B0_REG TCCR2A
00720 #define COM2B1_REG TCCR2A
00721 #define COM2A0_REG TCCR2A
00722 #define COM2A1_REG TCCR2A
00723
00724
00725 #define CS20_REG TCCR2B
00726 #define CS21_REG TCCR2B
00727 #define CS22_REG TCCR2B
00728 #define WGM22_REG TCCR2B
00729 #define FOC2B_REG TCCR2B
00730 #define FOC2A_REG TCCR2B
00731
00732
00733 #define UBRR8_REG UBRR0H
00734 #define UBRR9_REG UBRR0H
00735 #define UBRR10_REG UBRR0H
00736 #define UBRR11_REG UBRR0H
00737
00738
00739 #define UBRR0_REG UBRR0L
00740 #define UBRR1_REG UBRR0L
00741 #define UBRR2_REG UBRR0L
00742 #define UBRR3_REG UBRR0L
00743 #define UBRR4_REG UBRR0L
00744 #define UBRR5_REG UBRR0L
00745 #define UBRR6_REG UBRR0L
00746 #define UBRR7_REG UBRR0L
00747
00748
00749 #define TWPS0_REG TWSR
00750 #define TWPS1_REG TWSR
00751 #define TWS3_REG TWSR
00752 #define TWS4_REG TWSR
00753 #define TWS5_REG TWSR
00754 #define TWS6_REG TWSR
00755 #define TWS7_REG TWSR
00756
00757
00758 #define EEAR0_REG EEARL
00759 #define EEAR1_REG EEARL
00760 #define EEAR2_REG EEARL
00761 #define EEAR3_REG EEARL
00762 #define EEAR4_REG EEARL
00763 #define EEAR5_REG EEARL
00764 #define EEAR6_REG EEARL
00765 #define EEAR7_REG EEARL
00766
00767
00768 #define JTD_REG MCUCR
00769 #define IVCE_REG MCUCR
00770 #define IVSEL_REG MCUCR
00771 #define PUD_REG MCUCR
00772 #define BODSE_REG MCUCR
00773 #define BODS_REG MCUCR
00774
00775
00776 #define OCDR0_REG OCDR
00777 #define OCDR1_REG OCDR
00778 #define OCDR2_REG OCDR
00779 #define OCDR3_REG OCDR
00780 #define OCDR4_REG OCDR
00781 #define OCDR5_REG OCDR
00782 #define OCDR6_REG OCDR
00783 #define OCDR7_REG OCDR
00784
00785
00786 #define PINA0_REG PINA
00787 #define PINA1_REG PINA
00788 #define PINA2_REG PINA
00789 #define PINA3_REG PINA
00790 #define PINA4_REG PINA
00791 #define PINA5_REG PINA
00792 #define PINA6_REG PINA
00793 #define PINA7_REG PINA
00794
00795
00796 #define TXB81_REG UCSR1B
00797 #define RXB81_REG UCSR1B
00798 #define UCSZ12_REG UCSR1B
00799 #define TXEN1_REG UCSR1B
00800 #define RXEN1_REG UCSR1B
00801 #define UDRIE1_REG UCSR1B
00802 #define TXCIE1_REG UCSR1B
00803 #define RXCIE1_REG UCSR1B
00804
00805
00806 #define UCPOL1_REG UCSR1C
00807 #define UCSZ10_REG UCSR1C
00808 #define UCSZ11_REG UCSR1C
00809 #define USBS1_REG UCSR1C
00810 #define UPM10_REG UCSR1C
00811 #define UPM11_REG UCSR1C
00812 #define UMSEL10_REG UCSR1C
00813 #define UMSEL11_REG UCSR1C
00814
00815
00816 #define MPCM1_REG UCSR1A
00817 #define U2X1_REG UCSR1A
00818 #define UPE1_REG UCSR1A
00819 #define DOR1_REG UCSR1A
00820 #define FE1_REG UCSR1A
00821 #define UDRE1_REG UCSR1A
00822 #define TXC1_REG UCSR1A
00823 #define RXC1_REG UCSR1A
00824
00825
00826 #define DDB0_REG DDRB
00827 #define DDB1_REG DDRB
00828 #define DDB2_REG DDRB
00829 #define DDB3_REG DDRB
00830 #define DDB4_REG DDRB
00831 #define DDB5_REG DDRB
00832 #define DDB6_REG DDRB
00833 #define DDB7_REG DDRB
00834
00835
00836 #define TWD0_REG TWDR
00837 #define TWD1_REG TWDR
00838 #define TWD2_REG TWDR
00839 #define TWD3_REG TWDR
00840 #define TWD4_REG TWDR
00841 #define TWD5_REG TWDR
00842 #define TWD6_REG TWDR
00843 #define TWD7_REG TWDR
00844
00845
00846 #define TWAM0_REG TWAMR
00847 #define TWAM1_REG TWAMR
00848 #define TWAM2_REG TWAMR
00849 #define TWAM3_REG TWAMR
00850 #define TWAM4_REG TWAMR
00851 #define TWAM5_REG TWAMR
00852 #define TWAM6_REG TWAMR
00853
00854
00855 #define ADPS0_REG ADCSRA
00856 #define ADPS1_REG ADCSRA
00857 #define ADPS2_REG ADCSRA
00858 #define ADIE_REG ADCSRA
00859 #define ADIF_REG ADCSRA
00860 #define ADATE_REG ADCSRA
00861 #define ADSC_REG ADCSRA
00862 #define ADEN_REG ADCSRA
00863
00864
00865 #define ACME_REG ADCSRB
00866 #define ADTS0_REG ADCSRB
00867 #define ADTS1_REG ADCSRB
00868 #define ADTS2_REG ADCSRB
00869
00870
00871 #define PRADC_REG PRR0
00872 #define PRUSART0_REG PRR0
00873 #define PRSPI_REG PRR0
00874 #define PRTIM1_REG PRR0
00875 #define PRUSART1_REG PRR0
00876 #define PRTIM0_REG PRR0
00877 #define PRTIM2_REG PRR0
00878 #define PRTWI_REG PRR0
00879
00880
00881 #define WGM10_REG TCCR1A
00882 #define WGM11_REG TCCR1A
00883 #define COM1B0_REG TCCR1A
00884 #define COM1B1_REG TCCR1A
00885 #define COM1A0_REG TCCR1A
00886 #define COM1A1_REG TCCR1A
00887
00888
00889 #define OCROA_0_REG OCR0A
00890 #define OCROA_1_REG OCR0A
00891 #define OCROA_2_REG OCR0A
00892 #define OCROA_3_REG OCR0A
00893 #define OCROA_4_REG OCR0A
00894 #define OCROA_5_REG OCR0A
00895 #define OCROA_6_REG OCR0A
00896 #define OCROA_7_REG OCR0A
00897
00898
00899 #define OCR0B_0_REG OCR0B
00900 #define OCR0B_1_REG OCR0B
00901 #define OCR0B_2_REG OCR0B
00902 #define OCR0B_3_REG OCR0B
00903 #define OCR0B_4_REG OCR0B
00904 #define OCR0B_5_REG OCR0B
00905 #define OCR0B_6_REG OCR0B
00906 #define OCR0B_7_REG OCR0B
00907
00908
00909 #define TCNT1L0_REG TCNT1L
00910 #define TCNT1L1_REG TCNT1L
00911 #define TCNT1L2_REG TCNT1L
00912 #define TCNT1L3_REG TCNT1L
00913 #define TCNT1L4_REG TCNT1L
00914 #define TCNT1L5_REG TCNT1L
00915 #define TCNT1L6_REG TCNT1L
00916 #define TCNT1L7_REG TCNT1L
00917
00918
00919 #define FOC1B_REG TCCR1C
00920 #define FOC1A_REG TCCR1C
00921
00922
00923 #define ICR3H0_REG ICR3H
00924 #define ICR3H1_REG ICR3H
00925 #define ICR3H2_REG ICR3H
00926 #define ICR3H3_REG ICR3H
00927 #define ICR3H4_REG ICR3H
00928 #define ICR3H5_REG ICR3H
00929 #define ICR3H6_REG ICR3H
00930 #define ICR3H7_REG ICR3H
00931
00932
00933 #define PORTD0_REG PORTD
00934 #define PORTD1_REG PORTD
00935 #define PORTD2_REG PORTD
00936 #define PORTD3_REG PORTD
00937 #define PORTD4_REG PORTD
00938 #define PORTD5_REG PORTD
00939 #define PORTD6_REG PORTD
00940 #define PORTD7_REG PORTD
00941
00942
00943 #define ICR3L0_REG ICR3L
00944 #define ICR3L1_REG ICR3L
00945 #define ICR3L2_REG ICR3L
00946 #define ICR3L3_REG ICR3L
00947 #define ICR3L4_REG ICR3L
00948 #define ICR3L5_REG ICR3L
00949 #define ICR3L6_REG ICR3L
00950 #define ICR3L7_REG ICR3L
00951
00952
00953 #define SPMEN_REG SPMCSR
00954 #define PGERS_REG SPMCSR
00955 #define PGWRT_REG SPMCSR
00956 #define BLBSET_REG SPMCSR
00957 #define RWWSRE_REG SPMCSR
00958 #define SIGRD_REG SPMCSR
00959 #define RWWSB_REG SPMCSR
00960 #define SPMIE_REG SPMCSR
00961
00962
00963 #define PORTB0_REG PORTB
00964 #define PORTB1_REG PORTB
00965 #define PORTB2_REG PORTB
00966 #define PORTB3_REG PORTB
00967 #define PORTB4_REG PORTB
00968 #define PORTB5_REG PORTB
00969 #define PORTB6_REG PORTB
00970 #define PORTB7_REG PORTB
00971
00972
00973 #define ADCL0_REG ADCL
00974 #define ADCL1_REG ADCL
00975 #define ADCL2_REG ADCL
00976 #define ADCL3_REG ADCL
00977 #define ADCL4_REG ADCL
00978 #define ADCL5_REG ADCL
00979 #define ADCL6_REG ADCL
00980 #define ADCL7_REG ADCL
00981
00982
00983 #define ADCH0_REG ADCH
00984 #define ADCH1_REG ADCH
00985 #define ADCH2_REG ADCH
00986 #define ADCH3_REG ADCH
00987 #define ADCH4_REG ADCH
00988 #define ADCH5_REG ADCH
00989 #define ADCH6_REG ADCH
00990 #define ADCH7_REG ADCH
00991
00992
00993
00994
00995
00996
00997
00998
00999
01000
01001
01002
01003
01004
01005
01006
01007
01008
01009
01010
01011
01012
01013 #define TOIE2_REG TIMSK2
01014 #define OCIE2A_REG TIMSK2
01015 #define OCIE2B_REG TIMSK2
01016
01017
01018 #define TOIE3_REG TIMSK3
01019 #define OCIE3A_REG TIMSK3
01020 #define OCIE3B_REG TIMSK3
01021 #define ICIE3_REG TIMSK3
01022
01023
01024 #define TOIE0_REG TIMSK0
01025 #define OCIE0A_REG TIMSK0
01026 #define OCIE0B_REG TIMSK0
01027
01028
01029 #define TOIE1_REG TIMSK1
01030 #define OCIE1A_REG TIMSK1
01031 #define OCIE1B_REG TIMSK1
01032 #define ICIE1_REG TIMSK1
01033
01034
01035 #define PCINT0_REG PCMSK0
01036 #define PCINT1_REG PCMSK0
01037 #define PCINT2_REG PCMSK0
01038 #define PCINT3_REG PCMSK0
01039 #define PCINT4_REG PCMSK0
01040 #define PCINT5_REG PCMSK0
01041 #define PCINT6_REG PCMSK0
01042 #define PCINT7_REG PCMSK0
01043
01044
01045 #define PCINT8_REG PCMSK1
01046 #define PCINT9_REG PCMSK1
01047 #define PCINT10_REG PCMSK1
01048 #define PCINT11_REG PCMSK1
01049 #define PCINT12_REG PCMSK1
01050 #define PCINT13_REG PCMSK1
01051 #define PCINT14_REG PCMSK1
01052 #define PCINT15_REG PCMSK1
01053
01054
01055 #define PCINT16_REG PCMSK2
01056 #define PCINT17_REG PCMSK2
01057 #define PCINT18_REG PCMSK2
01058 #define PCINT19_REG PCMSK2
01059 #define PCINT20_REG PCMSK2
01060 #define PCINT21_REG PCMSK2
01061 #define PCINT22_REG PCMSK2
01062 #define PCINT23_REG PCMSK2
01063
01064
01065 #define PCINT24_REG PCMSK3
01066 #define PCINT25_REG PCMSK3
01067 #define PCINT26_REG PCMSK3
01068 #define PCINT27_REG PCMSK3
01069 #define PCINT28_REG PCMSK3
01070 #define PCINT29_REG PCMSK3
01071 #define PCINT30_REG PCMSK3
01072 #define PCINT31_REG PCMSK3
01073
01074
01075 #define PINC0_REG PINC
01076 #define PINC1_REG PINC
01077 #define PINC2_REG PINC
01078 #define PINC3_REG PINC
01079 #define PINC4_REG PINC
01080 #define PINC5_REG PINC
01081 #define PINC6_REG PINC
01082 #define PINC7_REG PINC
01083
01084
01085 #define PINB0_REG PINB
01086 #define PINB1_REG PINB
01087 #define PINB2_REG PINB
01088 #define PINB3_REG PINB
01089 #define PINB4_REG PINB
01090 #define PINB5_REG PINB
01091 #define PINB6_REG PINB
01092 #define PINB7_REG PINB
01093
01094
01095 #define INTF0_REG EIFR
01096 #define INTF1_REG EIFR
01097 #define INTF2_REG EIFR
01098
01099
01100 #define PIND0_REG PIND
01101 #define PIND1_REG PIND
01102 #define PIND2_REG PIND
01103 #define PIND3_REG PIND
01104 #define PIND4_REG PIND
01105 #define PIND5_REG PIND
01106 #define PIND6_REG PIND
01107 #define PIND7_REG PIND
01108
01109
01110
01111
01112
01113
01114
01115
01116
01117
01118
01119
01120
01121
01122
01123
01124
01125
01126
01127
01128
01129
01130 #define TOV0_REG TIFR0
01131 #define OCF0A_REG TIFR0
01132 #define OCF0B_REG TIFR0
01133
01134
01135 #define PRTIM3_REG PRR1
01136
01137
01138 #define ADC0_PORT PORTA
01139 #define ADC0_BIT 0
01140 #define PCINT0_PORT PORTA
01141 #define PCINT0_BIT 0
01142
01143 #define ADC1_PORT PORTA
01144 #define ADC1_BIT 1
01145 #define PCINT1_PORT PORTA
01146 #define PCINT1_BIT 1
01147
01148 #define ADC2_PORT PORTA
01149 #define ADC2_BIT 2
01150 #define PCINT2_PORT PORTA
01151 #define PCINT2_BIT 2
01152
01153 #define ADC3_PORT PORTA
01154 #define ADC3_BIT 3
01155 #define PCINT3_PORT PORTA
01156 #define PCINT3_BIT 3
01157
01158 #define ADC4_PORT PORTA
01159 #define ADC4_BIT 4
01160 #define PCINT4_PORT PORTA
01161 #define PCINT4_BIT 4
01162
01163 #define ADC5_PORT PORTA
01164 #define ADC5_BIT 5
01165 #define PCINT5_PORT PORTA
01166 #define PCINT5_BIT 5
01167
01168 #define ADC6_PORT PORTA
01169 #define ADC6_BIT 6
01170 #define PCINT6_PORT PORTA
01171 #define PCINT6_BIT 6
01172
01173 #define ADC7_PORT PORTA
01174 #define ADC7_BIT 7
01175 #define PCINT7_PORT PORTA
01176 #define PCINT7_BIT 7
01177
01178 #define XCK_PORT PORTB
01179 #define XCK_BIT 0
01180 #define T0_PORT PORTB
01181 #define T0_BIT 0
01182 #define PCINT9_PORT PORTB
01183 #define PCINT9_BIT 0
01184
01185 #define T1_PORT PORTB
01186 #define T1_BIT 1
01187 #define CLKO_PORT PORTB
01188 #define CLKO_BIT 1
01189 #define PCINT9_PORT PORTB
01190 #define PCINT9_BIT 1
01191
01192 #define AIN0_PORT PORTB
01193 #define AIN0_BIT 2
01194 #define INT2_PORT PORTB
01195 #define INT2_BIT 2
01196 #define PCINT10_PORT PORTB
01197 #define PCINT10_BIT 2
01198
01199 #define AIN1_PORT PORTB
01200 #define AIN1_BIT 3
01201 #define OC0A_PORT PORTB
01202 #define OC0A_BIT 3
01203 #define PCINT11_PORT PORTB
01204 #define PCINT11_BIT 3
01205
01206 #define SS_PORT PORTB
01207 #define SS_BIT 4
01208 #define OC0B_PORT PORTB
01209 #define OC0B_BIT 4
01210 #define PCINT12_PORT PORTB
01211 #define PCINT12_BIT 4
01212
01213 #define MOSI_PORT PORTB
01214 #define MOSI_BIT 5
01215 #define PCINT13_PORT PORTB
01216 #define PCINT13_BIT 5
01217
01218 #define MISO_PORT PORTB
01219 #define MISO_BIT 6
01220 #define PCINT14_PORT PORTB
01221 #define PCINT14_BIT 6
01222
01223 #define SCK_PORT PORTB
01224 #define SCK_BIT 7
01225 #define PCINT15_PORT PORTB
01226 #define PCINT15_BIT 7
01227
01228 #define SCL_PORT PORTC
01229 #define SCL_BIT 0
01230 #define PCINT16_PORT PORTC
01231 #define PCINT16_BIT 0
01232
01233 #define SDA_PORT PORTC
01234 #define SDA_BIT 1
01235 #define PCINT17_PORT PORTC
01236 #define PCINT17_BIT 1
01237
01238 #define TCK_PORT PORTC
01239 #define TCK_BIT 2
01240 #define PCINT18_PORT PORTC
01241 #define PCINT18_BIT 2
01242
01243 #define TMS_PORT PORTC
01244 #define TMS_BIT 3
01245 #define PCINT19_PORT PORTC
01246 #define PCINT19_BIT 3
01247
01248 #define TDO_PORT PORTC
01249 #define TDO_BIT 4
01250 #define PCINT20_PORT PORTC
01251 #define PCINT20_BIT 4
01252
01253 #define TDI_PORT PORTC
01254 #define TDI_BIT 5
01255 #define PCINT21_PORT PORTC
01256 #define PCINT21_BIT 5
01257
01258 #define TOSC1_PORT PORTC
01259 #define TOSC1_BIT 6
01260 #define PCINT22_PORT PORTC
01261 #define PCINT22_BIT 6
01262
01263 #define TOSC2_PORT PORTC
01264 #define TOSC2_BIT 7
01265 #define PCINT23_PORT PORTC
01266 #define PCINT23_BIT 7
01267
01268 #define RXD_PORT PORTD
01269 #define RXD_BIT 0
01270 #define PCINT24_PORT PORTD
01271 #define PCINT24_BIT 0
01272
01273 #define TXD_PORT PORTD
01274 #define TXD_BIT 1
01275 #define PCINT25_PORT PORTD
01276 #define PCINT25_BIT 1
01277
01278 #define INT0_PORT PORTD
01279 #define INT0_BIT 2
01280 #define RDX1_PORT PORTD
01281 #define RDX1_BIT 2
01282 #define PCINT26_PORT PORTD
01283 #define PCINT26_BIT 2
01284
01285 #define INT1_PORT PORTD
01286 #define INT1_BIT 3
01287 #define TXD1_PORT PORTD
01288 #define TXD1_BIT 3
01289 #define PCINT27_PORT PORTD
01290 #define PCINT27_BIT 3
01291
01292 #define OC1B_PORT PORTD
01293 #define OC1B_BIT 4
01294 #define XCK1_PORT PORTD
01295 #define XCK1_BIT 4
01296 #define PCINT28_PORT PORTD
01297 #define PCINT28_BIT 4
01298
01299 #define OC1A_PORT PORTD
01300 #define OC1A_BIT 5
01301 #define PCINT29_PORT PORTD
01302 #define PCINT29_BIT 5
01303
01304 #define ICP_PORT PORTD
01305 #define ICP_BIT 6
01306 #define OC2B_PORT PORTD
01307 #define OC2B_BIT 6
01308 #define PCINT30_PORT PORTD
01309 #define PCINT30_BIT 6
01310
01311 #define OC2A_PORT PORTD
01312 #define OC2A_BIT 7
01313 #define PCINT31_PORT PORTD
01314 #define PCINT31_BIT 7
01315
01316