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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_FALL 6
00092 #define TIMER3_PRESCALER_DIV_RISE 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 -1
00101 #define TIMER3_PRESCALER_REG_7 -2
00102
00103
00104 #define TIMER4_PRESCALER_DIV_0 0
00105 #define TIMER4_PRESCALER_DIV_1 1
00106 #define TIMER4_PRESCALER_DIV_8 2
00107 #define TIMER4_PRESCALER_DIV_64 3
00108 #define TIMER4_PRESCALER_DIV_256 4
00109 #define TIMER4_PRESCALER_DIV_1024 5
00110 #define TIMER4_PRESCALER_DIV_FALL 6
00111 #define TIMER4_PRESCALER_DIV_RISE 7
00112
00113 #define TIMER4_PRESCALER_REG_0 0
00114 #define TIMER4_PRESCALER_REG_1 1
00115 #define TIMER4_PRESCALER_REG_2 8
00116 #define TIMER4_PRESCALER_REG_3 64
00117 #define TIMER4_PRESCALER_REG_4 256
00118 #define TIMER4_PRESCALER_REG_5 1024
00119 #define TIMER4_PRESCALER_REG_6 -1
00120 #define TIMER4_PRESCALER_REG_7 -2
00121
00122
00123 #define TIMER5_PRESCALER_DIV_0 0
00124 #define TIMER5_PRESCALER_DIV_1 1
00125 #define TIMER5_PRESCALER_DIV_8 2
00126 #define TIMER5_PRESCALER_DIV_64 3
00127 #define TIMER5_PRESCALER_DIV_256 4
00128 #define TIMER5_PRESCALER_DIV_1024 5
00129 #define TIMER5_PRESCALER_DIV_FALL 6
00130 #define TIMER5_PRESCALER_DIV_RISE 7
00131
00132 #define TIMER5_PRESCALER_REG_0 0
00133 #define TIMER5_PRESCALER_REG_1 1
00134 #define TIMER5_PRESCALER_REG_2 8
00135 #define TIMER5_PRESCALER_REG_3 64
00136 #define TIMER5_PRESCALER_REG_4 256
00137 #define TIMER5_PRESCALER_REG_5 1024
00138 #define TIMER5_PRESCALER_REG_6 -1
00139 #define TIMER5_PRESCALER_REG_7 -2
00140
00141
00142
00143 #define TIMER0_AVAILABLE
00144 #define TIMER0A_AVAILABLE
00145 #define TIMER0B_AVAILABLE
00146 #define TIMER1_AVAILABLE
00147 #define TIMER1A_AVAILABLE
00148 #define TIMER1B_AVAILABLE
00149 #define TIMER1C_AVAILABLE
00150 #define TIMER2_AVAILABLE
00151 #define TIMER2A_AVAILABLE
00152 #define TIMER2B_AVAILABLE
00153 #define TIMER3_AVAILABLE
00154 #define TIMER3A_AVAILABLE
00155 #define TIMER3B_AVAILABLE
00156 #define TIMER3C_AVAILABLE
00157 #define TIMER4_AVAILABLE
00158 #define TIMER4A_AVAILABLE
00159 #define TIMER4B_AVAILABLE
00160 #define TIMER4C_AVAILABLE
00161 #define TIMER5_AVAILABLE
00162 #define TIMER5A_AVAILABLE
00163 #define TIMER5B_AVAILABLE
00164 #define TIMER5C_AVAILABLE
00165
00166
00167 #define SIG_OVERFLOW0_NUM 0
00168 #define SIG_OVERFLOW1_NUM 1
00169 #define SIG_OVERFLOW2_NUM 2
00170 #define SIG_OVERFLOW3_NUM 3
00171 #define SIG_OVERFLOW4_NUM 4
00172 #define SIG_OVERFLOW5_NUM 5
00173 #define SIG_OVERFLOW_TOTAL_NUM 6
00174
00175
00176 #define SIG_OUTPUT_COMPARE0A_NUM 0
00177 #define SIG_OUTPUT_COMPARE0B_NUM 1
00178 #define SIG_OUTPUT_COMPARE1A_NUM 2
00179 #define SIG_OUTPUT_COMPARE1B_NUM 3
00180 #define SIG_OUTPUT_COMPARE1C_NUM 4
00181 #define SIG_OUTPUT_COMPARE2A_NUM 5
00182 #define SIG_OUTPUT_COMPARE2B_NUM 6
00183 #define SIG_OUTPUT_COMPARE3A_NUM 7
00184 #define SIG_OUTPUT_COMPARE3B_NUM 8
00185 #define SIG_OUTPUT_COMPARE3C_NUM 9
00186 #define SIG_OUTPUT_COMPARE4A_NUM 10
00187 #define SIG_OUTPUT_COMPARE4B_NUM 11
00188 #define SIG_OUTPUT_COMPARE4C_NUM 12
00189 #define SIG_OUTPUT_COMPARE5A_NUM 13
00190 #define SIG_OUTPUT_COMPARE5B_NUM 14
00191 #define SIG_OUTPUT_COMPARE5C_NUM 15
00192 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 16
00193
00194
00195 #define PWM0A_NUM 0
00196 #define PWM0B_NUM 1
00197 #define PWM1A_NUM 2
00198 #define PWM1B_NUM 3
00199 #define PWM1C_NUM 4
00200 #define PWM2A_NUM 5
00201 #define PWM2B_NUM 6
00202 #define PWM3A_NUM 7
00203 #define PWM3B_NUM 8
00204 #define PWM3C_NUM 9
00205 #define PWM4A_NUM 10
00206 #define PWM4B_NUM 11
00207 #define PWM4C_NUM 12
00208 #define PWM5A_NUM 13
00209 #define PWM5B_NUM 14
00210 #define PWM5C_NUM 15
00211 #define PWM_TOTAL_NUM 16
00212
00213
00214 #define SIG_INPUT_CAPTURE1_NUM 0
00215 #define SIG_INPUT_CAPTURE3_NUM 1
00216 #define SIG_INPUT_CAPTURE4_NUM 2
00217 #define SIG_INPUT_CAPTURE5_NUM 3
00218 #define SIG_INPUT_CAPTURE_TOTAL_NUM 4
00219
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00223
00224
00225
00226
00227
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00237
00238 #define OCROA_0_REG OCR0A
00239 #define OCROA_1_REG OCR0A
00240 #define OCROA_2_REG OCR0A
00241 #define OCROA_3_REG OCR0A
00242 #define OCROA_4_REG OCR0A
00243 #define OCROA_5_REG OCR0A
00244 #define OCROA_6_REG OCR0A
00245 #define OCROA_7_REG OCR0A
00246
00247
00248 #define MUX0_REG ADMUX
00249 #define MUX1_REG ADMUX
00250 #define MUX2_REG ADMUX
00251 #define MUX3_REG ADMUX
00252 #define MUX4_REG ADMUX
00253 #define ADLAR_REG ADMUX
00254 #define REFS0_REG ADMUX
00255 #define REFS1_REG ADMUX
00256
00257
00258 #define MPCM3_REG UCSR3A
00259 #define U2X3_REG UCSR3A
00260 #define UPE3_REG UCSR3A
00261 #define DOR3_REG UCSR3A
00262 #define FE3_REG UCSR3A
00263 #define UDRE3_REG UCSR3A
00264 #define TXC3_REG UCSR3A
00265 #define RXC3_REG UCSR3A
00266
00267
00268 #define TXB83_REG UCSR3B
00269 #define RXB83_REG UCSR3B
00270 #define UCSZ32_REG UCSR3B
00271 #define TXEN3_REG UCSR3B
00272 #define RXEN3_REG UCSR3B
00273 #define UDRIE3_REG UCSR3B
00274 #define TXCIE3_REG UCSR3B
00275 #define RXCIE3_REG UCSR3B
00276
00277
00278 #define UCPOL3_REG UCSR3C
00279 #define UCSZ30_REG UCSR3C
00280 #define UCSZ31_REG UCSR3C
00281 #define USBS3_REG UCSR3C
00282 #define UPM30_REG UCSR3C
00283 #define UPM31_REG UCSR3C
00284 #define UMSEL30_REG UCSR3C
00285 #define UMSEL31_REG UCSR3C
00286
00287
00288 #define EEDR0_REG EEDR
00289 #define EEDR1_REG EEDR
00290 #define EEDR2_REG EEDR
00291 #define EEDR3_REG EEDR
00292 #define EEDR4_REG EEDR
00293 #define EEDR5_REG EEDR
00294 #define EEDR6_REG EEDR
00295 #define EEDR7_REG EEDR
00296
00297
00298 #define ACIS0_REG ACSR
00299 #define ACIS1_REG ACSR
00300 #define ACIC_REG ACSR
00301 #define ACIE_REG ACSR
00302 #define ACI_REG ACSR
00303 #define ACO_REG ACSR
00304 #define ACBG_REG ACSR
00305 #define ACD_REG ACSR
00306
00307
00308 #define RAMPZ0_REG RAMPZ
00309 #define RAMPZ1_REG RAMPZ
00310
00311
00312 #define OCR2B_0_REG OCR2B
00313 #define OCR2B_1_REG OCR2B
00314 #define OCR2B_2_REG OCR2B
00315 #define OCR2B_3_REG OCR2B
00316 #define OCR2B_4_REG OCR2B
00317 #define OCR2B_5_REG OCR2B
00318 #define OCR2B_6_REG OCR2B
00319 #define OCR2B_7_REG OCR2B
00320
00321
00322 #define OCR2A_0_REG OCR2A
00323 #define OCR2A_1_REG OCR2A
00324 #define OCR2A_2_REG OCR2A
00325 #define OCR2A_3_REG OCR2A
00326 #define OCR2A_4_REG OCR2A
00327 #define OCR2A_5_REG OCR2A
00328 #define OCR2A_6_REG OCR2A
00329 #define OCR2A_7_REG OCR2A
00330
00331
00332 #define SPDR0_REG SPDR
00333 #define SPDR1_REG SPDR
00334 #define SPDR2_REG SPDR
00335 #define SPDR3_REG SPDR
00336 #define SPDR4_REG SPDR
00337 #define SPDR5_REG SPDR
00338 #define SPDR6_REG SPDR
00339 #define SPDR7_REG SPDR
00340
00341
00342 #define SPI2X_REG SPSR
00343 #define WCOL_REG SPSR
00344 #define SPIF_REG SPSR
00345
00346
00347 #define ICR1H0_REG ICR1H
00348 #define ICR1H1_REG ICR1H
00349 #define ICR1H2_REG ICR1H
00350 #define ICR1H3_REG ICR1H
00351 #define ICR1H4_REG ICR1H
00352 #define ICR1H5_REG ICR1H
00353 #define ICR1H6_REG ICR1H
00354 #define ICR1H7_REG ICR1H
00355
00356
00357 #define ICR1L0_REG ICR1L
00358 #define ICR1L1_REG ICR1L
00359 #define ICR1L2_REG ICR1L
00360 #define ICR1L3_REG ICR1L
00361 #define ICR1L4_REG ICR1L
00362 #define ICR1L5_REG ICR1L
00363 #define ICR1L6_REG ICR1L
00364 #define ICR1L7_REG ICR1L
00365
00366
00367 #define EEAR8_REG EEARH
00368 #define EEAR9_REG EEARH
00369 #define EEAR10_REG EEARH
00370 #define EEAR11_REG EEARH
00371
00372
00373 #define PORTL0_REG PORTL
00374 #define PORTL1_REG PORTL
00375 #define PORTL2_REG PORTL
00376 #define PORTL3_REG PORTL
00377 #define PORTL4_REG PORTL
00378 #define PORTL5_REG PORTL
00379 #define PORTL6_REG PORTL
00380 #define PORTL7_REG PORTL
00381
00382
00383 #define PORTJ0_REG PORTJ
00384 #define PORTJ1_REG PORTJ
00385 #define PORTJ2_REG PORTJ
00386 #define PORTJ3_REG PORTJ
00387 #define PORTJ4_REG PORTJ
00388 #define PORTJ5_REG PORTJ
00389 #define PORTJ6_REG PORTJ
00390 #define PORTJ7_REG PORTJ
00391
00392
00393 #define PORTK0_REG PORTK
00394 #define PORTK1_REG PORTK
00395 #define PORTK2_REG PORTK
00396 #define PORTK3_REG PORTK
00397 #define PORTK4_REG PORTK
00398 #define PORTK5_REG PORTK
00399 #define PORTK6_REG PORTK
00400 #define PORTK7_REG PORTK
00401
00402
00403 #define PORTH0_REG PORTH
00404 #define PORTH1_REG PORTH
00405 #define PORTH2_REG PORTH
00406 #define PORTH3_REG PORTH
00407 #define PORTH4_REG PORTH
00408 #define PORTH5_REG PORTH
00409 #define PORTH6_REG PORTH
00410 #define PORTH7_REG PORTH
00411
00412
00413 #define MPCM0_REG UCSR0A
00414 #define U2X0_REG UCSR0A
00415 #define UPE0_REG UCSR0A
00416 #define DOR0_REG UCSR0A
00417 #define FE0_REG UCSR0A
00418 #define UDRE0_REG UCSR0A
00419 #define TXC0_REG UCSR0A
00420 #define RXC0_REG UCSR0A
00421
00422
00423 #define PORTG0_REG PORTG
00424 #define PORTG1_REG PORTG
00425 #define PORTG2_REG PORTG
00426 #define PORTG3_REG PORTG
00427 #define PORTG4_REG PORTG
00428 #define PORTG5_REG PORTG
00429
00430
00431 #define UCPOL0_REG UCSR0C
00432 #define UCSZ00_REG UCSR0C
00433 #define UCSZ01_REG UCSR0C
00434 #define USBS0_REG UCSR0C
00435 #define UPM00_REG UCSR0C
00436 #define UPM01_REG UCSR0C
00437 #define UMSEL00_REG UCSR0C
00438 #define UMSEL01_REG UCSR0C
00439
00440
00441 #define TXB80_REG UCSR0B
00442 #define RXB80_REG UCSR0B
00443 #define UCSZ02_REG UCSR0B
00444 #define TXEN0_REG UCSR0B
00445 #define RXEN0_REG UCSR0B
00446 #define UDRIE0_REG UCSR0B
00447 #define TXCIE0_REG UCSR0B
00448 #define RXCIE0_REG UCSR0B
00449
00450
00451 #define TCNT1H0_REG TCNT1H
00452 #define TCNT1H1_REG TCNT1H
00453 #define TCNT1H2_REG TCNT1H
00454 #define TCNT1H3_REG TCNT1H
00455 #define TCNT1H4_REG TCNT1H
00456 #define TCNT1H5_REG TCNT1H
00457 #define TCNT1H6_REG TCNT1H
00458 #define TCNT1H7_REG TCNT1H
00459
00460
00461 #define PORTC0_REG PORTC
00462 #define PORTC1_REG PORTC
00463 #define PORTC2_REG PORTC
00464 #define PORTC3_REG PORTC
00465 #define PORTC4_REG PORTC
00466 #define PORTC5_REG PORTC
00467 #define PORTC6_REG PORTC
00468 #define PORTC7_REG PORTC
00469
00470
00471 #define PORTA0_REG PORTA
00472 #define PORTA1_REG PORTA
00473 #define PORTA2_REG PORTA
00474 #define PORTA3_REG PORTA
00475 #define PORTA4_REG PORTA
00476 #define PORTA5_REG PORTA
00477 #define PORTA6_REG PORTA
00478 #define PORTA7_REG PORTA
00479
00480
00481 #define GPIOR10_REG GPIOR1
00482 #define GPIOR11_REG GPIOR1
00483 #define GPIOR12_REG GPIOR1
00484 #define GPIOR13_REG GPIOR1
00485 #define GPIOR14_REG GPIOR1
00486 #define GPIOR15_REG GPIOR1
00487 #define GPIOR16_REG GPIOR1
00488 #define GPIOR17_REG GPIOR1
00489
00490
00491 #define INT0_REG EIMSK
00492 #define INT1_REG EIMSK
00493 #define INT2_REG EIMSK
00494 #define INT3_REG EIMSK
00495 #define INT4_REG EIMSK
00496 #define INT5_REG EIMSK
00497 #define INT6_REG EIMSK
00498 #define INT7_REG EIMSK
00499
00500
00501 #define UDR1_0_REG UDR1
00502 #define UDR1_1_REG UDR1
00503 #define UDR1_2_REG UDR1
00504 #define UDR1_3_REG UDR1
00505 #define UDR1_4_REG UDR1
00506 #define UDR1_5_REG UDR1
00507 #define UDR1_6_REG UDR1
00508 #define UDR1_7_REG UDR1
00509
00510
00511 #define UDR0_0_REG UDR0
00512 #define UDR0_1_REG UDR0
00513 #define UDR0_2_REG UDR0
00514 #define UDR0_3_REG UDR0
00515 #define UDR0_4_REG UDR0
00516 #define UDR0_5_REG UDR0
00517 #define UDR0_6_REG UDR0
00518 #define UDR0_7_REG UDR0
00519
00520
00521 #define UDR3_0_REG UDR3
00522 #define UDR3_1_REG UDR3
00523 #define UDR3_2_REG UDR3
00524 #define UDR3_3_REG UDR3
00525 #define UDR3_4_REG UDR3
00526 #define UDR3_5_REG UDR3
00527 #define UDR3_6_REG UDR3
00528 #define UDR3_7_REG UDR3
00529
00530
00531 #define UDR2_0_REG UDR2
00532 #define UDR2_1_REG UDR2
00533 #define UDR2_2_REG UDR2
00534 #define UDR2_3_REG UDR2
00535 #define UDR2_4_REG UDR2
00536 #define UDR2_5_REG UDR2
00537 #define UDR2_6_REG UDR2
00538 #define UDR2_7_REG UDR2
00539
00540
00541 #define ISC40_REG EICRB
00542 #define ISC41_REG EICRB
00543 #define ISC50_REG EICRB
00544 #define ISC51_REG EICRB
00545 #define ISC60_REG EICRB
00546 #define ISC61_REG EICRB
00547 #define ISC70_REG EICRB
00548 #define ISC71_REG EICRB
00549
00550
00551 #define ISC00_REG EICRA
00552 #define ISC01_REG EICRA
00553 #define ISC10_REG EICRA
00554 #define ISC11_REG EICRA
00555 #define ISC20_REG EICRA
00556 #define ISC21_REG EICRA
00557 #define ISC30_REG EICRA
00558 #define ISC31_REG EICRA
00559
00560
00561 #define ADC0D_REG DIDR0
00562 #define ADC1D_REG DIDR0
00563 #define ADC2D_REG DIDR0
00564 #define ADC3D_REG DIDR0
00565 #define ADC4D_REG DIDR0
00566 #define ADC5D_REG DIDR0
00567 #define ADC6D_REG DIDR0
00568 #define ADC7D_REG DIDR0
00569
00570
00571 #define AIN0D_REG DIDR1
00572 #define AIN1D_REG DIDR1
00573
00574
00575 #define ADC8D_REG DIDR2
00576 #define ADC9D_REG DIDR2
00577 #define ADC10D_REG DIDR2
00578 #define ADC11D_REG DIDR2
00579 #define ADC12D_REG DIDR2
00580 #define ADC13D_REG DIDR2
00581 #define ADC14D_REG DIDR2
00582 #define ADC15D_REG DIDR2
00583
00584
00585 #define DDF0_REG DDRF
00586 #define DDF1_REG DDRF
00587 #define DDF2_REG DDRF
00588 #define DDF3_REG DDRF
00589 #define DDF4_REG DDRF
00590 #define DDF5_REG DDRF
00591 #define DDF6_REG DDRF
00592 #define DDF7_REG DDRF
00593
00594
00595 #define TCR2BUB_REG ASSR
00596 #define TCR2AUB_REG ASSR
00597 #define OCR2BUB_REG ASSR
00598 #define OCR2AUB_REG ASSR
00599 #define TCN2UB_REG ASSR
00600 #define AS2_REG ASSR
00601 #define EXCLK_REG ASSR
00602
00603
00604 #define CLKPS0_REG CLKPR
00605 #define CLKPS1_REG CLKPR
00606 #define CLKPS2_REG CLKPR
00607 #define CLKPS3_REG CLKPR
00608 #define CLKPCE_REG CLKPR
00609
00610
00611 #define OCR0B_0_REG OCR0B
00612 #define OCR0B_1_REG OCR0B
00613 #define OCR0B_2_REG OCR0B
00614 #define OCR0B_3_REG OCR0B
00615 #define OCR0B_4_REG OCR0B
00616 #define OCR0B_5_REG OCR0B
00617 #define OCR0B_6_REG OCR0B
00618 #define OCR0B_7_REG OCR0B
00619
00620
00621 #define WDP0_REG WDTCSR
00622 #define WDP1_REG WDTCSR
00623 #define WDP2_REG WDTCSR
00624 #define WDE_REG WDTCSR
00625 #define WDCE_REG WDTCSR
00626 #define WDP3_REG WDTCSR
00627 #define WDIE_REG WDTCSR
00628 #define WDIF_REG WDTCSR
00629
00630
00631 #define C_REG SREG
00632 #define Z_REG SREG
00633 #define N_REG SREG
00634 #define V_REG SREG
00635 #define S_REG SREG
00636 #define H_REG SREG
00637 #define T_REG SREG
00638 #define I_REG SREG
00639
00640
00641 #define DDJ0_REG DDRJ
00642 #define DDJ1_REG DDRJ
00643 #define DDJ2_REG DDRJ
00644 #define DDJ3_REG DDRJ
00645 #define DDJ4_REG DDRJ
00646 #define DDJ5_REG DDRJ
00647 #define DDJ6_REG DDRJ
00648 #define DDJ7_REG DDRJ
00649
00650
00651 #define DDK0_REG DDRK
00652 #define DDK1_REG DDRK
00653 #define DDK2_REG DDRK
00654 #define DDK3_REG DDRK
00655 #define DDK4_REG DDRK
00656 #define DDK5_REG DDRK
00657 #define DDK6_REG DDRK
00658 #define DDK7_REG DDRK
00659
00660
00661 #define DDH0_REG DDRH
00662 #define DDH1_REG DDRH
00663 #define DDH2_REG DDRH
00664 #define DDH3_REG DDRH
00665 #define DDH4_REG DDRH
00666 #define DDH5_REG DDRH
00667 #define DDH6_REG DDRH
00668 #define DDH7_REG DDRH
00669
00670
00671 #define DDL0_REG DDRL
00672 #define DDL1_REG DDRL
00673 #define DDL2_REG DDRL
00674 #define DDL3_REG DDRL
00675 #define DDL4_REG DDRL
00676 #define DDL5_REG DDRL
00677 #define DDL6_REG DDRL
00678 #define DDL7_REG DDRL
00679
00680
00681 #define UBRR_0_REG UBRR1L
00682 #define UBRR_1_REG UBRR1L
00683 #define UBRR_2_REG UBRR1L
00684 #define UBRR_3_REG UBRR1L
00685 #define UBRR_4_REG UBRR1L
00686 #define UBRR_5_REG UBRR1L
00687 #define UBRR_6_REG UBRR1L
00688 #define UBRR_7_REG UBRR1L
00689
00690
00691 #define DDC0_REG DDRC
00692 #define DDC1_REG DDRC
00693 #define DDC2_REG DDRC
00694 #define DDC3_REG DDRC
00695 #define DDC4_REG DDRC
00696 #define DDC5_REG DDRC
00697 #define DDC6_REG DDRC
00698 #define DDC7_REG DDRC
00699
00700
00701 #define OCR3AL0_REG OCR3AL
00702 #define OCR3AL1_REG OCR3AL
00703 #define OCR3AL2_REG OCR3AL
00704 #define OCR3AL3_REG OCR3AL
00705 #define OCR3AL4_REG OCR3AL
00706 #define OCR3AL5_REG OCR3AL
00707 #define OCR3AL6_REG OCR3AL
00708 #define OCR3AL7_REG OCR3AL
00709
00710
00711 #define DDA0_REG DDRA
00712 #define DDA1_REG DDRA
00713 #define DDA2_REG DDRA
00714 #define DDA3_REG DDRA
00715 #define DDA4_REG DDRA
00716 #define DDA5_REG DDRA
00717 #define DDA6_REG DDRA
00718 #define DDA7_REG DDRA
00719
00720
00721 #define UBRR_8_REG UBRR1H
00722 #define UBRR_9_REG UBRR1H
00723 #define UBRR_10_REG UBRR1H
00724 #define UBRR_11_REG UBRR1H
00725
00726
00727 #define DDG0_REG DDRG
00728 #define DDG1_REG DDRG
00729 #define DDG2_REG DDRG
00730 #define DDG3_REG DDRG
00731 #define DDG4_REG DDRG
00732 #define DDG5_REG DDRG
00733
00734
00735 #define OCR3AH0_REG OCR3AH
00736 #define OCR3AH1_REG OCR3AH
00737 #define OCR3AH2_REG OCR3AH
00738 #define OCR3AH3_REG OCR3AH
00739 #define OCR3AH4_REG OCR3AH
00740 #define OCR3AH5_REG OCR3AH
00741 #define OCR3AH6_REG OCR3AH
00742 #define OCR3AH7_REG OCR3AH
00743
00744
00745 #define CS10_REG TCCR1B
00746 #define CS11_REG TCCR1B
00747 #define CS12_REG TCCR1B
00748 #define WGM12_REG TCCR1B
00749 #define WGM13_REG TCCR1B
00750 #define ICES1_REG TCCR1B
00751 #define ICNC1_REG TCCR1B
00752
00753
00754 #define CAL0_REG OSCCAL
00755 #define CAL1_REG OSCCAL
00756 #define CAL2_REG OSCCAL
00757 #define CAL3_REG OSCCAL
00758 #define CAL4_REG OSCCAL
00759 #define CAL5_REG OSCCAL
00760 #define CAL6_REG OSCCAL
00761 #define CAL7_REG OSCCAL
00762
00763
00764 #define DDD0_REG DDRD
00765 #define DDD1_REG DDRD
00766 #define DDD2_REG DDRD
00767 #define DDD3_REG DDRD
00768 #define DDD4_REG DDRD
00769 #define DDD5_REG DDRD
00770 #define DDD6_REG DDRD
00771 #define DDD7_REG DDRD
00772
00773
00774 #define TCNT5H0_REG TCNT5H
00775 #define TCNT5H1_REG TCNT5H
00776 #define TCNT5H2_REG TCNT5H
00777 #define TCNT5H3_REG TCNT5H
00778 #define TCNT5H4_REG TCNT5H
00779 #define TCNT5H5_REG TCNT5H
00780 #define TCNT5H6_REG TCNT5H
00781 #define TCNT5H7_REG TCNT5H
00782
00783
00784 #define GPIOR00_REG GPIOR0
00785 #define GPIOR01_REG GPIOR0
00786 #define GPIOR02_REG GPIOR0
00787 #define GPIOR03_REG GPIOR0
00788 #define GPIOR04_REG GPIOR0
00789 #define GPIOR05_REG GPIOR0
00790 #define GPIOR06_REG GPIOR0
00791 #define GPIOR07_REG GPIOR0
00792
00793
00794 #define GPIOR20_REG GPIOR2
00795 #define GPIOR21_REG GPIOR2
00796 #define GPIOR22_REG GPIOR2
00797 #define GPIOR23_REG GPIOR2
00798 #define GPIOR24_REG GPIOR2
00799 #define GPIOR25_REG GPIOR2
00800 #define GPIOR26_REG GPIOR2
00801 #define GPIOR27_REG GPIOR2
00802
00803
00804 #define TCNT5L0_REG TCNT5L
00805 #define TCNT5L1_REG TCNT5L
00806 #define TCNT5L2_REG TCNT5L
00807 #define TCNT5L3_REG TCNT5L
00808 #define TCNT5L4_REG TCNT5L
00809 #define TCNT5L5_REG TCNT5L
00810 #define TCNT5L6_REG TCNT5L
00811 #define TCNT5L7_REG TCNT5L
00812
00813
00814
00815
00816
00817
00818
00819
00820
00821
00822
00823
00824
00825
00826
00827
00828
00829
00830 #define PCIE0_REG PCICR
00831 #define PCIE1_REG PCICR
00832 #define PCIE2_REG PCICR
00833
00834
00835 #define TCNT2_0_REG TCNT2
00836 #define TCNT2_1_REG TCNT2
00837 #define TCNT2_2_REG TCNT2
00838 #define TCNT2_3_REG TCNT2
00839 #define TCNT2_4_REG TCNT2
00840 #define TCNT2_5_REG TCNT2
00841 #define TCNT2_6_REG TCNT2
00842 #define TCNT2_7_REG TCNT2
00843
00844
00845 #define TXB82_REG UCSR2B
00846 #define RXB82_REG UCSR2B
00847 #define UCSZ22_REG UCSR2B
00848 #define TXEN2_REG UCSR2B
00849 #define RXEN2_REG UCSR2B
00850 #define UDRIE2_REG UCSR2B
00851 #define TXCIE2_REG UCSR2B
00852 #define RXCIE2_REG UCSR2B
00853
00854
00855 #define MPCM2_REG UCSR2A
00856 #define U2X2_REG UCSR2A
00857 #define UPE2_REG UCSR2A
00858 #define DOR2_REG UCSR2A
00859 #define FE2_REG UCSR2A
00860 #define UDRE2_REG UCSR2A
00861 #define TXC2_REG UCSR2A
00862 #define RXC2_REG UCSR2A
00863
00864
00865 #define TWGCE_REG TWAR
00866 #define TWA0_REG TWAR
00867 #define TWA1_REG TWAR
00868 #define TWA2_REG TWAR
00869 #define TWA3_REG TWAR
00870 #define TWA4_REG TWAR
00871 #define TWA5_REG TWAR
00872 #define TWA6_REG TWAR
00873
00874
00875 #define CS00_REG TCCR0B
00876 #define CS01_REG TCCR0B
00877 #define CS02_REG TCCR0B
00878 #define WGM02_REG TCCR0B
00879 #define FOC0B_REG TCCR0B
00880 #define FOC0A_REG TCCR0B
00881
00882
00883 #define WGM00_REG TCCR0A
00884 #define WGM01_REG TCCR0A
00885 #define COM0B0_REG TCCR0A
00886 #define COM0B1_REG TCCR0A
00887 #define COM0A0_REG TCCR0A
00888 #define COM0A1_REG TCCR0A
00889
00890
00891 #define UCPOL2_REG UCSR2C
00892 #define UCSZ20_REG UCSR2C
00893 #define UCSZ21_REG UCSR2C
00894 #define USBS2_REG UCSR2C
00895 #define UPM20_REG UCSR2C
00896 #define UPM21_REG UCSR2C
00897 #define UMSEL20_REG UCSR2C
00898 #define UMSEL21_REG UCSR2C
00899
00900
00901 #define TCNT0_0_REG TCNT0
00902 #define TCNT0_1_REG TCNT0
00903 #define TCNT0_2_REG TCNT0
00904 #define TCNT0_3_REG TCNT0
00905 #define TCNT0_4_REG TCNT0
00906 #define TCNT0_5_REG TCNT0
00907 #define TCNT0_6_REG TCNT0
00908 #define TCNT0_7_REG TCNT0
00909
00910
00911 #define TOV4_REG TIFR4
00912 #define OCF4A_REG TIFR4
00913 #define OCF4B_REG TIFR4
00914 #define OCF4C_REG TIFR4
00915 #define ICF4_REG TIFR4
00916
00917
00918 #define TOV5_REG TIFR5
00919 #define OCF5A_REG TIFR5
00920 #define OCF5B_REG TIFR5
00921 #define OCF5C_REG TIFR5
00922 #define ICF5_REG TIFR5
00923
00924
00925 #define TOV2_REG TIFR2
00926 #define OCF2A_REG TIFR2
00927 #define OCF2B_REG TIFR2
00928
00929
00930 #define TOV3_REG TIFR3
00931 #define OCF3A_REG TIFR3
00932 #define OCF3B_REG TIFR3
00933 #define OCF3C_REG TIFR3
00934 #define ICF3_REG TIFR3
00935
00936
00937 #define SPR0_REG SPCR
00938 #define SPR1_REG SPCR
00939 #define CPHA_REG SPCR
00940 #define CPOL_REG SPCR
00941 #define MSTR_REG SPCR
00942 #define DORD_REG SPCR
00943 #define SPE_REG SPCR
00944 #define SPIE_REG SPCR
00945
00946
00947 #define TOV1_REG TIFR1
00948 #define OCF1A_REG TIFR1
00949 #define OCF1B_REG TIFR1
00950 #define OCF1C_REG TIFR1
00951 #define ICF1_REG TIFR1
00952
00953
00954 #define OCR4AH0_REG OCR4AH
00955 #define OCR4AH1_REG OCR4AH
00956 #define OCR4AH2_REG OCR4AH
00957 #define OCR4AH3_REG OCR4AH
00958 #define OCR4AH4_REG OCR4AH
00959 #define OCR4AH5_REG OCR4AH
00960 #define OCR4AH6_REG OCR4AH
00961 #define OCR4AH7_REG OCR4AH
00962
00963
00964 #define OCR5CH0_REG OCR5CH
00965 #define OCR5CH1_REG OCR5CH
00966 #define OCR5CH2_REG OCR5CH
00967 #define OCR5CH3_REG OCR5CH
00968 #define OCR5CH4_REG OCR5CH
00969 #define OCR5CH5_REG OCR5CH
00970 #define OCR5CH6_REG OCR5CH
00971 #define OCR5CH7_REG OCR5CH
00972
00973
00974 #define OCR4AL0_REG OCR4AL
00975 #define OCR4AL1_REG OCR4AL
00976 #define OCR4AL2_REG OCR4AL
00977 #define OCR4AL3_REG OCR4AL
00978 #define OCR4AL4_REG OCR4AL
00979 #define OCR4AL5_REG OCR4AL
00980 #define OCR4AL6_REG OCR4AL
00981 #define OCR4AL7_REG OCR4AL
00982
00983
00984 #define OCR5CL0_REG OCR5CL
00985 #define OCR5CL1_REG OCR5CL
00986 #define OCR5CL2_REG OCR5CL
00987 #define OCR5CL3_REG OCR5CL
00988 #define OCR5CL4_REG OCR5CL
00989 #define OCR5CL5_REG OCR5CL
00990 #define OCR5CL6_REG OCR5CL
00991 #define OCR5CL7_REG OCR5CL
00992
00993
00994 #define OCR3CH0_REG OCR3CH
00995 #define OCR3CH1_REG OCR3CH
00996 #define OCR3CH2_REG OCR3CH
00997 #define OCR3CH3_REG OCR3CH
00998 #define OCR3CH4_REG OCR3CH
00999 #define OCR3CH5_REG OCR3CH
01000 #define OCR3CH6_REG OCR3CH
01001 #define OCR3CH7_REG OCR3CH
01002
01003
01004 #define OCR3CL0_REG OCR3CL
01005 #define OCR3CL1_REG OCR3CL
01006 #define OCR3CL2_REG OCR3CL
01007 #define OCR3CL3_REG OCR3CL
01008 #define OCR3CL4_REG OCR3CL
01009 #define OCR3CL5_REG OCR3CL
01010 #define OCR3CL6_REG OCR3CL
01011 #define OCR3CL7_REG OCR3CL
01012
01013
01014 #define PSRSYNC_REG GTCCR
01015 #define TSM_REG GTCCR
01016 #define PSRASY_REG GTCCR
01017
01018
01019 #define TWBR0_REG TWBR
01020 #define TWBR1_REG TWBR
01021 #define TWBR2_REG TWBR
01022 #define TWBR3_REG TWBR
01023 #define TWBR4_REG TWBR
01024 #define TWBR5_REG TWBR
01025 #define TWBR6_REG TWBR
01026 #define TWBR7_REG TWBR
01027
01028
01029 #define SP8_REG SPH
01030 #define SP9_REG SPH
01031 #define SP10_REG SPH
01032 #define SP11_REG SPH
01033 #define SP12_REG SPH
01034 #define SP13_REG SPH
01035 #define SP14_REG SPH
01036 #define SP15_REG SPH
01037
01038
01039 #define FOC3C_REG TCCR3C
01040 #define FOC3B_REG TCCR3C
01041 #define FOC3A_REG TCCR3C
01042
01043
01044 #define CS30_REG TCCR3B
01045 #define CS31_REG TCCR3B
01046 #define CS32_REG TCCR3B
01047 #define WGM32_REG TCCR3B
01048 #define WGM33_REG TCCR3B
01049 #define ICES3_REG TCCR3B
01050 #define ICNC3_REG TCCR3B
01051
01052
01053 #define WGM30_REG TCCR3A
01054 #define WGM31_REG TCCR3A
01055 #define COM3C0_REG TCCR3A
01056 #define COM3C1_REG TCCR3A
01057 #define COM3B0_REG TCCR3A
01058 #define COM3B1_REG TCCR3A
01059 #define COM3A0_REG TCCR3A
01060 #define COM3A1_REG TCCR3A
01061
01062
01063 #define PORTF0_REG PORTF
01064 #define PORTF1_REG PORTF
01065 #define PORTF2_REG PORTF
01066 #define PORTF3_REG PORTF
01067 #define PORTF4_REG PORTF
01068 #define PORTF5_REG PORTF
01069 #define PORTF6_REG PORTF
01070 #define PORTF7_REG PORTF
01071
01072
01073 #define PCINT8_REG PCMSK1
01074 #define PCINT9_REG PCMSK1
01075 #define PCINT10_REG PCMSK1
01076 #define PCINT11_REG PCMSK1
01077 #define PCINT12_REG PCMSK1
01078 #define PCINT13_REG PCMSK1
01079 #define PCINT14_REG PCMSK1
01080 #define PCINT15_REG PCMSK1
01081
01082
01083 #define OCR1BL0_REG OCR1BL
01084 #define OCR1BL1_REG OCR1BL
01085 #define OCR1BL2_REG OCR1BL
01086 #define OCR1BL3_REG OCR1BL
01087 #define OCR1BL4_REG OCR1BL
01088 #define OCR1BL5_REG OCR1BL
01089 #define OCR1BL6_REG OCR1BL
01090 #define OCR1BL7_REG OCR1BL
01091
01092
01093 #define TCNT3H0_REG TCNT3H
01094 #define TCNT3H1_REG TCNT3H
01095 #define TCNT3H2_REG TCNT3H
01096 #define TCNT3H3_REG TCNT3H
01097 #define TCNT3H4_REG TCNT3H
01098 #define TCNT3H5_REG TCNT3H
01099 #define TCNT3H6_REG TCNT3H
01100 #define TCNT3H7_REG TCNT3H
01101
01102
01103 #define OCR1BH0_REG OCR1BH
01104 #define OCR1BH1_REG OCR1BH
01105 #define OCR1BH2_REG OCR1BH
01106 #define OCR1BH3_REG OCR1BH
01107 #define OCR1BH4_REG OCR1BH
01108 #define OCR1BH5_REG OCR1BH
01109 #define OCR1BH6_REG OCR1BH
01110 #define OCR1BH7_REG OCR1BH
01111
01112
01113 #define TCNT3L0_REG TCNT3L
01114 #define TCNT3L1_REG TCNT3L
01115 #define TCNT3L2_REG TCNT3L
01116 #define TCNT3L3_REG TCNT3L
01117 #define TCNT3L4_REG TCNT3L
01118 #define TCNT3L5_REG TCNT3L
01119 #define TCNT3L6_REG TCNT3L
01120 #define TCNT3L7_REG TCNT3L
01121
01122
01123 #define ICR5L0_REG ICR5L
01124 #define ICR5L1_REG ICR5L
01125 #define ICR5L2_REG ICR5L
01126 #define ICR5L3_REG ICR5L
01127 #define ICR5L4_REG ICR5L
01128 #define ICR5L5_REG ICR5L
01129 #define ICR5L6_REG ICR5L
01130 #define ICR5L7_REG ICR5L
01131
01132
01133 #define SP0_REG SPL
01134 #define SP1_REG SPL
01135 #define SP2_REG SPL
01136 #define SP3_REG SPL
01137 #define SP4_REG SPL
01138 #define SP5_REG SPL
01139 #define SP6_REG SPL
01140 #define SP7_REG SPL
01141
01142
01143 #define ICR5H0_REG ICR5H
01144 #define ICR5H1_REG ICR5H
01145 #define ICR5H2_REG ICR5H
01146 #define ICR5H3_REG ICR5H
01147 #define ICR5H4_REG ICR5H
01148 #define ICR5H5_REG ICR5H
01149 #define ICR5H6_REG ICR5H
01150 #define ICR5H7_REG ICR5H
01151
01152
01153 #define JTRF_REG MCUSR
01154 #define PORF_REG MCUSR
01155 #define EXTRF_REG MCUSR
01156 #define BORF_REG MCUSR
01157 #define WDRF_REG MCUSR
01158
01159
01160 #define PINK0_REG PINK
01161 #define PINK1_REG PINK
01162 #define PINK2_REG PINK
01163 #define PINK3_REG PINK
01164 #define PINK4_REG PINK
01165 #define PINK5_REG PINK
01166 #define PINK6_REG PINK
01167 #define PINK7_REG PINK
01168
01169
01170 #define PINJ0_REG PINJ
01171 #define PINJ1_REG PINJ
01172 #define PINJ2_REG PINJ
01173 #define PINJ3_REG PINJ
01174 #define PINJ4_REG PINJ
01175 #define PINJ5_REG PINJ
01176 #define PINJ6_REG PINJ
01177 #define PINJ7_REG PINJ
01178
01179
01180 #define SE_REG SMCR
01181 #define SM0_REG SMCR
01182 #define SM1_REG SMCR
01183 #define SM2_REG SMCR
01184
01185
01186 #define TWIE_REG TWCR
01187 #define TWEN_REG TWCR
01188 #define TWWC_REG TWCR
01189 #define TWSTO_REG TWCR
01190 #define TWSTA_REG TWCR
01191 #define TWEA_REG TWCR
01192 #define TWINT_REG TWCR
01193
01194
01195 #define PINH0_REG PINH
01196 #define PINH1_REG PINH
01197 #define PINH2_REG PINH
01198 #define PINH3_REG PINH
01199 #define PINH4_REG PINH
01200 #define PINH5_REG PINH
01201 #define PINH6_REG PINH
01202 #define PINH7_REG PINH
01203
01204
01205 #define PCIF0_REG PCIFR
01206 #define PCIF1_REG PCIFR
01207 #define PCIF2_REG PCIFR
01208
01209
01210 #define WGM20_REG TCCR2A
01211 #define WGM21_REG TCCR2A
01212 #define COM2B0_REG TCCR2A
01213 #define COM2B1_REG TCCR2A
01214 #define COM2A0_REG TCCR2A
01215 #define COM2A1_REG TCCR2A
01216
01217
01218 #define CS20_REG TCCR2B
01219 #define CS21_REG TCCR2B
01220 #define CS22_REG TCCR2B
01221 #define WGM22_REG TCCR2B
01222 #define FOC2B_REG TCCR2B
01223 #define FOC2A_REG TCCR2B
01224
01225
01226
01227
01228
01229
01230
01231
01232 #define PING0_REG PING
01233 #define PING1_REG PING
01234 #define PING2_REG PING
01235 #define PING3_REG PING
01236 #define PING4_REG PING
01237 #define PING5_REG PING
01238
01239
01240
01241
01242
01243
01244
01245
01246
01247
01248
01249
01250 #define TWPS0_REG TWSR
01251 #define TWPS1_REG TWSR
01252 #define TWS3_REG TWSR
01253 #define TWS4_REG TWSR
01254 #define TWS5_REG TWSR
01255 #define TWS6_REG TWSR
01256 #define TWS7_REG TWSR
01257
01258
01259 #define ICR4H0_REG ICR4H
01260 #define ICR4H1_REG ICR4H
01261 #define ICR4H2_REG ICR4H
01262 #define ICR4H3_REG ICR4H
01263 #define ICR4H4_REG ICR4H
01264 #define ICR4H5_REG ICR4H
01265 #define ICR4H6_REG ICR4H
01266 #define ICR4H7_REG ICR4H
01267
01268
01269 #define EEAR0_REG EEARL
01270 #define EEAR1_REG EEARL
01271 #define EEAR2_REG EEARL
01272 #define EEAR3_REG EEARL
01273 #define EEAR4_REG EEARL
01274 #define EEAR5_REG EEARL
01275 #define EEAR6_REG EEARL
01276 #define EEAR7_REG EEARL
01277
01278
01279 #define PCINT16_REG PCMSK2
01280 #define PCINT17_REG PCMSK2
01281 #define PCINT18_REG PCMSK2
01282 #define PCINT19_REG PCMSK2
01283 #define PCINT20_REG PCMSK2
01284 #define PCINT21_REG PCMSK2
01285 #define PCINT22_REG PCMSK2
01286 #define PCINT23_REG PCMSK2
01287
01288
01289 #define ICR4L0_REG ICR4L
01290 #define ICR4L1_REG ICR4L
01291 #define ICR4L2_REG ICR4L
01292 #define ICR4L3_REG ICR4L
01293 #define ICR4L4_REG ICR4L
01294 #define ICR4L5_REG ICR4L
01295 #define ICR4L6_REG ICR4L
01296 #define ICR4L7_REG ICR4L
01297
01298
01299 #define JTD_REG MCUCR
01300 #define IVCE_REG MCUCR
01301 #define IVSEL_REG MCUCR
01302 #define PUD_REG MCUCR
01303
01304
01305 #define PINC0_REG PINC
01306 #define PINC1_REG PINC
01307 #define PINC2_REG PINC
01308 #define PINC3_REG PINC
01309 #define PINC4_REG PINC
01310 #define PINC5_REG PINC
01311 #define PINC6_REG PINC
01312 #define PINC7_REG PINC
01313
01314
01315 #define OCR1CL0_REG OCR1CL
01316 #define OCR1CL1_REG OCR1CL
01317 #define OCR1CL2_REG OCR1CL
01318 #define OCR1CL3_REG OCR1CL
01319 #define OCR1CL4_REG OCR1CL
01320 #define OCR1CL5_REG OCR1CL
01321 #define OCR1CL6_REG OCR1CL
01322 #define OCR1CL7_REG OCR1CL
01323
01324
01325 #define TCNT4L0_REG TCNT4L
01326 #define TCNT4L1_REG TCNT4L
01327 #define TCNT4L2_REG TCNT4L
01328 #define TCNT4L3_REG TCNT4L
01329 #define TCNT4L4_REG TCNT4L
01330 #define TCNT4L5_REG TCNT4L
01331 #define TCNT4L6_REG TCNT4L
01332 #define TCNT4L7_REG TCNT4L
01333
01334
01335 #define OCR1CH0_REG OCR1CH
01336 #define OCR1CH1_REG OCR1CH
01337 #define OCR1CH2_REG OCR1CH
01338 #define OCR1CH3_REG OCR1CH
01339 #define OCR1CH4_REG OCR1CH
01340 #define OCR1CH5_REG OCR1CH
01341 #define OCR1CH6_REG OCR1CH
01342 #define OCR1CH7_REG OCR1CH
01343
01344
01345 #define TCNT4H0_REG TCNT4H
01346 #define TCNT4H1_REG TCNT4H
01347 #define TCNT4H2_REG TCNT4H
01348 #define TCNT4H3_REG TCNT4H
01349 #define TCNT4H4_REG TCNT4H
01350 #define TCNT4H5_REG TCNT4H
01351 #define TCNT4H6_REG TCNT4H
01352 #define TCNT4H7_REG TCNT4H
01353
01354
01355 #define OCDR0_REG OCDR
01356 #define OCDR1_REG OCDR
01357 #define OCDR2_REG OCDR
01358 #define OCDR3_REG OCDR
01359 #define OCDR4_REG OCDR
01360 #define OCDR5_REG OCDR
01361 #define OCDR6_REG OCDR
01362 #define OCDR7_REG OCDR
01363
01364
01365 #define PINA0_REG PINA
01366 #define PINA1_REG PINA
01367 #define PINA2_REG PINA
01368 #define PINA3_REG PINA
01369 #define PINA4_REG PINA
01370 #define PINA5_REG PINA
01371 #define PINA6_REG PINA
01372 #define PINA7_REG PINA
01373
01374
01375 #define EERE_REG EECR
01376 #define EEPE_REG EECR
01377 #define EEMPE_REG EECR
01378 #define EERIE_REG EECR
01379 #define EEPM0_REG EECR
01380 #define EEPM1_REG EECR
01381
01382
01383 #define TXB81_REG UCSR1B
01384 #define RXB81_REG UCSR1B
01385 #define UCSZ12_REG UCSR1B
01386 #define TXEN1_REG UCSR1B
01387 #define RXEN1_REG UCSR1B
01388 #define UDRIE1_REG UCSR1B
01389 #define TXCIE1_REG UCSR1B
01390 #define RXCIE1_REG UCSR1B
01391
01392
01393 #define UCPOL1_REG UCSR1C
01394 #define UCSZ10_REG UCSR1C
01395 #define UCSZ11_REG UCSR1C
01396 #define USBS1_REG UCSR1C
01397 #define UPM10_REG UCSR1C
01398 #define UPM11_REG UCSR1C
01399 #define UMSEL10_REG UCSR1C
01400 #define UMSEL11_REG UCSR1C
01401
01402
01403 #define MPCM1_REG UCSR1A
01404 #define U2X1_REG UCSR1A
01405 #define UPE1_REG UCSR1A
01406 #define DOR1_REG UCSR1A
01407 #define FE1_REG UCSR1A
01408 #define UDRE1_REG UCSR1A
01409 #define TXC1_REG UCSR1A
01410 #define RXC1_REG UCSR1A
01411
01412
01413 #define DDB0_REG DDRB
01414 #define DDB1_REG DDRB
01415 #define DDB2_REG DDRB
01416 #define DDB3_REG DDRB
01417 #define DDB4_REG DDRB
01418 #define DDB5_REG DDRB
01419 #define DDB6_REG DDRB
01420 #define DDB7_REG DDRB
01421
01422
01423 #define EIND0_REG EIND
01424
01425
01426 #define TWD0_REG TWDR
01427 #define TWD1_REG TWDR
01428 #define TWD2_REG TWDR
01429 #define TWD3_REG TWDR
01430 #define TWD4_REG TWDR
01431 #define TWD5_REG TWDR
01432 #define TWD6_REG TWDR
01433 #define TWD7_REG TWDR
01434
01435
01436 #define WGM50_REG TCCR5A
01437 #define WGM51_REG TCCR5A
01438 #define COM5C0_REG TCCR5A
01439 #define COM5C1_REG TCCR5A
01440 #define COM5B0_REG TCCR5A
01441 #define COM5B1_REG TCCR5A
01442 #define COM5A0_REG TCCR5A
01443 #define COM5A1_REG TCCR5A
01444
01445
01446 #define OCR1AH0_REG OCR1AH
01447 #define OCR1AH1_REG OCR1AH
01448 #define OCR1AH2_REG OCR1AH
01449 #define OCR1AH3_REG OCR1AH
01450 #define OCR1AH4_REG OCR1AH
01451 #define OCR1AH5_REG OCR1AH
01452 #define OCR1AH6_REG OCR1AH
01453 #define OCR1AH7_REG OCR1AH
01454
01455
01456 #define FOC5C_REG TCCR5C
01457 #define FOC5B_REG TCCR5C
01458 #define FOC5A_REG TCCR5C
01459
01460
01461 #define CS50_REG TCCR5B
01462 #define CS51_REG TCCR5B
01463 #define CS52_REG TCCR5B
01464 #define WGM52_REG TCCR5B
01465 #define WGM53_REG TCCR5B
01466 #define ICES5_REG TCCR5B
01467 #define ICNC5_REG TCCR5B
01468
01469
01470 #define ADPS0_REG ADCSRA
01471 #define ADPS1_REG ADCSRA
01472 #define ADPS2_REG ADCSRA
01473 #define ADIE_REG ADCSRA
01474 #define ADIF_REG ADCSRA
01475 #define ADATE_REG ADCSRA
01476 #define ADSC_REG ADCSRA
01477 #define ADEN_REG ADCSRA
01478
01479
01480 #define ACME_REG ADCSRB
01481 #define ADTS0_REG ADCSRB
01482 #define ADTS1_REG ADCSRB
01483 #define ADTS2_REG ADCSRB
01484 #define MUX5_REG ADCSRB
01485
01486
01487 #define OCR5AL0_REG OCR5AL
01488 #define OCR5AL1_REG OCR5AL
01489 #define OCR5AL2_REG OCR5AL
01490 #define OCR5AL3_REG OCR5AL
01491 #define OCR5AL4_REG OCR5AL
01492 #define OCR5AL5_REG OCR5AL
01493 #define OCR5AL6_REG OCR5AL
01494 #define OCR5AL7_REG OCR5AL
01495
01496
01497 #define WGM10_REG TCCR1A
01498 #define WGM11_REG TCCR1A
01499 #define COM1C0_REG TCCR1A
01500 #define COM1C1_REG TCCR1A
01501 #define COM1B0_REG TCCR1A
01502 #define COM1B1_REG TCCR1A
01503 #define COM1A0_REG TCCR1A
01504 #define COM1A1_REG TCCR1A
01505
01506
01507 #define OCR4CH0_REG OCR4CH
01508 #define OCR4CH1_REG OCR4CH
01509 #define OCR4CH2_REG OCR4CH
01510 #define OCR4CH3_REG OCR4CH
01511 #define OCR4CH4_REG OCR4CH
01512 #define OCR4CH5_REG OCR4CH
01513 #define OCR4CH6_REG OCR4CH
01514 #define OCR4CH7_REG OCR4CH
01515
01516
01517 #define OCR5AH0_REG OCR5AH
01518 #define OCR5AH1_REG OCR5AH
01519 #define OCR5AH2_REG OCR5AH
01520 #define OCR5AH3_REG OCR5AH
01521 #define OCR5AH4_REG OCR5AH
01522 #define OCR5AH5_REG OCR5AH
01523 #define OCR5AH6_REG OCR5AH
01524 #define OCR5AH7_REG OCR5AH
01525
01526
01527 #define OCR4CL0_REG OCR4CL
01528 #define OCR4CL1_REG OCR4CL
01529 #define OCR4CL2_REG OCR4CL
01530 #define OCR4CL3_REG OCR4CL
01531 #define OCR4CL4_REG OCR4CL
01532 #define OCR4CL5_REG OCR4CL
01533 #define OCR4CL6_REG OCR4CL
01534 #define OCR4CL7_REG OCR4CL
01535
01536
01537 #define TCNT1L0_REG TCNT1L
01538 #define TCNT1L1_REG TCNT1L
01539 #define TCNT1L2_REG TCNT1L
01540 #define TCNT1L3_REG TCNT1L
01541 #define TCNT1L4_REG TCNT1L
01542 #define TCNT1L5_REG TCNT1L
01543 #define TCNT1L6_REG TCNT1L
01544 #define TCNT1L7_REG TCNT1L
01545
01546
01547 #define FOC1C_REG TCCR1C
01548 #define FOC1B_REG TCCR1C
01549 #define FOC1A_REG TCCR1C
01550
01551
01552 #define ICR3H0_REG ICR3H
01553 #define ICR3H1_REG ICR3H
01554 #define ICR3H2_REG ICR3H
01555 #define ICR3H3_REG ICR3H
01556 #define ICR3H4_REG ICR3H
01557 #define ICR3H5_REG ICR3H
01558 #define ICR3H6_REG ICR3H
01559 #define ICR3H7_REG ICR3H
01560
01561
01562 #define DDE0_REG DDRE
01563 #define DDE1_REG DDRE
01564 #define DDE2_REG DDRE
01565 #define DDE3_REG DDRE
01566 #define DDE4_REG DDRE
01567 #define DDE5_REG DDRE
01568 #define DDE6_REG DDRE
01569 #define DDE7_REG DDRE
01570
01571
01572 #define PORTD0_REG PORTD
01573 #define PORTD1_REG PORTD
01574 #define PORTD2_REG PORTD
01575 #define PORTD3_REG PORTD
01576 #define PORTD4_REG PORTD
01577 #define PORTD5_REG PORTD
01578 #define PORTD6_REG PORTD
01579 #define PORTD7_REG PORTD
01580
01581
01582 #define ICR3L0_REG ICR3L
01583 #define ICR3L1_REG ICR3L
01584 #define ICR3L2_REG ICR3L
01585 #define ICR3L3_REG ICR3L
01586 #define ICR3L4_REG ICR3L
01587 #define ICR3L5_REG ICR3L
01588 #define ICR3L6_REG ICR3L
01589 #define ICR3L7_REG ICR3L
01590
01591
01592 #define PORTE0_REG PORTE
01593 #define PORTE1_REG PORTE
01594 #define PORTE2_REG PORTE
01595 #define PORTE3_REG PORTE
01596 #define PORTE4_REG PORTE
01597 #define PORTE5_REG PORTE
01598 #define PORTE6_REG PORTE
01599 #define PORTE7_REG PORTE
01600
01601
01602 #define SPMEN_REG SPMCSR
01603 #define PGERS_REG SPMCSR
01604 #define PGWRT_REG SPMCSR
01605 #define BLBSET_REG SPMCSR
01606 #define RWWSRE_REG SPMCSR
01607 #define SIGRD_REG SPMCSR
01608 #define RWWSB_REG SPMCSR
01609 #define SPMIE_REG SPMCSR
01610
01611
01612 #define PORTB0_REG PORTB
01613 #define PORTB1_REG PORTB
01614 #define PORTB2_REG PORTB
01615 #define PORTB3_REG PORTB
01616 #define PORTB4_REG PORTB
01617 #define PORTB5_REG PORTB
01618 #define PORTB6_REG PORTB
01619 #define PORTB7_REG PORTB
01620
01621
01622 #define ADCL0_REG ADCL
01623 #define ADCL1_REG ADCL
01624 #define ADCL2_REG ADCL
01625 #define ADCL3_REG ADCL
01626 #define ADCL4_REG ADCL
01627 #define ADCL5_REG ADCL
01628 #define ADCL6_REG ADCL
01629 #define ADCL7_REG ADCL
01630
01631
01632 #define ADCH0_REG ADCH
01633 #define ADCH1_REG ADCH
01634 #define ADCH2_REG ADCH
01635 #define ADCH3_REG ADCH
01636 #define ADCH4_REG ADCH
01637 #define ADCH5_REG ADCH
01638 #define ADCH6_REG ADCH
01639 #define ADCH7_REG ADCH
01640
01641
01642 #define OCR5BH0_REG OCR5BH
01643 #define OCR5BH1_REG OCR5BH
01644 #define OCR5BH2_REG OCR5BH
01645 #define OCR5BH3_REG OCR5BH
01646 #define OCR5BH4_REG OCR5BH
01647 #define OCR5BH5_REG OCR5BH
01648 #define OCR5BH6_REG OCR5BH
01649 #define OCR5BH7_REG OCR5BH
01650
01651
01652 #define OCR3BL0_REG OCR3BL
01653 #define OCR3BL1_REG OCR3BL
01654 #define OCR3BL2_REG OCR3BL
01655 #define OCR3BL3_REG OCR3BL
01656 #define OCR3BL4_REG OCR3BL
01657 #define OCR3BL5_REG OCR3BL
01658 #define OCR3BL6_REG OCR3BL
01659 #define OCR3BL7_REG OCR3BL
01660
01661
01662 #define OCR5BL0_REG OCR5BL
01663 #define OCR5BL1_REG OCR5BL
01664 #define OCR5BL2_REG OCR5BL
01665 #define OCR5BL3_REG OCR5BL
01666 #define OCR5BL4_REG OCR5BL
01667 #define OCR5BL5_REG OCR5BL
01668 #define OCR5BL6_REG OCR5BL
01669 #define OCR5BL7_REG OCR5BL
01670
01671
01672 #define OCR3BH0_REG OCR3BH
01673 #define OCR3BH1_REG OCR3BH
01674 #define OCR3BH2_REG OCR3BH
01675 #define OCR3BH3_REG OCR3BH
01676 #define OCR3BH4_REG OCR3BH
01677 #define OCR3BH5_REG OCR3BH
01678 #define OCR3BH6_REG OCR3BH
01679 #define OCR3BH7_REG OCR3BH
01680
01681
01682 #define TOIE2_REG TIMSK2
01683 #define OCIE2A_REG TIMSK2
01684 #define OCIE2B_REG TIMSK2
01685
01686
01687 #define TOIE3_REG TIMSK3
01688 #define OCIE3A_REG TIMSK3
01689 #define OCIE3B_REG TIMSK3
01690 #define OCIE3C_REG TIMSK3
01691 #define ICIE3_REG TIMSK3
01692
01693
01694 #define TOIE0_REG TIMSK0
01695 #define OCIE0A_REG TIMSK0
01696 #define OCIE0B_REG TIMSK0
01697
01698
01699 #define TOIE1_REG TIMSK1
01700 #define OCIE1A_REG TIMSK1
01701 #define OCIE1B_REG TIMSK1
01702 #define OCIE1C_REG TIMSK1
01703 #define ICIE1_REG TIMSK1
01704
01705
01706 #define TOIE4_REG TIMSK4
01707 #define OCIE4A_REG TIMSK4
01708 #define OCIE4B_REG TIMSK4
01709 #define OCIE4C_REG TIMSK4
01710 #define ICIE4_REG TIMSK4
01711
01712
01713 #define TOIE5_REG TIMSK5
01714 #define OCIE5A_REG TIMSK5
01715 #define OCIE5B_REG TIMSK5
01716 #define OCIE5C_REG TIMSK5
01717 #define ICIE5_REG TIMSK5
01718
01719
01720 #define CS40_REG TCCR4B
01721 #define CS41_REG TCCR4B
01722 #define CS42_REG TCCR4B
01723 #define WGM42_REG TCCR4B
01724 #define WGM43_REG TCCR4B
01725 #define ICES4_REG TCCR4B
01726 #define ICNC4_REG TCCR4B
01727
01728
01729 #define FOC4C_REG TCCR4C
01730 #define FOC4B_REG TCCR4C
01731 #define FOC4A_REG TCCR4C
01732
01733
01734 #define WGM40_REG TCCR4A
01735 #define WGM41_REG TCCR4A
01736 #define COM4C0_REG TCCR4A
01737 #define COM4C1_REG TCCR4A
01738 #define COM4B0_REG TCCR4A
01739 #define COM4B1_REG TCCR4A
01740 #define COM4A0_REG TCCR4A
01741 #define COM4A1_REG TCCR4A
01742
01743
01744 #define PCINT0_REG PCMSK0
01745 #define PCINT1_REG PCMSK0
01746 #define PCINT2_REG PCMSK0
01747 #define PCINT3_REG PCMSK0
01748 #define PCINT4_REG PCMSK0
01749 #define PCINT5_REG PCMSK0
01750 #define PCINT6_REG PCMSK0
01751 #define PCINT7_REG PCMSK0
01752
01753
01754 #define XMM0_REG XMCRB
01755 #define XMM1_REG XMCRB
01756 #define XMM2_REG XMCRB
01757 #define XMBK_REG XMCRB
01758
01759
01760 #define SRW00_REG XMCRA
01761 #define SRW01_REG XMCRA
01762 #define SRW10_REG XMCRA
01763 #define SRW11_REG XMCRA
01764 #define SRL0_REG XMCRA
01765 #define SRL1_REG XMCRA
01766 #define SRL2_REG XMCRA
01767 #define SRE_REG XMCRA
01768
01769
01770 #define PINL0_REG PINL
01771 #define PINL1_REG PINL
01772 #define PINL2_REG PINL
01773 #define PINL3_REG PINL
01774 #define PINL4_REG PINL
01775 #define PINL5_REG PINL
01776 #define PINL6_REG PINL
01777 #define PINL7_REG PINL
01778
01779
01780 #define OCR4BL0_REG OCR4BL
01781 #define OCR4BL1_REG OCR4BL
01782 #define OCR4BL2_REG OCR4BL
01783 #define OCR4BL3_REG OCR4BL
01784 #define OCR4BL4_REG OCR4BL
01785 #define OCR4BL5_REG OCR4BL
01786 #define OCR4BL6_REG OCR4BL
01787 #define OCR4BL7_REG OCR4BL
01788
01789
01790 #define PINB0_REG PINB
01791 #define PINB1_REG PINB
01792 #define PINB2_REG PINB
01793 #define PINB3_REG PINB
01794 #define PINB4_REG PINB
01795 #define PINB5_REG PINB
01796 #define PINB6_REG PINB
01797 #define PINB7_REG PINB
01798
01799
01800 #define INTF0_REG EIFR
01801 #define INTF1_REG EIFR
01802 #define INTF2_REG EIFR
01803 #define INTF3_REG EIFR
01804 #define INTF4_REG EIFR
01805 #define INTF5_REG EIFR
01806 #define INTF6_REG EIFR
01807 #define INTF7_REG EIFR
01808
01809
01810 #define OCR4BH0_REG OCR4BH
01811 #define OCR4BH1_REG OCR4BH
01812 #define OCR4BH2_REG OCR4BH
01813 #define OCR4BH3_REG OCR4BH
01814 #define OCR4BH4_REG OCR4BH
01815 #define OCR4BH5_REG OCR4BH
01816 #define OCR4BH6_REG OCR4BH
01817 #define OCR4BH7_REG OCR4BH
01818
01819
01820 #define PINF0_REG PINF
01821 #define PINF1_REG PINF
01822 #define PINF2_REG PINF
01823 #define PINF3_REG PINF
01824 #define PINF4_REG PINF
01825 #define PINF5_REG PINF
01826 #define PINF6_REG PINF
01827 #define PINF7_REG PINF
01828
01829
01830 #define PINE0_REG PINE
01831 #define PINE1_REG PINE
01832 #define PINE2_REG PINE
01833 #define PINE3_REG PINE
01834 #define PINE4_REG PINE
01835 #define PINE5_REG PINE
01836 #define PINE6_REG PINE
01837 #define PINE7_REG PINE
01838
01839
01840 #define PIND0_REG PIND
01841 #define PIND1_REG PIND
01842 #define PIND2_REG PIND
01843 #define PIND3_REG PIND
01844 #define PIND4_REG PIND
01845 #define PIND5_REG PIND
01846 #define PIND6_REG PIND
01847 #define PIND7_REG PIND
01848
01849
01850 #define TWAM0_REG TWAMR
01851 #define TWAM1_REG TWAMR
01852 #define TWAM2_REG TWAMR
01853 #define TWAM3_REG TWAMR
01854 #define TWAM4_REG TWAMR
01855 #define TWAM5_REG TWAMR
01856 #define TWAM6_REG TWAMR
01857
01858
01859 #define PRADC_REG PRR0
01860 #define PRUSART0_REG PRR0
01861 #define PRSPI_REG PRR0
01862 #define PRTIM1_REG PRR0
01863 #define PRTIM0_REG PRR0
01864 #define PRTIM2_REG PRR0
01865 #define PRTWI_REG PRR0
01866
01867
01868 #define OCR1AL0_REG OCR1AL
01869 #define OCR1AL1_REG OCR1AL
01870 #define OCR1AL2_REG OCR1AL
01871 #define OCR1AL3_REG OCR1AL
01872 #define OCR1AL4_REG OCR1AL
01873 #define OCR1AL5_REG OCR1AL
01874 #define OCR1AL6_REG OCR1AL
01875 #define OCR1AL7_REG OCR1AL
01876
01877
01878 #define TOV0_REG TIFR0
01879 #define OCF0A_REG TIFR0
01880 #define OCF0B_REG TIFR0
01881
01882
01883 #define PRUSART1_REG PRR1
01884 #define PRUSART2_REG PRR1
01885 #define PRUSART3_REG PRR1
01886 #define PRTIM3_REG PRR1
01887 #define PRTIM4_REG PRR1
01888 #define PRTIM5_REG PRR1
01889
01890
01891 #define AD0_PORT PORTA
01892 #define AD0_BIT 0
01893
01894 #define AD1_PORT PORTA
01895 #define AD1_BIT 1
01896
01897 #define AD2_PORT PORTA
01898 #define AD2_BIT 2
01899
01900 #define AD3_PORT PORTA
01901 #define AD3_BIT 3
01902
01903 #define AD4_PORT PORTA
01904 #define AD4_BIT 4
01905
01906 #define AD5_PORT PORTA
01907 #define AD5_BIT 5
01908
01909 #define AD6_PORT PORTA
01910 #define AD6_BIT 6
01911
01912 #define AD7_PORT PORTA
01913 #define AD7_BIT 7
01914
01915 #define SS_PORT PORTB
01916 #define SS_BIT 0
01917 #define PCINT0_PORT PORTB
01918 #define PCINT0_BIT 0
01919
01920 #define SCK_PORT PORTB
01921 #define SCK_BIT 1
01922 #define PCINT1_PORT PORTB
01923 #define PCINT1_BIT 1
01924
01925 #define MOSI_PORT PORTB
01926 #define MOSI_BIT 2
01927 #define PCINT2_PORT PORTB
01928 #define PCINT2_BIT 2
01929
01930 #define MISO_PORT PORTB
01931 #define MISO_BIT 3
01932 #define PCINT3_PORT PORTB
01933 #define PCINT3_BIT 3
01934
01935 #define OC0A_PORT PORTB
01936 #define OC0A_BIT 4
01937 #define PCINT4_PORT PORTB
01938 #define PCINT4_BIT 4
01939
01940 #define OC1B_PORT PORTB
01941 #define OC1B_BIT 6
01942 #define PCINT6_PORT PORTB
01943 #define PCINT6_BIT 6
01944
01945 #define OC0A_PORT PORTB
01946 #define OC0A_BIT 7
01947 #define OC1C_PORT PORTB
01948 #define OC1C_BIT 7
01949 #define PCINT7_PORT PORTB
01950 #define PCINT7_BIT 7
01951
01952 #define A8_PORT PORTC
01953 #define A8_BIT 0
01954
01955 #define A9_PORT PORTC
01956 #define A9_BIT 1
01957
01958 #define A10_PORT PORTC
01959 #define A10_BIT 2
01960
01961 #define A11_PORT PORTC
01962 #define A11_BIT 3
01963
01964 #define A12_PORT PORTC
01965 #define A12_BIT 4
01966
01967 #define A13_PORT PORTC
01968 #define A13_BIT 5
01969
01970 #define A14_PORT PORTC
01971 #define A14_BIT 6
01972
01973 #define A15_PORT PORTC
01974 #define A15_BIT 7
01975
01976 #define SCL_PORT PORTD
01977 #define SCL_BIT 0
01978 #define INT0_PORT PORTD
01979 #define INT0_BIT 0
01980
01981 #define SDA_PORT PORTD
01982 #define SDA_BIT 1
01983 #define INT1_PORT PORTD
01984 #define INT1_BIT 1
01985
01986 #define RXD1_PORT PORTD
01987 #define RXD1_BIT 2
01988 #define INT2_PORT PORTD
01989 #define INT2_BIT 2
01990
01991 #define TXD1_PORT PORTD
01992 #define TXD1_BIT 3
01993 #define INT3_PORT PORTD
01994 #define INT3_BIT 3
01995
01996 #define ICP1_PORT PORTD
01997 #define ICP1_BIT 4
01998
01999 #define XCK1_PORT PORTD
02000 #define XCK1_BIT 5
02001
02002 #define T1_PORT PORTD
02003 #define T1_BIT 6
02004
02005 #define T0_PORT PORTD
02006 #define T0_BIT 7
02007
02008 #define RXD_PORT PORTE
02009 #define RXD_BIT 0
02010 #define PCINT8_PORT PORTE
02011 #define PCINT8_BIT 0
02012
02013 #define TXD0_PORT PORTE
02014 #define TXD0_BIT 1
02015
02016 #define XCK_PORT PORTE
02017 #define XCK_BIT 2
02018 #define AIN0_PORT PORTE
02019 #define AIN0_BIT 2
02020
02021 #define OC3A_PORT PORTE
02022 #define OC3A_BIT 3
02023 #define AIN1_PORT PORTE
02024 #define AIN1_BIT 3
02025
02026 #define OC3B_PORT PORTE
02027 #define OC3B_BIT 4
02028 #define INT4_PORT PORTE
02029 #define INT4_BIT 4
02030
02031 #define T3_PORT PORTE
02032 #define T3_BIT 6
02033 #define INT6_PORT PORTE
02034 #define INT6_BIT 6
02035
02036 #define CLKO_PORT PORTE
02037 #define CLKO_BIT 7
02038 #define ICP3_PORT PORTE
02039 #define ICP3_BIT 7
02040 #define INT7_PORT PORTE
02041 #define INT7_BIT 7
02042
02043 #define ADC0_PORT PORTF
02044 #define ADC0_BIT 0
02045
02046 #define ADC1_PORT PORTF
02047 #define ADC1_BIT 1
02048
02049 #define ADC2_PORT PORTF
02050 #define ADC2_BIT 2
02051
02052 #define ADC3_PORT PORTF
02053 #define ADC3_BIT 3
02054
02055 #define ADC4_PORT PORTF
02056 #define ADC4_BIT 4
02057 #define TCK_PORT PORTF
02058 #define TCK_BIT 4
02059
02060 #define ADC6_PORT PORTF
02061 #define ADC6_BIT 6
02062 #define TDO_PORT PORTF
02063 #define TDO_BIT 6
02064
02065 #define ADC7_PORT PORTF
02066 #define ADC7_BIT 7
02067 #define TDI_PORT PORTF
02068 #define TDI_BIT 7
02069
02070 #define WR_PORT PORTG
02071 #define WR_BIT 0
02072
02073 #define RD_PORT PORTG
02074 #define RD_BIT 1
02075
02076 #define ALE_PORT PORTG
02077 #define ALE_BIT 2
02078
02079 #define TOSC2_PORT PORTG
02080 #define TOSC2_BIT 3
02081
02082 #define TOSC1_PORT PORTG
02083 #define TOSC1_BIT 4
02084
02085 #define OC0B_PORT PORTG
02086 #define OC0B_BIT 5
02087
02088 #define RXD2_PORT PORTH
02089 #define RXD2_BIT 0
02090
02091 #define TXD2_PORT PORTH
02092 #define TXD2_BIT 1
02093
02094 #define XCK2_PORT PORTH
02095 #define XCK2_BIT 2
02096
02097 #define OC4A_PORT PORTH
02098 #define OC4A_BIT 3
02099
02100 #define OC4B_PORT PORTH
02101 #define OC4B_BIT 4
02102
02103 #define OC2B_PORT PORTH
02104 #define OC2B_BIT 6
02105
02106 #define T4_PORT PORTH
02107 #define T4_BIT 7
02108
02109 #define RXD3_PORT PORTJ
02110 #define RXD3_BIT 0
02111 #define PCINT9_PORT PORTJ
02112 #define PCINT9_BIT 0
02113
02114 #define TXD3_PORT PORTJ
02115 #define TXD3_BIT 1
02116 #define PCINT10_PORT PORTJ
02117 #define PCINT10_BIT 1
02118
02119 #define XCK3_PORT PORTJ
02120 #define XCK3_BIT 2
02121 #define PCINT11_PORT PORTJ
02122 #define PCINT11_BIT 2
02123
02124 #define PCINT12_PORT PORTJ
02125 #define PCINT12_BIT 3
02126
02127 #define PCINT13_PORT PORTJ
02128 #define PCINT13_BIT 4
02129
02130 #define PCINT15_PORT PORTJ
02131 #define PCINT15_BIT 6
02132
02133 #define ADC8_PORT PORTK
02134 #define ADC8_BIT 0
02135 #define PCINT16_PORT PORTK
02136 #define PCINT16_BIT 0
02137
02138 #define ADC9_PORT PORTK
02139 #define ADC9_BIT 1
02140 #define PCINT17_PORT PORTK
02141 #define PCINT17_BIT 1
02142
02143 #define ADC10_PORT PORTK
02144 #define ADC10_BIT 2
02145 #define PCINT18_PORT PORTK
02146 #define PCINT18_BIT 2
02147
02148 #define ADC11_PORT PORTK
02149 #define ADC11_BIT 3
02150 #define PCINT19_PORT PORTK
02151 #define PCINT19_BIT 3
02152
02153 #define ADC12_PORT PORTK
02154 #define ADC12_BIT 4
02155 #define PCINT20_PORT PORTK
02156 #define PCINT20_BIT 4
02157
02158 #define ADC13_PORT PORTK
02159 #define ADC13_BIT 5
02160 #define PCINT21_PORT PORTK
02161 #define PCINT21_BIT 5
02162
02163 #define ADC14_PORT PORTK
02164 #define ADC14_BIT 6
02165 #define PCINT22_PORT PORTK
02166 #define PCINT22_BIT 6
02167
02168 #define ADC15_PORT PORTK
02169 #define ADC15_BIT 7
02170 #define PCINT23_PORT PORTK
02171 #define PCINT23_BIT 7
02172
02173 #define ICP4_PORT PORTL
02174 #define ICP4_BIT 0
02175
02176 #define ICP5_PORT PORTL
02177 #define ICP5_BIT 1
02178
02179 #define T5_PORT PORTL
02180 #define T5_BIT 2
02181
02182 #define OC5A_PORT PORTL
02183 #define OC5A_BIT 3
02184
02185 #define OC5B_PORT PORTL
02186 #define OC5B_BIT 4
02187
02188