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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_32 3
00032 #define TIMER0_PRESCALER_DIV_64 4
00033 #define TIMER0_PRESCALER_DIV_128 5
00034 #define TIMER0_PRESCALER_DIV_256 6
00035 #define TIMER0_PRESCALER_DIV_1024 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 32
00041 #define TIMER0_PRESCALER_REG_4 64
00042 #define TIMER0_PRESCALER_REG_5 128
00043 #define TIMER0_PRESCALER_REG_6 256
00044 #define TIMER0_PRESCALER_REG_7 1024
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_64 3
00070 #define TIMER2_PRESCALER_DIV_256 4
00071 #define TIMER2_PRESCALER_DIV_1024 5
00072 #define TIMER2_PRESCALER_DIV_FALL 6
00073 #define TIMER2_PRESCALER_DIV_RISE 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 64
00079 #define TIMER2_PRESCALER_REG_4 256
00080 #define TIMER2_PRESCALER_REG_5 1024
00081 #define TIMER2_PRESCALER_REG_6 -1
00082 #define TIMER2_PRESCALER_REG_7 -2
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER1C_AVAILABLE
00091 #define TIMER2_AVAILABLE
00092 #define TIMER3_AVAILABLE
00093 #define TIMER3A_AVAILABLE
00094 #define TIMER3B_AVAILABLE
00095 #define TIMER3C_AVAILABLE
00096
00097
00098 #define SIG_OVERFLOW0_NUM 0
00099 #define SIG_OVERFLOW1_NUM 1
00100 #define SIG_OVERFLOW2_NUM 2
00101 #define SIG_OVERFLOW3_NUM 3
00102 #define SIG_OVERFLOW_TOTAL_NUM 4
00103
00104
00105 #define SIG_OUTPUT_COMPARE0_NUM 0
00106 #define SIG_OUTPUT_COMPARE1A_NUM 1
00107 #define SIG_OUTPUT_COMPARE1B_NUM 2
00108 #define SIG_OUTPUT_COMPARE1C_NUM 3
00109 #define SIG_OUTPUT_COMPARE2_NUM 4
00110 #define SIG_OUTPUT_COMPARE3A_NUM 5
00111 #define SIG_OUTPUT_COMPARE3B_NUM 6
00112 #define SIG_OUTPUT_COMPARE3C_NUM 7
00113 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
00114
00115
00116 #define PWM0_NUM 0
00117 #define PWM1A_NUM 1
00118 #define PWM1B_NUM 2
00119 #define PWM1C_NUM 3
00120 #define PWM2_NUM 4
00121 #define PWM3A_NUM 5
00122 #define PWM3B_NUM 6
00123 #define PWM3C_NUM 7
00124 #define PWM_TOTAL_NUM 8
00125
00126
00127 #define SIG_INPUT_CAPTURE1_NUM 0
00128 #define SIG_INPUT_CAPTURE3_NUM 1
00129 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00130
00131
00132
00133 #define WDP0_REG WDTCR
00134 #define WDP1_REG WDTCR
00135 #define WDP2_REG WDTCR
00136 #define WDE_REG WDTCR
00137 #define WDCE_REG WDTCR
00138
00139
00140 #define ICR1H0_REG ICR1H
00141 #define ICR1H1_REG ICR1H
00142 #define ICR1H2_REG ICR1H
00143 #define ICR1H3_REG ICR1H
00144 #define ICR1H4_REG ICR1H
00145 #define ICR1H5_REG ICR1H
00146 #define ICR1H6_REG ICR1H
00147 #define ICR1H7_REG ICR1H
00148
00149
00150 #define MUX0_REG ADMUX
00151 #define MUX1_REG ADMUX
00152 #define MUX2_REG ADMUX
00153 #define MUX3_REG ADMUX
00154 #define MUX4_REG ADMUX
00155 #define ADLAR_REG ADMUX
00156 #define REFS0_REG ADMUX
00157 #define REFS1_REG ADMUX
00158
00159
00160 #define CS00_REG TCCR0
00161 #define CS01_REG TCCR0
00162 #define CS02_REG TCCR0
00163 #define CTC0_REG TCCR0
00164 #define COM00_REG TCCR0
00165 #define COM01_REG TCCR0
00166 #define PWM0_REG TCCR0
00167
00168
00169 #define C_REG SREG
00170 #define Z_REG SREG
00171 #define N_REG SREG
00172 #define V_REG SREG
00173 #define S_REG SREG
00174 #define H_REG SREG
00175 #define T_REG SREG
00176 #define I_REG SREG
00177
00178
00179 #define DDB0_REG DDRB
00180 #define DDB1_REG DDRB
00181 #define DDB2_REG DDRB
00182 #define DDB3_REG DDRB
00183 #define DDB4_REG DDRB
00184 #define DDB5_REG DDRB
00185 #define DDB6_REG DDRB
00186 #define DDB7_REG DDRB
00187
00188
00189 #define XDIV0_REG XDIV
00190 #define XDIV1_REG XDIV
00191 #define XDIV2_REG XDIV
00192 #define XDIV3_REG XDIV
00193 #define XDIV4_REG XDIV
00194 #define XDIV5_REG XDIV
00195 #define XDIV6_REG XDIV
00196 #define XDIVEN_REG XDIV
00197
00198
00199 #define EEDR0_REG EEDR
00200 #define EEDR1_REG EEDR
00201 #define EEDR2_REG EEDR
00202 #define EEDR3_REG EEDR
00203 #define EEDR4_REG EEDR
00204 #define EEDR5_REG EEDR
00205 #define EEDR6_REG EEDR
00206 #define EEDR7_REG EEDR
00207
00208
00209 #define DDE0_REG DDRE
00210 #define DDE1_REG DDRE
00211 #define DDE2_REG DDRE
00212 #define DDE3_REG DDRE
00213 #define DDE4_REG DDRE
00214 #define DDE5_REG DDRE
00215 #define DDE6_REG DDRE
00216 #define DDE7_REG DDRE
00217
00218
00219 #define DDA0_REG DDRA
00220 #define DDA1_REG DDRA
00221 #define DDA2_REG DDRA
00222 #define DDA3_REG DDRA
00223 #define DDA4_REG DDRA
00224 #define DDA5_REG DDRA
00225 #define DDA6_REG DDRA
00226 #define DDA7_REG DDRA
00227
00228
00229 #define PWM10_REG TCCR1A
00230 #define PWM11_REG TCCR1A
00231 #define COM1B0_REG TCCR1A
00232 #define COM1B1_REG TCCR1A
00233 #define COM1A0_REG TCCR1A
00234 #define COM1A1_REG TCCR1A
00235
00236
00237 #define DDD0_REG DDRD
00238 #define DDD1_REG DDRD
00239 #define DDD2_REG DDRD
00240 #define DDD3_REG DDRD
00241 #define DDD4_REG DDRD
00242 #define DDD5_REG DDRD
00243 #define DDD6_REG DDRD
00244 #define DDD7_REG DDRD
00245
00246
00247 #define CS10_REG TCCR1B
00248 #define CS11_REG TCCR1B
00249 #define CS12_REG TCCR1B
00250 #define CTC1_REG TCCR1B
00251 #define ICES1_REG TCCR1B
00252 #define ICNC1_REG TCCR1B
00253
00254
00255 #define TOIE2_REG TIMSK
00256 #define OCIE2_REG TIMSK
00257 #define TOIE0_REG TIMSK
00258 #define OCIE0_REG TIMSK
00259 #define TOIE1_REG TIMSK
00260 #define OCIE1B_REG TIMSK
00261 #define OCIE1A_REG TIMSK
00262 #define TICIE1_REG TIMSK
00263
00264
00265 #define INT0_REG EIMSK
00266 #define INT1_REG EIMSK
00267 #define INT2_REG EIMSK
00268 #define INT3_REG EIMSK
00269 #define INT4_REG EIMSK
00270 #define INT5_REG EIMSK
00271 #define INT6_REG EIMSK
00272 #define INT7_REG EIMSK
00273
00274
00275 #define RAMPZ0_REG RAMPZ
00276
00277
00278 #define SPDR0_REG SPDR
00279 #define SPDR1_REG SPDR
00280 #define SPDR2_REG SPDR
00281 #define SPDR3_REG SPDR
00282 #define SPDR4_REG SPDR
00283 #define SPDR5_REG SPDR
00284 #define SPDR6_REG SPDR
00285 #define SPDR7_REG SPDR
00286
00287
00288 #define ADPS0_REG ADCSR
00289 #define ADPS1_REG ADCSR
00290 #define ADPS2_REG ADCSR
00291 #define ADIE_REG ADCSR
00292 #define ADIF_REG ADCSR
00293 #define ADFR_REG ADCSR
00294 #define ADSC_REG ADCSR
00295 #define ADEN_REG ADCSR
00296
00297
00298 #define ACME_REG SFIOR
00299 #define PSR321_REG SFIOR
00300 #define PSR0_REG SFIOR
00301 #define PUD_REG SFIOR
00302 #define TSM_REG SFIOR
00303
00304
00305 #define UDR00_REG UDR0
00306 #define UDR01_REG UDR0
00307 #define UDR02_REG UDR0
00308 #define UDR03_REG UDR0
00309 #define UDR04_REG UDR0
00310 #define UDR05_REG UDR0
00311 #define UDR06_REG UDR0
00312 #define UDR07_REG UDR0
00313
00314
00315 #define SP8_REG SPH
00316 #define SP9_REG SPH
00317 #define SP10_REG SPH
00318 #define SP11_REG SPH
00319 #define SP12_REG SPH
00320 #define SP13_REG SPH
00321 #define SP14_REG SPH
00322 #define SP15_REG SPH
00323
00324
00325 #define OCR1BL0_REG OCR1BL
00326 #define OCR1BL1_REG OCR1BL
00327 #define OCR1BL2_REG OCR1BL
00328 #define OCR1BL3_REG OCR1BL
00329 #define OCR1BL4_REG OCR1BL
00330 #define OCR1BL5_REG OCR1BL
00331 #define OCR1BL6_REG OCR1BL
00332 #define OCR1BL7_REG OCR1BL
00333
00334
00335 #define SP0_REG SPL
00336 #define SP1_REG SPL
00337 #define SP2_REG SPL
00338 #define SP3_REG SPL
00339 #define SP4_REG SPL
00340 #define SP5_REG SPL
00341 #define SP6_REG SPL
00342 #define SP7_REG SPL
00343
00344
00345 #define OCR1BH0_REG OCR1BH
00346 #define OCR1BH1_REG OCR1BH
00347 #define OCR1BH2_REG OCR1BH
00348 #define OCR1BH3_REG OCR1BH
00349 #define OCR1BH4_REG OCR1BH
00350 #define OCR1BH5_REG OCR1BH
00351 #define OCR1BH6_REG OCR1BH
00352 #define OCR1BH7_REG OCR1BH
00353
00354
00355 #define PIND0_REG PIND
00356 #define PIND1_REG PIND
00357 #define PIND2_REG PIND
00358 #define PIND3_REG PIND
00359 #define PIND4_REG PIND
00360 #define PIND5_REG PIND
00361 #define PIND6_REG PIND
00362 #define PIND7_REG PIND
00363
00364
00365 #define ICR1L0_REG ICR1L
00366 #define ICR1L1_REG ICR1L
00367 #define ICR1L2_REG ICR1L
00368 #define ICR1L3_REG ICR1L
00369 #define ICR1L4_REG ICR1L
00370 #define ICR1L5_REG ICR1L
00371 #define ICR1L6_REG ICR1L
00372 #define ICR1L7_REG ICR1L
00373
00374
00375 #define SPI2X_REG SPSR
00376 #define WCOL_REG SPSR
00377 #define SPIF_REG SPSR
00378
00379
00380 #define ADCL0_REG ADCL
00381 #define ADCL1_REG ADCL
00382 #define ADCL2_REG ADCL
00383 #define ADCL3_REG ADCL
00384 #define ADCL4_REG ADCL
00385 #define ADCL5_REG ADCL
00386 #define ADCL6_REG ADCL
00387 #define ADCL7_REG ADCL
00388
00389
00390 #define ACIS0_REG ACSR
00391 #define ACIS1_REG ACSR
00392 #define ACIC_REG ACSR
00393 #define ACIE_REG ACSR
00394 #define ACI_REG ACSR
00395 #define ACO_REG ACSR
00396 #define ACBG_REG ACSR
00397 #define ACD_REG ACSR
00398
00399
00400 #define EERE_REG EECR
00401 #define EEWE_REG EECR
00402 #define EEMWE_REG EECR
00403 #define EERIE_REG EECR
00404
00405
00406 #define PORTE0_REG PORTE
00407 #define PORTE1_REG PORTE
00408 #define PORTE2_REG PORTE
00409 #define PORTE3_REG PORTE
00410 #define PORTE4_REG PORTE
00411 #define PORTE5_REG PORTE
00412 #define PORTE6_REG PORTE
00413 #define PORTE7_REG PORTE
00414
00415
00416 #define TCNT1L0_REG TCNT1L
00417 #define TCNT1L1_REG TCNT1L
00418 #define TCNT1L2_REG TCNT1L
00419 #define TCNT1L3_REG TCNT1L
00420 #define TCNT1L4_REG TCNT1L
00421 #define TCNT1L5_REG TCNT1L
00422 #define TCNT1L6_REG TCNT1L
00423 #define TCNT1L7_REG TCNT1L
00424
00425
00426 #define PORTB0_REG PORTB
00427 #define PORTB1_REG PORTB
00428 #define PORTB2_REG PORTB
00429 #define PORTB3_REG PORTB
00430 #define PORTB4_REG PORTB
00431 #define PORTB5_REG PORTB
00432 #define PORTB6_REG PORTB
00433 #define PORTB7_REG PORTB
00434
00435
00436 #define PORTD0_REG PORTD
00437 #define PORTD1_REG PORTD
00438 #define PORTD2_REG PORTD
00439 #define PORTD3_REG PORTD
00440 #define PORTD4_REG PORTD
00441 #define PORTD5_REG PORTD
00442 #define PORTD6_REG PORTD
00443 #define PORTD7_REG PORTD
00444
00445
00446 #define TXB80_REG UCSR0B
00447 #define RXB80_REG UCSR0B
00448 #define UCSZ02_REG UCSR0B
00449 #define TXEN0_REG UCSR0B
00450 #define RXEN0_REG UCSR0B
00451 #define UDRIE0_REG UCSR0B
00452 #define TXCIE0_REG UCSR0B
00453 #define RXCIE0_REG UCSR0B
00454
00455
00456 #define TCNT1H0_REG TCNT1H
00457 #define TCNT1H1_REG TCNT1H
00458 #define TCNT1H2_REG TCNT1H
00459 #define TCNT1H3_REG TCNT1H
00460 #define TCNT1H4_REG TCNT1H
00461 #define TCNT1H5_REG TCNT1H
00462 #define TCNT1H6_REG TCNT1H
00463 #define TCNT1H7_REG TCNT1H
00464
00465
00466 #define PORTC0_REG PORTC
00467 #define PORTC1_REG PORTC
00468 #define PORTC2_REG PORTC
00469 #define PORTC3_REG PORTC
00470 #define PORTC4_REG PORTC
00471 #define PORTC5_REG PORTC
00472 #define PORTC6_REG PORTC
00473 #define PORTC7_REG PORTC
00474
00475
00476 #define ADCH0_REG ADCH
00477 #define ADCH1_REG ADCH
00478 #define ADCH2_REG ADCH
00479 #define ADCH3_REG ADCH
00480 #define ADCH4_REG ADCH
00481 #define ADCH5_REG ADCH
00482 #define ADCH6_REG ADCH
00483 #define ADCH7_REG ADCH
00484
00485
00486 #define PORTA0_REG PORTA
00487 #define PORTA1_REG PORTA
00488 #define PORTA2_REG PORTA
00489 #define PORTA3_REG PORTA
00490 #define PORTA4_REG PORTA
00491 #define PORTA5_REG PORTA
00492 #define PORTA6_REG PORTA
00493 #define PORTA7_REG PORTA
00494
00495
00496 #define TCNT2_0_REG TCNT2
00497 #define TCNT2_1_REG TCNT2
00498 #define TCNT2_2_REG TCNT2
00499 #define TCNT2_3_REG TCNT2
00500 #define TCNT2_4_REG TCNT2
00501 #define TCNT2_5_REG TCNT2
00502 #define TCNT2_6_REG TCNT2
00503 #define TCNT2_7_REG TCNT2
00504
00505
00506 #define TCNT0_0_REG TCNT0
00507 #define TCNT0_1_REG TCNT0
00508 #define TCNT0_2_REG TCNT0
00509 #define TCNT0_3_REG TCNT0
00510 #define TCNT0_4_REG TCNT0
00511 #define TCNT0_5_REG TCNT0
00512 #define TCNT0_6_REG TCNT0
00513 #define TCNT0_7_REG TCNT0
00514
00515
00516 #define PORF_REG MCUCSR
00517 #define EXTRF_REG MCUCSR
00518
00519
00520 #define MPCM0_REG UCSR0A
00521 #define U2X0_REG UCSR0A
00522 #define UPE0_REG UCSR0A
00523 #define DOR0_REG UCSR0A
00524 #define FE0_REG UCSR0A
00525 #define UDRE0_REG UCSR0A
00526 #define TXC0_REG UCSR0A
00527 #define RXC0_REG UCSR0A
00528
00529
00530 #define EEARL0_REG EEARL
00531 #define EEARL1_REG EEARL
00532 #define EEARL2_REG EEARL
00533 #define EEARL3_REG EEARL
00534 #define EEARL4_REG EEARL
00535 #define EEARL5_REG EEARL
00536 #define EEARL6_REG EEARL
00537 #define EEARL7_REG EEARL
00538
00539
00540 #define CS20_REG TCCR2
00541 #define CS21_REG TCCR2
00542 #define CS22_REG TCCR2
00543 #define CTC2_REG TCCR2
00544 #define COM20_REG TCCR2
00545 #define COM21_REG TCCR2
00546 #define PWM2_REG TCCR2
00547
00548
00549 #define TOV2_REG TIFR
00550 #define OCF2_REG TIFR
00551 #define TOV0_REG TIFR
00552 #define OCF0_REG TIFR
00553 #define TOV1_REG TIFR
00554 #define OCF1B_REG TIFR
00555 #define OCF1A_REG TIFR
00556 #define ICF1_REG TIFR
00557
00558
00559 #define UBRR0_REG UBRR0L
00560 #define UBRR1_REG UBRR0L
00561 #define UBRR2_REG UBRR0L
00562 #define UBRR3_REG UBRR0L
00563 #define UBRR4_REG UBRR0L
00564 #define UBRR5_REG UBRR0L
00565 #define UBRR6_REG UBRR0L
00566 #define UBRR7_REG UBRR0L
00567
00568
00569 #define EEAR8_REG EEARH
00570 #define EEAR9_REG EEARH
00571 #define EEAR10_REG EEARH
00572 #define EEAR11_REG EEARH
00573
00574
00575 #define ISC40_REG EICRB
00576 #define ISC41_REG EICRB
00577 #define ISC50_REG EICRB
00578 #define ISC51_REG EICRB
00579 #define ISC60_REG EICRB
00580 #define ISC61_REG EICRB
00581 #define ISC70_REG EICRB
00582 #define ISC71_REG EICRB
00583
00584
00585 #define PINB0_REG PINB
00586 #define PINB1_REG PINB
00587 #define PINB2_REG PINB
00588 #define PINB3_REG PINB
00589 #define PINB4_REG PINB
00590 #define PINB5_REG PINB
00591 #define PINB6_REG PINB
00592 #define PINB7_REG PINB
00593
00594
00595 #define INTF0_REG EIFR
00596 #define INTF1_REG EIFR
00597 #define INTF2_REG EIFR
00598 #define INTF3_REG EIFR
00599 #define INTF4_REG EIFR
00600 #define INTF5_REG EIFR
00601 #define INTF6_REG EIFR
00602 #define INTF7_REG EIFR
00603
00604
00605 #define PINF0_REG PINF
00606 #define PINF1_REG PINF
00607 #define PINF2_REG PINF
00608 #define PINF3_REG PINF
00609 #define PINF4_REG PINF
00610 #define PINF5_REG PINF
00611 #define PINF6_REG PINF
00612 #define PINF7_REG PINF
00613
00614
00615 #define PINE0_REG PINE
00616 #define PINE1_REG PINE
00617 #define PINE2_REG PINE
00618 #define PINE3_REG PINE
00619 #define PINE4_REG PINE
00620 #define PINE5_REG PINE
00621 #define PINE6_REG PINE
00622 #define PINE7_REG PINE
00623
00624
00625 #define IVCE_REG MCUCR
00626 #define IVSEL_REG MCUCR
00627 #define SM2_REG MCUCR
00628 #define SM0_REG MCUCR
00629 #define SM1_REG MCUCR
00630 #define SE_REG MCUCR
00631 #define SRW10_REG MCUCR
00632 #define SRE_REG MCUCR
00633
00634
00635 #define OCR1AH0_REG OCR1AH
00636 #define OCR1AH1_REG OCR1AH
00637 #define OCR1AH2_REG OCR1AH
00638 #define OCR1AH3_REG OCR1AH
00639 #define OCR1AH4_REG OCR1AH
00640 #define OCR1AH5_REG OCR1AH
00641 #define OCR1AH6_REG OCR1AH
00642 #define OCR1AH7_REG OCR1AH
00643
00644
00645 #define OCR1AL0_REG OCR1AL
00646 #define OCR1AL1_REG OCR1AL
00647 #define OCR1AL2_REG OCR1AL
00648 #define OCR1AL3_REG OCR1AL
00649 #define OCR1AL4_REG OCR1AL
00650 #define OCR1AL5_REG OCR1AL
00651 #define OCR1AL6_REG OCR1AL
00652 #define OCR1AL7_REG OCR1AL
00653
00654
00655 #define SPR0_REG SPCR
00656 #define SPR1_REG SPCR
00657 #define CPHA_REG SPCR
00658 #define CPOL_REG SPCR
00659 #define MSTR_REG SPCR
00660 #define DORD_REG SPCR
00661 #define SPE_REG SPCR
00662 #define SPIE_REG SPCR
00663
00664
00665 #define OCR0_0_REG OCR0
00666 #define OCR0_1_REG OCR0
00667 #define OCR0_2_REG OCR0
00668 #define OCR0_3_REG OCR0
00669 #define OCR0_4_REG OCR0
00670 #define OCR0_5_REG OCR0
00671 #define OCR0_6_REG OCR0
00672 #define OCR0_7_REG OCR0
00673
00674
00675 #define PINA0_REG PINA
00676 #define PINA1_REG PINA
00677 #define PINA2_REG PINA
00678 #define PINA3_REG PINA
00679 #define PINA4_REG PINA
00680 #define PINA5_REG PINA
00681 #define PINA6_REG PINA
00682 #define PINA7_REG PINA
00683
00684
00685 #define OCR2_0_REG OCR2
00686 #define OCR2_1_REG OCR2
00687 #define OCR2_2_REG OCR2
00688 #define OCR2_3_REG OCR2
00689 #define OCR2_4_REG OCR2
00690 #define OCR2_5_REG OCR2
00691 #define OCR2_6_REG OCR2
00692 #define OCR2_7_REG OCR2
00693
00694
00695 #define TCR0UB_REG ASSR
00696 #define OCR0UB_REG ASSR
00697 #define TCN0UB_REG ASSR
00698 #define AS0_REG ASSR
00699
00700
00701 #define AD0_PORT PORTA
00702 #define AD0_BIT 0
00703
00704 #define AD1_PORT PORTA
00705 #define AD1_BIT 1
00706
00707 #define AD2_PORT PORTA
00708 #define AD2_BIT 2
00709
00710 #define AD3_PORT PORTA
00711 #define AD3_BIT 3
00712
00713 #define AD4_PORT PORTA
00714 #define AD4_BIT 4
00715
00716 #define AD5_PORT PORTA
00717 #define AD5_BIT 5
00718
00719 #define AD6_PORT PORTA
00720 #define AD6_BIT 6
00721
00722 #define AD7_PORT PORTA
00723 #define AD7_BIT 7
00724
00725 #define SS_PORT PORTB
00726 #define SS_BIT 0
00727
00728 #define SCK_PORT PORTB
00729 #define SCK_BIT 1
00730
00731 #define MOSI_PORT PORTB
00732 #define MOSI_BIT 2
00733
00734 #define MISO_PORT PORTB
00735 #define MISO_BIT 3
00736
00737 #define OC0_PORT PORTB
00738 #define OC0_BIT 4
00739 #define PWM0_PORT PORTB
00740 #define PWM0_BIT 4
00741
00742 #define OC1A_PORT PORTB
00743 #define OC1A_BIT 5
00744 #define PWM1A_PORT PORTB
00745 #define PWM1A_BIT 5
00746
00747 #define OC1B_PORT PORTB
00748 #define OC1B_BIT 6
00749 #define PWM1B_PORT PORTB
00750 #define PWM1B_BIT 6
00751
00752 #define OC2_PORT PORTB
00753 #define OC2_BIT 7
00754 #define PWM2_PORT PORTB
00755 #define PWM2_BIT 7
00756 #define OC1C_PORT PORTB
00757 #define OC1C_BIT 7
00758
00759 #define A8_PORT PORTC
00760 #define A8_BIT 0
00761
00762 #define A9_PORT PORTC
00763 #define A9_BIT 1
00764
00765 #define A10_PORT PORTC
00766 #define A10_BIT 2
00767
00768 #define A11_PORT PORTC
00769 #define A11_BIT 3
00770
00771 #define A12_PORT PORTC
00772 #define A12_BIT 4
00773
00774 #define A13_PORT PORTC
00775 #define A13_BIT 5
00776
00777 #define A14_PORT PORTC
00778 #define A14_BIT 6
00779
00780 #define A15_PORT PORTC
00781 #define A15_BIT 7
00782
00783 #define SCL_PORT PORTD
00784 #define SCL_BIT 0
00785 #define INT0_PORT PORTD
00786 #define INT0_BIT 0
00787
00788 #define SDA_PORT PORTD
00789 #define SDA_BIT 1
00790 #define INT1_PORT PORTD
00791 #define INT1_BIT 1
00792
00793 #define RXD1_PORT PORTD
00794 #define RXD1_BIT 2
00795 #define INT2_PORT PORTD
00796 #define INT2_BIT 2
00797
00798 #define TXD1_PORT PORTD
00799 #define TXD1_BIT 3
00800 #define INT3_PORT PORTD
00801 #define INT3_BIT 3
00802
00803 #define IC1_PORT PORTD
00804 #define IC1_BIT 4
00805
00806 #define XCK1_PORT PORTD
00807 #define XCK1_BIT 5
00808
00809 #define T1_PORT PORTD
00810 #define T1_BIT 6
00811
00812 #define T2_PORT PORTD
00813 #define T2_BIT 7
00814
00815 #define RXD0_PORT PORTE
00816 #define RXD0_BIT 0
00817 #define PDI_PORT PORTE
00818 #define PDI_BIT 0
00819
00820 #define TXD0_PORT PORTE
00821 #define TXD0_BIT 1
00822 #define PDO_PORT PORTE
00823 #define PDO_BIT 1
00824
00825 #define XCK0_PORT PORTE
00826 #define XCK0_BIT 2
00827 #define AIN0_PORT PORTE
00828 #define AIN0_BIT 2
00829
00830 #define OC3A_PORT PORTE
00831 #define OC3A_BIT 3
00832 #define AIN1_PORT PORTE
00833 #define AIN1_BIT 3
00834
00835 #define OC3B_PORT PORTE
00836 #define OC3B_BIT 4
00837 #define INT4_PORT PORTE
00838 #define INT4_BIT 4
00839
00840 #define OC3C_PORT PORTE
00841 #define OC3C_BIT 5
00842 #define INT5_PORT PORTE
00843 #define INT5_BIT 5
00844
00845 #define T3_PORT PORTE
00846 #define T3_BIT 6
00847 #define INT6_PORT PORTE
00848 #define INT6_BIT 6
00849
00850 #define IC3_PORT PORTE
00851 #define IC3_BIT 7
00852 #define INT7_PORT PORTE
00853 #define INT7_BIT 7
00854
00855 #define ADC0_PORT PORTF
00856 #define ADC0_BIT 0
00857
00858 #define ADC1_PORT PORTF
00859 #define ADC1_BIT 1
00860
00861 #define ADC2_PORT PORTF
00862 #define ADC2_BIT 2
00863
00864 #define ADC3_PORT PORTF
00865 #define ADC3_BIT 3
00866
00867 #define ADC4_PORT PORTF
00868 #define ADC4_BIT 4
00869 #define TCK_PORT PORTF
00870 #define TCK_BIT 4
00871
00872 #define ADC5_PORT PORTF
00873 #define ADC5_BIT 5
00874 #define TMS_PORT PORTF
00875 #define TMS_BIT 5
00876
00877 #define ADC6_PORT PORTF
00878 #define ADC6_BIT 6
00879 #define TD0_PORT PORTF
00880 #define TD0_BIT 6
00881
00882 #define ADC7_PORT PORTF
00883 #define ADC7_BIT 7
00884 #define TDI_PORT PORTF
00885 #define TDI_BIT 7
00886
00887 #define WR_PORT PORTG
00888 #define WR_BIT 0
00889
00890 #define RD_PORT PORTG
00891 #define RD_BIT 1
00892
00893 #define ALE_PORT PORTG
00894 #define ALE_BIT 2
00895
00896 #define TOSC2_PORT PORTG
00897 #define TOSC2_BIT 3
00898
00899 #define TOSC1_PORT PORTG
00900 #define TOSC1_BIT 4
00901
00902