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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_32 3
00032 #define TIMER0_PRESCALER_DIV_64 4
00033 #define TIMER0_PRESCALER_DIV_128 5
00034 #define TIMER0_PRESCALER_DIV_256 6
00035 #define TIMER0_PRESCALER_DIV_1024 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 32
00041 #define TIMER0_PRESCALER_REG_4 64
00042 #define TIMER0_PRESCALER_REG_5 128
00043 #define TIMER0_PRESCALER_REG_6 256
00044 #define TIMER0_PRESCALER_REG_7 1024
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_64 3
00070 #define TIMER2_PRESCALER_DIV_256 4
00071 #define TIMER2_PRESCALER_DIV_1024 5
00072 #define TIMER2_PRESCALER_DIV_FALL 6
00073 #define TIMER2_PRESCALER_DIV_RISE 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 64
00079 #define TIMER2_PRESCALER_REG_4 256
00080 #define TIMER2_PRESCALER_REG_5 1024
00081 #define TIMER2_PRESCALER_REG_6 -1
00082 #define TIMER2_PRESCALER_REG_7 -2
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define WDP0_REG WDTCR
00119 #define WDP1_REG WDTCR
00120 #define WDP2_REG WDTCR
00121 #define WDE_REG WDTCR
00122 #define WDTOE_REG WDTCR
00123
00124
00125 #define ICR1H0_REG ICR1H
00126 #define ICR1H1_REG ICR1H
00127 #define ICR1H2_REG ICR1H
00128 #define ICR1H3_REG ICR1H
00129 #define ICR1H4_REG ICR1H
00130 #define ICR1H5_REG ICR1H
00131 #define ICR1H6_REG ICR1H
00132 #define ICR1H7_REG ICR1H
00133
00134
00135 #define MUX0_REG ADMUX
00136 #define MUX1_REG ADMUX
00137 #define MUX2_REG ADMUX
00138
00139
00140 #define CS00_REG TCCR0
00141 #define CS01_REG TCCR0
00142 #define CS02_REG TCCR0
00143 #define CTC0_REG TCCR0
00144 #define COM00_REG TCCR0
00145 #define COM01_REG TCCR0
00146 #define PWM0_REG TCCR0
00147
00148
00149 #define C_REG SREG
00150 #define Z_REG SREG
00151 #define N_REG SREG
00152 #define V_REG SREG
00153 #define S_REG SREG
00154 #define H_REG SREG
00155 #define T_REG SREG
00156 #define I_REG SREG
00157
00158
00159 #define DDB0_REG DDRB
00160 #define DDB1_REG DDRB
00161 #define DDB2_REG DDRB
00162 #define DDB3_REG DDRB
00163 #define DDB4_REG DDRB
00164 #define DDB5_REG DDRB
00165 #define DDB6_REG DDRB
00166 #define DDB7_REG DDRB
00167
00168
00169 #define XDIV0_REG XDIV
00170 #define XDIV1_REG XDIV
00171 #define XDIV2_REG XDIV
00172 #define XDIV3_REG XDIV
00173 #define XDIV4_REG XDIV
00174 #define XDIV5_REG XDIV
00175 #define XDIV6_REG XDIV
00176 #define XDIVEN_REG XDIV
00177
00178
00179 #define EEDR0_REG EEDR
00180 #define EEDR1_REG EEDR
00181 #define EEDR2_REG EEDR
00182 #define EEDR3_REG EEDR
00183 #define EEDR4_REG EEDR
00184 #define EEDR5_REG EEDR
00185 #define EEDR6_REG EEDR
00186 #define EEDR7_REG EEDR
00187
00188
00189 #define DDA0_REG DDRA
00190 #define DDA1_REG DDRA
00191 #define DDA2_REG DDRA
00192 #define DDA3_REG DDRA
00193 #define DDA4_REG DDRA
00194 #define DDA5_REG DDRA
00195 #define DDA6_REG DDRA
00196 #define DDA7_REG DDRA
00197
00198
00199 #define PWM10_REG TCCR1A
00200 #define PWM11_REG TCCR1A
00201 #define COM1B0_REG TCCR1A
00202 #define COM1B1_REG TCCR1A
00203 #define COM1A0_REG TCCR1A
00204 #define COM1A1_REG TCCR1A
00205
00206
00207 #define DDD0_REG DDRD
00208 #define DDD1_REG DDRD
00209 #define DDD2_REG DDRD
00210 #define DDD3_REG DDRD
00211 #define DDD4_REG DDRD
00212 #define DDD5_REG DDRD
00213 #define DDD6_REG DDRD
00214 #define DDD7_REG DDRD
00215
00216
00217 #define CS10_REG TCCR1B
00218 #define CS11_REG TCCR1B
00219 #define CS12_REG TCCR1B
00220 #define CTC1_REG TCCR1B
00221 #define ICES1_REG TCCR1B
00222 #define ICNC1_REG TCCR1B
00223
00224
00225 #define TOIE2_REG TIMSK
00226 #define OCIE2_REG TIMSK
00227 #define TOIE0_REG TIMSK
00228 #define OCIE0_REG TIMSK
00229 #define TOIE1_REG TIMSK
00230 #define OCIE1B_REG TIMSK
00231 #define OCIE1A_REG TIMSK
00232 #define TICIE1_REG TIMSK
00233
00234
00235 #define INT0_REG EIMSK
00236 #define INT1_REG EIMSK
00237 #define INT2_REG EIMSK
00238 #define INT3_REG EIMSK
00239 #define INT4_REG EIMSK
00240 #define INT5_REG EIMSK
00241 #define INT6_REG EIMSK
00242 #define INT7_REG EIMSK
00243
00244
00245 #define ISC40_REG EICR
00246 #define ISC41_REG EICR
00247 #define ISC50_REG EICR
00248 #define ISC51_REG EICR
00249 #define ISC60_REG EICR
00250 #define ISC61_REG EICR
00251 #define ISC70_REG EICR
00252 #define ISC71_REG EICR
00253
00254
00255 #define RAMPZ0_REG RAMPZ
00256
00257
00258 #define SPDR0_REG SPDR
00259 #define SPDR1_REG SPDR
00260 #define SPDR2_REG SPDR
00261 #define SPDR3_REG SPDR
00262 #define SPDR4_REG SPDR
00263 #define SPDR5_REG SPDR
00264 #define SPDR6_REG SPDR
00265 #define SPDR7_REG SPDR
00266
00267
00268 #define WCOL_REG SPSR
00269 #define SPIF_REG SPSR
00270
00271
00272 #define ACIS0_REG ACSR
00273 #define ACIS1_REG ACSR
00274 #define ACIC_REG ACSR
00275 #define ACIE_REG ACSR
00276 #define ACI_REG ACSR
00277 #define ACO_REG ACSR
00278 #define ACD_REG ACSR
00279
00280
00281 #define SP8_REG SPH
00282 #define SP9_REG SPH
00283 #define SP10_REG SPH
00284 #define SP11_REG SPH
00285 #define SP12_REG SPH
00286 #define SP13_REG SPH
00287 #define SP14_REG SPH
00288 #define SP15_REG SPH
00289
00290
00291 #define OCR1BL0_REG OCR1BL
00292 #define OCR1BL1_REG OCR1BL
00293 #define OCR1BL2_REG OCR1BL
00294 #define OCR1BL3_REG OCR1BL
00295 #define OCR1BL4_REG OCR1BL
00296 #define OCR1BL5_REG OCR1BL
00297 #define OCR1BL6_REG OCR1BL
00298 #define OCR1BL7_REG OCR1BL
00299
00300
00301 #define SP0_REG SPL
00302 #define SP1_REG SPL
00303 #define SP2_REG SPL
00304 #define SP3_REG SPL
00305 #define SP4_REG SPL
00306 #define SP5_REG SPL
00307 #define SP6_REG SPL
00308 #define SP7_REG SPL
00309
00310
00311 #define OCR1BH0_REG OCR1BH
00312 #define OCR1BH1_REG OCR1BH
00313 #define OCR1BH2_REG OCR1BH
00314 #define OCR1BH3_REG OCR1BH
00315 #define OCR1BH4_REG OCR1BH
00316 #define OCR1BH5_REG OCR1BH
00317 #define OCR1BH6_REG OCR1BH
00318 #define OCR1BH7_REG OCR1BH
00319
00320
00321 #define PIND0_REG PIND
00322 #define PIND1_REG PIND
00323 #define PIND2_REG PIND
00324 #define PIND3_REG PIND
00325 #define PIND4_REG PIND
00326 #define PIND5_REG PIND
00327 #define PIND6_REG PIND
00328 #define PIND7_REG PIND
00329
00330
00331 #define ICR1L0_REG ICR1L
00332 #define ICR1L1_REG ICR1L
00333 #define ICR1L2_REG ICR1L
00334 #define ICR1L3_REG ICR1L
00335 #define ICR1L4_REG ICR1L
00336 #define ICR1L5_REG ICR1L
00337 #define ICR1L6_REG ICR1L
00338 #define ICR1L7_REG ICR1L
00339
00340
00341 #define DDE0_REG DDRE
00342 #define DDE1_REG DDRE
00343 #define DDE2_REG DDRE
00344 #define DDE3_REG DDRE
00345 #define DDE4_REG DDRE
00346 #define DDE5_REG DDRE
00347 #define DDE6_REG DDRE
00348 #define DDE7_REG DDRE
00349
00350
00351 #define ADC0_REG ADCL
00352 #define ADC1_REG ADCL
00353 #define ADC2_REG ADCL
00354 #define ADC3_REG ADCL
00355 #define ADC4_REG ADCL
00356 #define ADC5_REG ADCL
00357 #define ADC6_REG ADCL
00358 #define ADC7_REG ADCL
00359
00360
00361 #define PORF_REG MCUSR
00362 #define EXTRF_REG MCUSR
00363
00364
00365 #define EERE_REG EECR
00366 #define EEWE_REG EECR
00367 #define EEMWE_REG EECR
00368 #define EERIE_REG EECR
00369
00370
00371 #define TCNT1L0_REG TCNT1L
00372 #define TCNT1L1_REG TCNT1L
00373 #define TCNT1L2_REG TCNT1L
00374 #define TCNT1L3_REG TCNT1L
00375 #define TCNT1L4_REG TCNT1L
00376 #define TCNT1L5_REG TCNT1L
00377 #define TCNT1L6_REG TCNT1L
00378 #define TCNT1L7_REG TCNT1L
00379
00380
00381 #define PORTB0_REG PORTB
00382 #define PORTB1_REG PORTB
00383 #define PORTB2_REG PORTB
00384 #define PORTB3_REG PORTB
00385 #define PORTB4_REG PORTB
00386 #define PORTB5_REG PORTB
00387 #define PORTB6_REG PORTB
00388 #define PORTB7_REG PORTB
00389
00390
00391 #define PORTD0_REG PORTD
00392 #define PORTD1_REG PORTD
00393 #define PORTD2_REG PORTD
00394 #define PORTD3_REG PORTD
00395 #define PORTD4_REG PORTD
00396 #define PORTD5_REG PORTD
00397 #define PORTD6_REG PORTD
00398 #define PORTD7_REG PORTD
00399
00400
00401 #define PORTE0_REG PORTE
00402 #define PORTE1_REG PORTE
00403 #define PORTE2_REG PORTE
00404 #define PORTE3_REG PORTE
00405 #define PORTE4_REG PORTE
00406 #define PORTE5_REG PORTE
00407 #define PORTE6_REG PORTE
00408 #define PORTE7_REG PORTE
00409
00410
00411 #define TCNT1H0_REG TCNT1H
00412 #define TCNT1H1_REG TCNT1H
00413 #define TCNT1H2_REG TCNT1H
00414 #define TCNT1H3_REG TCNT1H
00415 #define TCNT1H4_REG TCNT1H
00416 #define TCNT1H5_REG TCNT1H
00417 #define TCNT1H6_REG TCNT1H
00418 #define TCNT1H7_REG TCNT1H
00419
00420
00421 #define PORTC0_REG PORTC
00422 #define PORTC1_REG PORTC
00423 #define PORTC2_REG PORTC
00424 #define PORTC3_REG PORTC
00425 #define PORTC4_REG PORTC
00426 #define PORTC5_REG PORTC
00427 #define PORTC6_REG PORTC
00428 #define PORTC7_REG PORTC
00429
00430
00431 #define ADC8_REG ADCH
00432 #define ADC9_REG ADCH
00433
00434
00435 #define PORTA0_REG PORTA
00436 #define PORTA1_REG PORTA
00437 #define PORTA2_REG PORTA
00438 #define PORTA3_REG PORTA
00439 #define PORTA4_REG PORTA
00440 #define PORTA5_REG PORTA
00441 #define PORTA6_REG PORTA
00442 #define PORTA7_REG PORTA
00443
00444
00445 #define TCNT2_0_REG TCNT2
00446 #define TCNT2_1_REG TCNT2
00447 #define TCNT2_2_REG TCNT2
00448 #define TCNT2_3_REG TCNT2
00449 #define TCNT2_4_REG TCNT2
00450 #define TCNT2_5_REG TCNT2
00451 #define TCNT2_6_REG TCNT2
00452 #define TCNT2_7_REG TCNT2
00453
00454
00455 #define TCNT0_0_REG TCNT0
00456 #define TCNT0_1_REG TCNT0
00457 #define TCNT0_2_REG TCNT0
00458 #define TCNT0_3_REG TCNT0
00459 #define TCNT0_4_REG TCNT0
00460 #define TCNT0_5_REG TCNT0
00461 #define TCNT0_6_REG TCNT0
00462 #define TCNT0_7_REG TCNT0
00463
00464
00465 #define UDR0_REG UDR
00466 #define UDR1_REG UDR
00467 #define UDR2_REG UDR
00468 #define UDR3_REG UDR
00469 #define UDR4_REG UDR
00470 #define UDR5_REG UDR
00471 #define UDR6_REG UDR
00472 #define UDR7_REG UDR
00473
00474
00475 #define UBRR0_REG UBRR
00476 #define UBRR1_REG UBRR
00477 #define UBRR2_REG UBRR
00478 #define UBRR3_REG UBRR
00479 #define UBRR4_REG UBRR
00480 #define UBRR5_REG UBRR
00481 #define UBRR6_REG UBRR
00482 #define UBRR7_REG UBRR
00483
00484
00485 #define ADPS0_REG ADCSR
00486 #define ADPS1_REG ADCSR
00487 #define ADPS2_REG ADCSR
00488 #define ADIE_REG ADCSR
00489 #define ADIF_REG ADCSR
00490 #define ADSC_REG ADCSR
00491 #define ADEN_REG ADCSR
00492
00493
00494 #define CS20_REG TCCR2
00495 #define CS21_REG TCCR2
00496 #define CS22_REG TCCR2
00497 #define CTC2_REG TCCR2
00498 #define COM20_REG TCCR2
00499 #define COM21_REG TCCR2
00500 #define PWM2_REG TCCR2
00501
00502
00503 #define TOV2_REG TIFR
00504 #define OCF2_REG TIFR
00505 #define TOV0_REG TIFR
00506 #define OCF0_REG TIFR
00507 #define TOV1_REG TIFR
00508 #define OCF1B_REG TIFR
00509 #define OCF1A_REG TIFR
00510 #define ICF1_REG TIFR
00511
00512
00513 #define TXB8_REG UCR
00514 #define RXB8_REG UCR
00515 #define CHR9_REG UCR
00516 #define TXEN_REG UCR
00517 #define RXEN_REG UCR
00518 #define UDRIE_REG UCR
00519 #define TXCIE_REG UCR
00520 #define RXCIE_REG UCR
00521
00522
00523 #define EEAR8_REG EEARH
00524 #define EEAR9_REG EEARH
00525 #define EEAR10_REG EEARH
00526 #define EEAR11_REG EEARH
00527
00528
00529 #define EEARL0_REG EEARL
00530 #define EEARL1_REG EEARL
00531 #define EEARL2_REG EEARL
00532 #define EEARL3_REG EEARL
00533 #define EEARL4_REG EEARL
00534 #define EEARL5_REG EEARL
00535 #define EEARL6_REG EEARL
00536 #define EEARL7_REG EEARL
00537
00538
00539 #define PINB0_REG PINB
00540 #define PINB1_REG PINB
00541 #define PINB2_REG PINB
00542 #define PINB3_REG PINB
00543 #define PINB4_REG PINB
00544 #define PINB5_REG PINB
00545 #define PINB6_REG PINB
00546 #define PINB7_REG PINB
00547
00548
00549 #define INTF4_REG EIFR
00550 #define INTF5_REG EIFR
00551 #define INTF6_REG EIFR
00552 #define INTF7_REG EIFR
00553
00554
00555 #define PINF0_REG PINF
00556 #define PINF1_REG PINF
00557 #define PINF2_REG PINF
00558 #define PINF3_REG PINF
00559 #define PINF4_REG PINF
00560 #define PINF5_REG PINF
00561 #define PINF6_REG PINF
00562 #define PINF7_REG PINF
00563
00564
00565 #define PINE0_REG PINE
00566 #define PINE1_REG PINE
00567 #define PINE2_REG PINE
00568 #define PINE3_REG PINE
00569 #define PINE4_REG PINE
00570 #define PINE5_REG PINE
00571 #define PINE6_REG PINE
00572 #define PINE7_REG PINE
00573
00574
00575 #define SM0_REG MCUCR
00576 #define SM1_REG MCUCR
00577 #define SE_REG MCUCR
00578 #define SRW_REG MCUCR
00579 #define SRE_REG MCUCR
00580
00581
00582 #define OCR1AH0_REG OCR1AH
00583 #define OCR1AH1_REG OCR1AH
00584 #define OCR1AH2_REG OCR1AH
00585 #define OCR1AH3_REG OCR1AH
00586 #define OCR1AH4_REG OCR1AH
00587 #define OCR1AH5_REG OCR1AH
00588 #define OCR1AH6_REG OCR1AH
00589 #define OCR1AH7_REG OCR1AH
00590
00591
00592 #define OCR1AL0_REG OCR1AL
00593 #define OCR1AL1_REG OCR1AL
00594 #define OCR1AL2_REG OCR1AL
00595 #define OCR1AL3_REG OCR1AL
00596 #define OCR1AL4_REG OCR1AL
00597 #define OCR1AL5_REG OCR1AL
00598 #define OCR1AL6_REG OCR1AL
00599 #define OCR1AL7_REG OCR1AL
00600
00601
00602 #define SPR0_REG SPCR
00603 #define SPR1_REG SPCR
00604 #define CPHA_REG SPCR
00605 #define CPOL_REG SPCR
00606 #define MSTR_REG SPCR
00607 #define DORD_REG SPCR
00608 #define SPE_REG SPCR
00609 #define SPIE_REG SPCR
00610
00611
00612 #define OR_REG USR
00613 #define FE_REG USR
00614 #define UDRE_REG USR
00615 #define TXC_REG USR
00616 #define RXC_REG USR
00617
00618
00619 #define OCR0_0_REG OCR0
00620 #define OCR0_1_REG OCR0
00621 #define OCR0_2_REG OCR0
00622 #define OCR0_3_REG OCR0
00623 #define OCR0_4_REG OCR0
00624 #define OCR0_5_REG OCR0
00625 #define OCR0_6_REG OCR0
00626 #define OCR0_7_REG OCR0
00627
00628
00629 #define PINA0_REG PINA
00630 #define PINA1_REG PINA
00631 #define PINA2_REG PINA
00632 #define PINA3_REG PINA
00633 #define PINA4_REG PINA
00634 #define PINA5_REG PINA
00635 #define PINA6_REG PINA
00636 #define PINA7_REG PINA
00637
00638
00639 #define OCR2_0_REG OCR2
00640 #define OCR2_1_REG OCR2
00641 #define OCR2_2_REG OCR2
00642 #define OCR2_3_REG OCR2
00643 #define OCR2_4_REG OCR2
00644 #define OCR2_5_REG OCR2
00645 #define OCR2_6_REG OCR2
00646 #define OCR2_7_REG OCR2
00647
00648
00649 #define TCR0UB_REG ASSR
00650 #define OCR0UB_REG ASSR
00651 #define TCN0UB_REG ASSR
00652 #define AS0_REG ASSR
00653
00654
00655 #define AD0_PORT PORTA
00656 #define AD0_BIT 0
00657
00658 #define AD1_PORT PORTA
00659 #define AD1_BIT 1
00660
00661 #define AD2_PORT PORTA
00662 #define AD2_BIT 2
00663
00664 #define AD3_PORT PORTA
00665 #define AD3_BIT 3
00666
00667 #define AD4_PORT PORTA
00668 #define AD4_BIT 4
00669
00670 #define AD5_PORT PORTA
00671 #define AD5_BIT 5
00672
00673 #define AD6_PORT PORTA
00674 #define AD6_BIT 6
00675
00676 #define AD7_PORT PORTA
00677 #define AD7_BIT 7
00678
00679 #define SS_PORT PORTB
00680 #define SS_BIT 0
00681
00682 #define SCK_PORT PORTB
00683 #define SCK_BIT 1
00684
00685 #define MOSI_PORT PORTB
00686 #define MOSI_BIT 2
00687
00688 #define MISO_PORT PORTB
00689 #define MISO_BIT 3
00690
00691 #define OC0_PORT PORTB
00692 #define OC0_BIT 4
00693 #define PWM0_PORT PORTB
00694 #define PWM0_BIT 4
00695
00696 #define OC1A_PORT PORTB
00697 #define OC1A_BIT 5
00698 #define PWM1A_PORT PORTB
00699 #define PWM1A_BIT 5
00700
00701 #define OC1B_PORT PORTB
00702 #define OC1B_BIT 6
00703 #define PWM1B_PORT PORTB
00704 #define PWM1B_BIT 6
00705
00706 #define OC2_PORT PORTB
00707 #define OC2_BIT 7
00708 #define PWM2_PORT PORTB
00709 #define PWM2_BIT 7
00710 #define OC1C_PORT PORTB
00711 #define OC1C_BIT 7
00712
00713 #define A8_PORT PORTC
00714 #define A8_BIT 0
00715
00716 #define A9_PORT PORTC
00717 #define A9_BIT 1
00718
00719 #define A10_PORT PORTC
00720 #define A10_BIT 2
00721
00722 #define A11_PORT PORTC
00723 #define A11_BIT 3
00724
00725 #define A12_PORT PORTC
00726 #define A12_BIT 4
00727
00728 #define A13_PORT PORTC
00729 #define A13_BIT 5
00730
00731 #define A14_PORT PORTC
00732 #define A14_BIT 6
00733
00734 #define A15_PORT PORTC
00735 #define A15_BIT 7
00736
00737 #define INT0_PORT PORTD
00738 #define INT0_BIT 0
00739
00740 #define INT1_PORT PORTD
00741 #define INT1_BIT 1
00742
00743 #define INT2_PORT PORTD
00744 #define INT2_BIT 2
00745
00746 #define INT3_PORT PORTD
00747 #define INT3_BIT 3
00748
00749 #define IC1_PORT PORTD
00750 #define IC1_BIT 4
00751
00752
00753 #define T1_PORT PORTD
00754 #define T1_BIT 6
00755
00756 #define T2_PORT PORTD
00757 #define T2_BIT 7
00758
00759 #define RXD0_PORT PORTE
00760 #define RXD0_BIT 0
00761 #define PDI_PORT PORTE
00762 #define PDI_BIT 0
00763
00764 #define TXD0_PORT PORTE
00765 #define TXD0_BIT 1
00766 #define PDO_PORT PORTE
00767 #define PDO_BIT 1
00768
00769 #define AC+_PORT PORTE
00770 #define AC+_BIT 2
00771
00772 #define AC-_PORT PORTE
00773 #define AC-_BIT 3
00774
00775 #define INT4_PORT PORTE
00776 #define INT4_BIT 4
00777
00778 #define INT5_PORT PORTE
00779 #define INT5_BIT 5
00780
00781 #define INT6_PORT PORTE
00782 #define INT6_BIT 6
00783
00784 #define INT7_PORT PORTE
00785 #define INT7_BIT 7
00786
00787 #define ADC0_PORT PORTF
00788 #define ADC0_BIT 0
00789
00790 #define ADC1_PORT PORTF
00791 #define ADC1_BIT 1
00792
00793 #define ADC2_PORT PORTF
00794 #define ADC2_BIT 2
00795
00796 #define ADC3_PORT PORTF
00797 #define ADC3_BIT 3
00798
00799 #define ADC4_PORT PORTF
00800 #define ADC4_BIT 4
00801
00802 #define ADC5_PORT PORTF
00803 #define ADC5_BIT 5
00804
00805 #define ADC6_PORT PORTF
00806 #define ADC6_BIT 6
00807
00808 #define ADC7_PORT PORTF
00809 #define ADC7_BIT 7
00810
00811