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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER0A_AVAILABLE
00069 #define TIMER0B_AVAILABLE
00070 #define TIMER1_AVAILABLE
00071 #define TIMER1A_AVAILABLE
00072 #define TIMER1B_AVAILABLE
00073 #define TIMER1C_AVAILABLE
00074
00075
00076 #define SIG_OVERFLOW0_NUM 0
00077 #define SIG_OVERFLOW1_NUM 1
00078 #define SIG_OVERFLOW_TOTAL_NUM 2
00079
00080
00081 #define SIG_OUTPUT_COMPARE0A_NUM 0
00082 #define SIG_OUTPUT_COMPARE0B_NUM 1
00083 #define SIG_OUTPUT_COMPARE1A_NUM 2
00084 #define SIG_OUTPUT_COMPARE1B_NUM 3
00085 #define SIG_OUTPUT_COMPARE1C_NUM 4
00086 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 5
00087
00088
00089 #define PWM0A_NUM 0
00090 #define PWM0B_NUM 1
00091 #define PWM1A_NUM 2
00092 #define PWM1B_NUM 3
00093 #define PWM1C_NUM 4
00094 #define PWM_TOTAL_NUM 5
00095
00096
00097 #define SIG_INPUT_CAPTURE1_NUM 0
00098 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00099
00100
00101
00102 #define SUSPE_REG UDIEN
00103 #define SOFE_REG UDIEN
00104 #define EORSTE_REG UDIEN
00105 #define WAKEUPE_REG UDIEN
00106 #define EORSME_REG UDIEN
00107 #define UPRSME_REG UDIEN
00108
00109
00110 #define WDP0_REG WDTCSR
00111 #define WDP1_REG WDTCSR
00112 #define WDP2_REG WDTCSR
00113 #define WDE_REG WDTCSR
00114 #define WDCE_REG WDTCSR
00115 #define WDP3_REG WDTCSR
00116 #define WDIE_REG WDTCSR
00117 #define WDIF_REG WDTCSR
00118
00119
00120 #define EEDR0_REG EEDR
00121 #define EEDR1_REG EEDR
00122 #define EEDR2_REG EEDR
00123 #define EEDR3_REG EEDR
00124 #define EEDR4_REG EEDR
00125 #define EEDR5_REG EEDR
00126 #define EEDR6_REG EEDR
00127 #define EEDR7_REG EEDR
00128
00129
00130 #define ACIS0_REG ACSR
00131 #define ACIS1_REG ACSR
00132 #define ACIC_REG ACSR
00133 #define ACIE_REG ACSR
00134 #define ACI_REG ACSR
00135 #define ACO_REG ACSR
00136 #define ACBG_REG ACSR
00137 #define ACD_REG ACSR
00138
00139
00140 #define PS2EN_REG PS2CON
00141
00142
00143 #define EPRST0_REG UERST
00144 #define EPRST1_REG UERST
00145 #define EPRST2_REG UERST
00146 #define EPRST3_REG UERST
00147 #define EPRST4_REG UERST
00148
00149
00150 #define ALLOC_REG UECFG1X
00151 #define EPBK0_REG UECFG1X
00152 #define EPBK1_REG UECFG1X
00153 #define EPSIZE0_REG UECFG1X
00154 #define EPSIZE1_REG UECFG1X
00155 #define EPSIZE2_REG UECFG1X
00156
00157
00158 #define UDR1_0_REG UDR1
00159 #define UDR1_1_REG UDR1
00160 #define UDR1_2_REG UDR1
00161 #define UDR1_3_REG UDR1
00162 #define UDR1_4_REG UDR1
00163 #define UDR1_5_REG UDR1
00164 #define UDR1_6_REG UDR1
00165 #define UDR1_7_REG UDR1
00166
00167
00168 #define SPDR0_REG SPDR
00169 #define SPDR1_REG SPDR
00170 #define SPDR2_REG SPDR
00171 #define SPDR3_REG SPDR
00172 #define SPDR4_REG SPDR
00173 #define SPDR5_REG SPDR
00174 #define SPDR6_REG SPDR
00175 #define SPDR7_REG SPDR
00176
00177
00178 #define SPI2X_REG SPSR
00179 #define WCOL_REG SPSR
00180 #define SPIF_REG SPSR
00181
00182
00183 #define ICR1H0_REG ICR1H
00184 #define ICR1H1_REG ICR1H
00185 #define ICR1H2_REG ICR1H
00186 #define ICR1H3_REG ICR1H
00187 #define ICR1H4_REG ICR1H
00188 #define ICR1H5_REG ICR1H
00189 #define ICR1H6_REG ICR1H
00190 #define ICR1H7_REG ICR1H
00191
00192
00193 #define ICR1L0_REG ICR1L
00194 #define ICR1L1_REG ICR1L
00195 #define ICR1L2_REG ICR1L
00196 #define ICR1L3_REG ICR1L
00197 #define ICR1L4_REG ICR1L
00198 #define ICR1L5_REG ICR1L
00199 #define ICR1L6_REG ICR1L
00200 #define ICR1L7_REG ICR1L
00201
00202
00203 #define EPINT0_REG UEINT
00204 #define EPINT1_REG UEINT
00205 #define EPINT2_REG UEINT
00206 #define EPINT3_REG UEINT
00207 #define EPINT4_REG UEINT
00208
00209
00210 #define TCNT1L0_REG TCNT1L
00211 #define TCNT1L1_REG TCNT1L
00212 #define TCNT1L2_REG TCNT1L
00213 #define TCNT1L3_REG TCNT1L
00214 #define TCNT1L4_REG TCNT1L
00215 #define TCNT1L5_REG TCNT1L
00216 #define TCNT1L6_REG TCNT1L
00217 #define TCNT1L7_REG TCNT1L
00218
00219
00220 #define PORTD0_REG PORTD
00221 #define PORTD1_REG PORTD
00222 #define PORTD2_REG PORTD
00223 #define PORTD3_REG PORTD
00224 #define PORTD4_REG PORTD
00225 #define PORTD5_REG PORTD
00226 #define PORTD6_REG PORTD
00227 #define PORTD7_REG PORTD
00228
00229
00230 #define TCNT1H0_REG TCNT1H
00231 #define TCNT1H1_REG TCNT1H
00232 #define TCNT1H2_REG TCNT1H
00233 #define TCNT1H3_REG TCNT1H
00234 #define TCNT1H4_REG TCNT1H
00235 #define TCNT1H5_REG TCNT1H
00236 #define TCNT1H6_REG TCNT1H
00237 #define TCNT1H7_REG TCNT1H
00238
00239
00240 #define PORTC0_REG PORTC
00241 #define PORTC1_REG PORTC
00242 #define PORTC2_REG PORTC
00243 #define PORTC4_REG PORTC
00244 #define PORTC5_REG PORTC
00245 #define PORTC6_REG PORTC
00246 #define PORTC7_REG PORTC
00247
00248
00249 #define REGDIS_REG REGCR
00250
00251
00252 #define ISC40_REG EICRB
00253 #define ISC41_REG EICRB
00254 #define ISC50_REG EICRB
00255 #define ISC51_REG EICRB
00256 #define ISC60_REG EICRB
00257 #define ISC61_REG EICRB
00258 #define ISC70_REG EICRB
00259 #define ISC71_REG EICRB
00260
00261
00262 #define DAT0_REG UEDATX
00263 #define DAT1_REG UEDATX
00264 #define DAT2_REG UEDATX
00265 #define DAT3_REG UEDATX
00266 #define DAT4_REG UEDATX
00267 #define DAT5_REG UEDATX
00268 #define DAT6_REG UEDATX
00269 #define DAT7_REG UEDATX
00270
00271
00272 #define ISC00_REG EICRA
00273 #define ISC01_REG EICRA
00274 #define ISC10_REG EICRA
00275 #define ISC11_REG EICRA
00276 #define ISC20_REG EICRA
00277 #define ISC21_REG EICRA
00278 #define ISC30_REG EICRA
00279 #define ISC31_REG EICRA
00280
00281
00282 #define EPDIR_REG UECFG0X
00283 #define EPTYPE0_REG UECFG0X
00284 #define EPTYPE1_REG UECFG0X
00285
00286
00287 #define AIN0D_REG DIDR1
00288 #define AIN1D_REG DIDR1
00289
00290
00291 #define EXCKSEL0_REG CLKSEL1
00292 #define EXCKSEL1_REG CLKSEL1
00293 #define EXCKSEL2_REG CLKSEL1
00294 #define EXCKSEL3_REG CLKSEL1
00295 #define RCCKSEL0_REG CLKSEL1
00296 #define RCCKSEL1_REG CLKSEL1
00297 #define RCCKSEL2_REG CLKSEL1
00298 #define RCCKSEL3_REG CLKSEL1
00299
00300
00301 #define CLKS_REG CLKSEL0
00302 #define EXTE_REG CLKSEL0
00303 #define RCE_REG CLKSEL0
00304 #define EXSUT0_REG CLKSEL0
00305 #define EXSUT1_REG CLKSEL0
00306 #define RCSUT0_REG CLKSEL0
00307 #define RCSUT1_REG CLKSEL0
00308
00309
00310 #define CLKPS0_REG CLKPR
00311 #define CLKPS1_REG CLKPR
00312 #define CLKPS2_REG CLKPR
00313 #define CLKPS3_REG CLKPR
00314 #define CLKPCE_REG CLKPR
00315
00316
00317 #define DMI_REG UPOE
00318 #define DPI_REG UPOE
00319 #define DATAI_REG UPOE
00320 #define SCKI_REG UPOE
00321 #define UPDRV0_REG UPOE
00322 #define UPDRV1_REG UPOE
00323 #define UPWE0_REG UPOE
00324 #define UPWE1_REG UPOE
00325
00326
00327 #define C_REG SREG
00328 #define Z_REG SREG
00329 #define N_REG SREG
00330 #define V_REG SREG
00331 #define S_REG SREG
00332 #define H_REG SREG
00333 #define T_REG SREG
00334 #define I_REG SREG
00335
00336
00337 #define EPNUM0_REG UENUM
00338 #define EPNUM1_REG UENUM
00339 #define EPNUM2_REG UENUM
00340
00341
00342 #define UBRR1_0_REG UBRR1L
00343 #define UBRR1_1_REG UBRR1L
00344 #define UBRR1_2_REG UBRR1L
00345 #define UBRR1_3_REG UBRR1L
00346 #define UBRR1_4_REG UBRR1L
00347 #define UBRR1_5_REG UBRR1L
00348 #define UBRR1_6_REG UBRR1L
00349 #define UBRR1_7_REG UBRR1L
00350
00351
00352 #define DDC0_REG DDRC
00353 #define DDC1_REG DDRC
00354 #define DDC2_REG DDRC
00355 #define DDC4_REG DDRC
00356 #define DDC5_REG DDRC
00357 #define DDC6_REG DDRC
00358 #define DDC7_REG DDRC
00359
00360
00361 #define WGM10_REG TCCR1A
00362 #define WGM11_REG TCCR1A
00363 #define COM1C0_REG TCCR1A
00364 #define COM1C1_REG TCCR1A
00365 #define COM1B0_REG TCCR1A
00366 #define COM1B1_REG TCCR1A
00367 #define COM1A0_REG TCCR1A
00368 #define COM1A1_REG TCCR1A
00369
00370
00371 #define FOC1C_REG TCCR1C
00372 #define FOC1B_REG TCCR1C
00373 #define FOC1A_REG TCCR1C
00374
00375
00376 #define CS10_REG TCCR1B
00377 #define CS11_REG TCCR1B
00378 #define CS12_REG TCCR1B
00379 #define WGM12_REG TCCR1B
00380 #define WGM13_REG TCCR1B
00381 #define ICES1_REG TCCR1B
00382 #define ICNC1_REG TCCR1B
00383
00384
00385 #define CAL0_REG OSCCAL
00386 #define CAL1_REG OSCCAL
00387 #define CAL2_REG OSCCAL
00388 #define CAL3_REG OSCCAL
00389 #define CAL4_REG OSCCAL
00390 #define CAL5_REG OSCCAL
00391 #define CAL6_REG OSCCAL
00392 #define CAL7_REG OSCCAL
00393
00394
00395 #define GPIOR10_REG GPIOR1
00396 #define GPIOR11_REG GPIOR1
00397 #define GPIOR12_REG GPIOR1
00398 #define GPIOR13_REG GPIOR1
00399 #define GPIOR14_REG GPIOR1
00400 #define GPIOR15_REG GPIOR1
00401 #define GPIOR16_REG GPIOR1
00402 #define GPIOR17_REG GPIOR1
00403
00404
00405 #define GPIOR00_REG GPIOR0
00406 #define GPIOR01_REG GPIOR0
00407 #define GPIOR02_REG GPIOR0
00408 #define GPIOR03_REG GPIOR0
00409 #define GPIOR04_REG GPIOR0
00410 #define GPIOR05_REG GPIOR0
00411 #define GPIOR06_REG GPIOR0
00412 #define GPIOR07_REG GPIOR0
00413
00414
00415 #define GPIOR20_REG GPIOR2
00416 #define GPIOR21_REG GPIOR2
00417 #define GPIOR22_REG GPIOR2
00418 #define GPIOR23_REG GPIOR2
00419 #define GPIOR24_REG GPIOR2
00420 #define GPIOR25_REG GPIOR2
00421 #define GPIOR26_REG GPIOR2
00422 #define GPIOR27_REG GPIOR2
00423
00424
00425 #define DETACH_REG UDCON
00426 #define RMWKUP_REG UDCON
00427 #define RSTCPU_REG UDCON
00428
00429
00430 #define WCLKD0_REG WDTCKD
00431 #define WCLKD1_REG WDTCKD
00432 #define WDEWIE_REG WDTCKD
00433 #define WDEWIF_REG WDTCKD
00434
00435
00436 #define PCIE0_REG PCICR
00437 #define PCIE1_REG PCICR
00438
00439
00440 #define TCNT0_0_REG TCNT0
00441 #define TCNT0_1_REG TCNT0
00442 #define TCNT0_2_REG TCNT0
00443 #define TCNT0_3_REG TCNT0
00444 #define TCNT0_4_REG TCNT0
00445 #define TCNT0_5_REG TCNT0
00446 #define TCNT0_6_REG TCNT0
00447 #define TCNT0_7_REG TCNT0
00448
00449
00450 #define SUSPI_REG UDINT
00451 #define SOFI_REG UDINT
00452 #define EORSTI_REG UDINT
00453 #define WAKEUPI_REG UDINT
00454 #define EORSMI_REG UDINT
00455 #define UPRSMI_REG UDINT
00456
00457
00458 #define CS00_REG TCCR0B
00459 #define CS01_REG TCCR0B
00460 #define CS02_REG TCCR0B
00461 #define WGM02_REG TCCR0B
00462 #define FOC0B_REG TCCR0B
00463 #define FOC0A_REG TCCR0B
00464
00465
00466 #define FNCERR_REG UDMFN
00467
00468
00469 #define WGM00_REG TCCR0A
00470 #define WGM01_REG TCCR0A
00471 #define COM0B0_REG TCCR0A
00472 #define COM0B1_REG TCCR0A
00473 #define COM0A0_REG TCCR0A
00474 #define COM0A1_REG TCCR0A
00475
00476
00477 #define DWDR0_REG DWDR
00478 #define DWDR1_REG DWDR
00479 #define DWDR2_REG DWDR
00480 #define DWDR3_REG DWDR
00481 #define DWDR4_REG DWDR
00482 #define DWDR5_REG DWDR
00483 #define DWDR6_REG DWDR
00484 #define DWDR7_REG DWDR
00485
00486
00487 #define SPR0_REG SPCR
00488 #define SPR1_REG SPCR
00489 #define CPHA_REG SPCR
00490 #define CPOL_REG SPCR
00491 #define MSTR_REG SPCR
00492 #define DORD_REG SPCR
00493 #define SPE_REG SPCR
00494 #define SPIE_REG SPCR
00495
00496
00497 #define TOV1_REG TIFR1
00498 #define OCF1A_REG TIFR1
00499 #define OCF1B_REG TIFR1
00500 #define OCF1C_REG TIFR1
00501 #define ICF1_REG TIFR1
00502
00503
00504 #define BYCT0_REG UEBCLX
00505 #define BYCT1_REG UEBCLX
00506 #define BYCT2_REG UEBCLX
00507 #define BYCT3_REG UEBCLX
00508 #define BYCT4_REG UEBCLX
00509 #define BYCT5_REG UEBCLX
00510 #define BYCT6_REG UEBCLX
00511 #define BYCT7_REG UEBCLX
00512
00513
00514 #define CURRBK0_REG UESTA1X
00515 #define CURRBK1_REG UESTA1X
00516 #define CTRLDIR_REG UESTA1X
00517
00518
00519 #define PSRSYNC_REG GTCCR
00520 #define TSM_REG GTCCR
00521
00522
00523 #define SP8_REG SPH
00524 #define SP9_REG SPH
00525 #define SP10_REG SPH
00526 #define SP11_REG SPH
00527 #define SP12_REG SPH
00528 #define SP13_REG SPH
00529 #define SP14_REG SPH
00530 #define SP15_REG SPH
00531
00532
00533 #define TXINI_REG UEINTX
00534 #define STALLEDI_REG UEINTX
00535 #define RXOUTI_REG UEINTX
00536 #define RXSTPI_REG UEINTX
00537 #define NAKOUTI_REG UEINTX
00538 #define RWAL_REG UEINTX
00539 #define NAKINI_REG UEINTX
00540 #define FIFOCON_REG UEINTX
00541
00542
00543 #define OCR1BL0_REG OCR1BL
00544 #define OCR1BL1_REG OCR1BL
00545 #define OCR1BL2_REG OCR1BL
00546 #define OCR1BL3_REG OCR1BL
00547 #define OCR1BL4_REG OCR1BL
00548 #define OCR1BL5_REG OCR1BL
00549 #define OCR1BL6_REG OCR1BL
00550 #define OCR1BL7_REG OCR1BL
00551
00552
00553 #define OCR1BH0_REG OCR1BH
00554 #define OCR1BH1_REG OCR1BH
00555 #define OCR1BH2_REG OCR1BH
00556 #define OCR1BH3_REG OCR1BH
00557 #define OCR1BH4_REG OCR1BH
00558 #define OCR1BH5_REG OCR1BH
00559 #define OCR1BH6_REG OCR1BH
00560 #define OCR1BH7_REG OCR1BH
00561
00562
00563 #define SP0_REG SPL
00564 #define SP1_REG SPL
00565 #define SP2_REG SPL
00566 #define SP3_REG SPL
00567 #define SP4_REG SPL
00568 #define SP5_REG SPL
00569 #define SP6_REG SPL
00570 #define SP7_REG SPL
00571
00572
00573 #define FRZCLK_REG USBCON
00574 #define USBE_REG USBCON
00575
00576
00577 #define PORF_REG MCUSR
00578 #define EXTRF_REG MCUSR
00579 #define BORF_REG MCUSR
00580 #define WDRF_REG MCUSR
00581 #define USBRF_REG MCUSR
00582
00583
00584 #define EERE_REG EECR
00585 #define EEPE_REG EECR
00586 #define EEMPE_REG EECR
00587 #define EERIE_REG EECR
00588 #define EEPM0_REG EECR
00589 #define EEPM1_REG EECR
00590
00591
00592 #define SE_REG SMCR
00593 #define SM0_REG SMCR
00594 #define SM1_REG SMCR
00595 #define SM2_REG SMCR
00596
00597
00598 #define PCIF0_REG PCIFR
00599 #define PCIF1_REG PCIFR
00600
00601
00602 #define EPEN_REG UECONX
00603 #define RSTDT_REG UECONX
00604 #define STALLRQC_REG UECONX
00605 #define STALLRQ_REG UECONX
00606
00607
00608 #define EEAR8_REG EEARH
00609 #define EEAR9_REG EEARH
00610 #define EEAR10_REG EEARH
00611 #define EEAR11_REG EEARH
00612
00613
00614 #define EEAR0_REG EEARL
00615 #define EEAR1_REG EEARL
00616 #define EEAR2_REG EEARL
00617 #define EEAR3_REG EEARL
00618 #define EEAR4_REG EEARL
00619 #define EEAR5_REG EEARL
00620 #define EEAR6_REG EEARL
00621 #define EEAR7_REG EEARL
00622
00623
00624 #define IVCE_REG MCUCR
00625 #define IVSEL_REG MCUCR
00626 #define PUD_REG MCUCR
00627
00628
00629 #define OCR1CL0_REG OCR1CL
00630 #define OCR1CL1_REG OCR1CL
00631 #define OCR1CL2_REG OCR1CL
00632 #define OCR1CL3_REG OCR1CL
00633 #define OCR1CL4_REG OCR1CL
00634 #define OCR1CL5_REG OCR1CL
00635 #define OCR1CL6_REG OCR1CL
00636 #define OCR1CL7_REG OCR1CL
00637
00638
00639 #define OCR1CH0_REG OCR1CH
00640 #define OCR1CH1_REG OCR1CH
00641 #define OCR1CH2_REG OCR1CH
00642 #define OCR1CH3_REG OCR1CH
00643 #define OCR1CH4_REG OCR1CH
00644 #define OCR1CH5_REG OCR1CH
00645 #define OCR1CH6_REG OCR1CH
00646 #define OCR1CH7_REG OCR1CH
00647
00648
00649 #define TXINE_REG UEIENX
00650 #define STALLEDE_REG UEIENX
00651 #define RXOUTE_REG UEIENX
00652 #define RXSTPE_REG UEIENX
00653 #define NAKOUTE_REG UEIENX
00654 #define NAKINE_REG UEIENX
00655 #define FLERRE_REG UEIENX
00656
00657
00658 #define TXB81_REG UCSR1B
00659 #define RXB81_REG UCSR1B
00660 #define UCSZ12_REG UCSR1B
00661 #define TXEN1_REG UCSR1B
00662 #define RXEN1_REG UCSR1B
00663 #define UDRIE1_REG UCSR1B
00664 #define TXCIE1_REG UCSR1B
00665 #define RXCIE1_REG UCSR1B
00666
00667
00668 #define UCPOL1_REG UCSR1C
00669 #define UCSZ10_REG UCSR1C
00670 #define UCSZ11_REG UCSR1C
00671 #define USBS1_REG UCSR1C
00672 #define UPM10_REG UCSR1C
00673 #define UPM11_REG UCSR1C
00674 #define UMSEL10_REG UCSR1C
00675 #define UMSEL11_REG UCSR1C
00676
00677
00678 #define MPCM1_REG UCSR1A
00679 #define U2X1_REG UCSR1A
00680 #define UPE1_REG UCSR1A
00681 #define DOR1_REG UCSR1A
00682 #define FE1_REG UCSR1A
00683 #define UDRE1_REG UCSR1A
00684 #define TXC1_REG UCSR1A
00685 #define RXC1_REG UCSR1A
00686
00687
00688 #define RTSEN_REG UCSR1D
00689 #define CTSEN_REG UCSR1D
00690
00691
00692 #define DDB0_REG DDRB
00693 #define DDB1_REG DDRB
00694 #define DDB2_REG DDRB
00695 #define DDB3_REG DDRB
00696 #define DDB4_REG DDRB
00697 #define DDB5_REG DDRB
00698 #define DDB6_REG DDRB
00699 #define DDB7_REG DDRB
00700
00701
00702 #define EIND0_REG EIND
00703
00704
00705 #define FNUM0_REG UDFNUML
00706 #define FNUM1_REG UDFNUML
00707 #define FNUM2_REG UDFNUML
00708 #define FNUM3_REG UDFNUML
00709 #define FNUM4_REG UDFNUML
00710 #define FNUM5_REG UDFNUML
00711 #define FNUM6_REG UDFNUML
00712 #define FNUM7_REG UDFNUML
00713
00714
00715 #define FNUM8_REG UDFNUMH
00716 #define FNUM9_REG UDFNUMH
00717 #define FNUM10_REG UDFNUMH
00718
00719
00720 #define INT0_REG EIMSK
00721 #define INT1_REG EIMSK
00722 #define INT2_REG EIMSK
00723 #define INT3_REG EIMSK
00724 #define INT4_REG EIMSK
00725 #define INT5_REG EIMSK
00726 #define INT6_REG EIMSK
00727 #define INT7_REG EIMSK
00728
00729
00730 #define PRSPI_REG PRR0
00731 #define PRTIM1_REG PRR0
00732 #define PRTIM0_REG PRR0
00733
00734
00735 #define UBRR1_8_REG UBRR1H
00736 #define UBRR1_9_REG UBRR1H
00737 #define UBRR1_10_REG UBRR1H
00738 #define UBRR1_11_REG UBRR1H
00739
00740
00741 #define OCROA_0_REG OCR0A
00742 #define OCROA_1_REG OCR0A
00743 #define OCROA_2_REG OCR0A
00744 #define OCROA_3_REG OCR0A
00745 #define OCROA_4_REG OCR0A
00746 #define OCROA_5_REG OCR0A
00747 #define OCROA_6_REG OCR0A
00748 #define OCROA_7_REG OCR0A
00749
00750
00751 #define OCR0B_0_REG OCR0B
00752 #define OCR0B_1_REG OCR0B
00753 #define OCR0B_2_REG OCR0B
00754 #define OCR0B_3_REG OCR0B
00755 #define OCR0B_4_REG OCR0B
00756 #define OCR0B_5_REG OCR0B
00757 #define OCR0B_6_REG OCR0B
00758 #define OCR0B_7_REG OCR0B
00759
00760
00761 #define DDD0_REG DDRD
00762 #define DDD1_REG DDRD
00763 #define DDD2_REG DDRD
00764 #define DDD3_REG DDRD
00765 #define DDD4_REG DDRD
00766 #define DDD5_REG DDRD
00767 #define DDD6_REG DDRD
00768 #define DDD7_REG DDRD
00769
00770
00771 #define UADD0_REG UDADDR
00772 #define UADD1_REG UDADDR
00773 #define UADD2_REG UDADDR
00774 #define UADD3_REG UDADDR
00775 #define UADD4_REG UDADDR
00776 #define UADD5_REG UDADDR
00777 #define UADD6_REG UDADDR
00778 #define ADDEN_REG UDADDR
00779
00780
00781 #define SPMEN_REG SPMCSR
00782 #define PGERS_REG SPMCSR
00783 #define PGWRT_REG SPMCSR
00784 #define BLBSET_REG SPMCSR
00785 #define RWWSRE_REG SPMCSR
00786 #define SIGRD_REG SPMCSR
00787 #define RWWSB_REG SPMCSR
00788 #define SPMIE_REG SPMCSR
00789
00790
00791 #define NBUSYBK0_REG UESTA0X
00792 #define NBUSYBK1_REG UESTA0X
00793 #define DTSEQ0_REG UESTA0X
00794 #define DTSEQ1_REG UESTA0X
00795 #define UNDERFI_REG UESTA0X
00796 #define OVERFI_REG UESTA0X
00797 #define CFGOK_REG UESTA0X
00798
00799
00800 #define PORTB0_REG PORTB
00801 #define PORTB1_REG PORTB
00802 #define PORTB2_REG PORTB
00803 #define PORTB3_REG PORTB
00804 #define PORTB4_REG PORTB
00805 #define PORTB5_REG PORTB
00806 #define PORTB6_REG PORTB
00807 #define PORTB7_REG PORTB
00808
00809
00810 #define TOIE0_REG TIMSK0
00811 #define OCIE0A_REG TIMSK0
00812 #define OCIE0B_REG TIMSK0
00813
00814
00815 #define TOIE1_REG TIMSK1
00816 #define OCIE1A_REG TIMSK1
00817 #define OCIE1B_REG TIMSK1
00818 #define OCIE1C_REG TIMSK1
00819 #define ICIE1_REG TIMSK1
00820
00821
00822 #define EXTON_REG CLKSTA
00823 #define RCON_REG CLKSTA
00824
00825
00826 #define PLOCK_REG PLLCSR
00827 #define PLLE_REG PLLCSR
00828 #define PLLP0_REG PLLCSR
00829 #define PLLP1_REG PLLCSR
00830 #define PLLP2_REG PLLCSR
00831
00832
00833 #define PCINT0_REG PCMSK0
00834 #define PCINT1_REG PCMSK0
00835 #define PCINT2_REG PCMSK0
00836 #define PCINT3_REG PCMSK0
00837 #define PCINT4_REG PCMSK0
00838 #define PCINT5_REG PCMSK0
00839 #define PCINT6_REG PCMSK0
00840 #define PCINT7_REG PCMSK0
00841
00842
00843 #define PCINT8_REG PCMSK1
00844 #define PCINT9_REG PCMSK1
00845 #define PCINT10_REG PCMSK1
00846 #define PCINT11_REG PCMSK1
00847 #define PCINT12_REG PCMSK1
00848
00849
00850 #define PINC0_REG PINC
00851 #define PINC1_REG PINC
00852 #define PINC2_REG PINC
00853 #define PINC4_REG PINC
00854 #define PINC5_REG PINC
00855 #define PINC6_REG PINC
00856 #define PINC7_REG PINC
00857
00858
00859 #define PINB0_REG PINB
00860 #define PINB1_REG PINB
00861 #define PINB2_REG PINB
00862 #define PINB3_REG PINB
00863 #define PINB4_REG PINB
00864 #define PINB5_REG PINB
00865 #define PINB6_REG PINB
00866 #define PINB7_REG PINB
00867
00868
00869 #define INTF0_REG EIFR
00870 #define INTF1_REG EIFR
00871 #define INTF2_REG EIFR
00872 #define INTF3_REG EIFR
00873 #define INTF4_REG EIFR
00874 #define INTF5_REG EIFR
00875 #define INTF6_REG EIFR
00876 #define INTF7_REG EIFR
00877
00878
00879 #define PIND0_REG PIND
00880 #define PIND1_REG PIND
00881 #define PIND2_REG PIND
00882 #define PIND3_REG PIND
00883 #define PIND4_REG PIND
00884 #define PIND5_REG PIND
00885 #define PIND6_REG PIND
00886 #define PIND7_REG PIND
00887
00888
00889 #define OCR1AH0_REG OCR1AH
00890 #define OCR1AH1_REG OCR1AH
00891 #define OCR1AH2_REG OCR1AH
00892 #define OCR1AH3_REG OCR1AH
00893 #define OCR1AH4_REG OCR1AH
00894 #define OCR1AH5_REG OCR1AH
00895 #define OCR1AH6_REG OCR1AH
00896 #define OCR1AH7_REG OCR1AH
00897
00898
00899 #define OCR1AL0_REG OCR1AL
00900 #define OCR1AL1_REG OCR1AL
00901 #define OCR1AL2_REG OCR1AL
00902 #define OCR1AL3_REG OCR1AL
00903 #define OCR1AL4_REG OCR1AL
00904 #define OCR1AL5_REG OCR1AL
00905 #define OCR1AL6_REG OCR1AL
00906 #define OCR1AL7_REG OCR1AL
00907
00908
00909 #define TOV0_REG TIFR0
00910 #define OCF0A_REG TIFR0
00911 #define OCF0B_REG TIFR0
00912
00913
00914 #define PRUSART1_REG PRR1
00915 #define PRUSB_REG PRR1
00916
00917
00918