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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_FALL 6
00092 #define TIMER3_PRESCALER_DIV_RISE 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 -1
00101 #define TIMER3_PRESCALER_REG_7 -2
00102
00103
00104
00105 #define TIMER0_AVAILABLE
00106 #define TIMER0A_AVAILABLE
00107 #define TIMER0B_AVAILABLE
00108 #define TIMER1_AVAILABLE
00109 #define TIMER1A_AVAILABLE
00110 #define TIMER1B_AVAILABLE
00111 #define TIMER1C_AVAILABLE
00112 #define TIMER2_AVAILABLE
00113 #define TIMER2A_AVAILABLE
00114 #define TIMER2B_AVAILABLE
00115 #define TIMER3_AVAILABLE
00116 #define TIMER3A_AVAILABLE
00117 #define TIMER3B_AVAILABLE
00118 #define TIMER3C_AVAILABLE
00119
00120
00121 #define SIG_OVERFLOW0_NUM 0
00122 #define SIG_OVERFLOW1_NUM 1
00123 #define SIG_OVERFLOW2_NUM 2
00124 #define SIG_OVERFLOW3_NUM 3
00125 #define SIG_OVERFLOW_TOTAL_NUM 4
00126
00127
00128 #define SIG_OUTPUT_COMPARE0A_NUM 0
00129 #define SIG_OUTPUT_COMPARE0B_NUM 1
00130 #define SIG_OUTPUT_COMPARE1A_NUM 2
00131 #define SIG_OUTPUT_COMPARE1B_NUM 3
00132 #define SIG_OUTPUT_COMPARE1C_NUM 4
00133 #define SIG_OUTPUT_COMPARE2A_NUM 5
00134 #define SIG_OUTPUT_COMPARE2B_NUM 6
00135 #define SIG_OUTPUT_COMPARE3A_NUM 7
00136 #define SIG_OUTPUT_COMPARE3B_NUM 8
00137 #define SIG_OUTPUT_COMPARE3C_NUM 9
00138 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 10
00139
00140
00141 #define PWM0A_NUM 0
00142 #define PWM0B_NUM 1
00143 #define PWM1A_NUM 2
00144 #define PWM1B_NUM 3
00145 #define PWM1C_NUM 4
00146 #define PWM2A_NUM 5
00147 #define PWM2B_NUM 6
00148 #define PWM3A_NUM 7
00149 #define PWM3B_NUM 8
00150 #define PWM3C_NUM 9
00151 #define PWM_TOTAL_NUM 10
00152
00153
00154 #define SIG_INPUT_CAPTURE1_NUM 0
00155 #define SIG_INPUT_CAPTURE3_NUM 1
00156 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00157
00158
00159
00160 #define UEBCHX_0_REG UEBCHX
00161 #define UEBCHX_1_REG UEBCHX
00162 #define UEBCHX_2_REG UEBCHX
00163
00164
00165 #define MUX0_REG ADMUX
00166 #define MUX1_REG ADMUX
00167 #define MUX2_REG ADMUX
00168 #define MUX3_REG ADMUX
00169 #define MUX4_REG ADMUX
00170 #define ADLAR_REG ADMUX
00171 #define REFS0_REG ADMUX
00172 #define REFS1_REG ADMUX
00173
00174
00175 #define SUSPE_REG UDIEN
00176 #define SOFE_REG UDIEN
00177 #define EORSTE_REG UDIEN
00178 #define WAKEUPE_REG UDIEN
00179 #define EORSME_REG UDIEN
00180 #define UPRSME_REG UDIEN
00181
00182
00183 #define WDP0_REG WDTCSR
00184 #define WDP1_REG WDTCSR
00185 #define WDP2_REG WDTCSR
00186 #define WDE_REG WDTCSR
00187 #define WDCE_REG WDTCSR
00188 #define WDP3_REG WDTCSR
00189 #define WDIE_REG WDTCSR
00190 #define WDIF_REG WDTCSR
00191
00192
00193 #define EEDR0_REG EEDR
00194 #define EEDR1_REG EEDR
00195 #define EEDR2_REG EEDR
00196 #define EEDR3_REG EEDR
00197 #define EEDR4_REG EEDR
00198 #define EEDR5_REG EEDR
00199 #define EEDR6_REG EEDR
00200 #define EEDR7_REG EEDR
00201
00202
00203 #define OCR0B_0_REG OCR0B
00204 #define OCR0B_1_REG OCR0B
00205 #define OCR0B_2_REG OCR0B
00206 #define OCR0B_3_REG OCR0B
00207 #define OCR0B_4_REG OCR0B
00208 #define OCR0B_5_REG OCR0B
00209 #define OCR0B_6_REG OCR0B
00210 #define OCR0B_7_REG OCR0B
00211
00212
00213 #define RXINE_REG UPIENX
00214 #define RXSTALLE_REG UPIENX
00215 #define TXOUTE_REG UPIENX
00216 #define TXSTPE_REG UPIENX
00217 #define PERRE_REG UPIENX
00218 #define NAKEDE_REG UPIENX
00219
00220
00221
00222 #define SUSPI_REG UDINT
00223 #define SOFI_REG UDINT
00224 #define EORSTI_REG UDINT
00225 #define WAKEUPI_REG UDINT
00226 #define EORSMI_REG UDINT
00227 #define UPRSMI_REG UDINT
00228
00229
00230 #define EPRST0_REG UERST
00231 #define EPRST1_REG UERST
00232 #define EPRST2_REG UERST
00233 #define EPRST3_REG UERST
00234 #define EPRST4_REG UERST
00235 #define EPRST5_REG UERST
00236 #define EPRST6_REG UERST
00237
00238
00239 #define RAMPZ0_REG RAMPZ
00240
00241
00242
00243 #define EPBK0_REG UECFG1X
00244 #define EPBK1_REG UECFG1X
00245 #define EPSIZE0_REG UECFG1X
00246 #define EPSIZE1_REG UECFG1X
00247 #define EPSIZE2_REG UECFG1X
00248
00249
00250 #define EPEN_REG UECONX
00251
00252 #define STALLRQC_REG UECONX
00253 #define STALLRQ_REG UECONX
00254
00255
00256 #define OCR2A_0_REG OCR2A
00257 #define OCR2A_1_REG OCR2A
00258 #define OCR2A_2_REG OCR2A
00259 #define OCR2A_3_REG OCR2A
00260 #define OCR2A_4_REG OCR2A
00261 #define OCR2A_5_REG OCR2A
00262 #define OCR2A_6_REG OCR2A
00263 #define OCR2A_7_REG OCR2A
00264
00265
00266 #define SPDR0_REG SPDR
00267 #define SPDR1_REG SPDR
00268 #define SPDR2_REG SPDR
00269 #define SPDR3_REG SPDR
00270 #define SPDR4_REG SPDR
00271 #define SPDR5_REG SPDR
00272 #define SPDR6_REG SPDR
00273 #define SPDR7_REG SPDR
00274
00275
00276 #define SRPE_REG OTGIEN
00277 #define VBERRE_REG OTGIEN
00278 #define BCERRE_REG OTGIEN
00279 #define ROLEEXE_REG OTGIEN
00280 #define HNPERRE_REG OTGIEN
00281 #define STOE_REG OTGIEN
00282
00283
00284 #define ICR1H0_REG ICR1H
00285 #define ICR1H1_REG ICR1H
00286 #define ICR1H2_REG ICR1H
00287 #define ICR1H3_REG ICR1H
00288 #define ICR1H4_REG ICR1H
00289 #define ICR1H5_REG ICR1H
00290 #define ICR1H6_REG ICR1H
00291 #define ICR1H7_REG ICR1H
00292
00293
00294 #define ICR1L0_REG ICR1L
00295 #define ICR1L1_REG ICR1L
00296 #define ICR1L2_REG ICR1L
00297 #define ICR1L3_REG ICR1L
00298 #define ICR1L4_REG ICR1L
00299 #define ICR1L5_REG ICR1L
00300 #define ICR1L6_REG ICR1L
00301 #define ICR1L7_REG ICR1L
00302
00303
00304 #define SPI2X_REG SPSR
00305 #define WCOL_REG SPSR
00306 #define SPIF_REG SPSR
00307
00308
00309 #define EPINT0_REG UEINT
00310 #define EPINT1_REG UEINT
00311 #define EPINT2_REG UEINT
00312 #define EPINT3_REG UEINT
00313 #define EPINT4_REG UEINT
00314 #define EPINT5_REG UEINT
00315 #define EPINT6_REG UEINT
00316
00317
00318 #define TCNT1L0_REG TCNT1L
00319 #define TCNT1L1_REG TCNT1L
00320 #define TCNT1L2_REG TCNT1L
00321 #define TCNT1L3_REG TCNT1L
00322 #define TCNT1L4_REG TCNT1L
00323 #define TCNT1L5_REG TCNT1L
00324 #define TCNT1L6_REG TCNT1L
00325 #define TCNT1L7_REG TCNT1L
00326
00327
00328 #define PORTD0_REG PORTD
00329 #define PORTD1_REG PORTD
00330 #define PORTD2_REG PORTD
00331 #define PORTD3_REG PORTD
00332 #define PORTD4_REG PORTD
00333 #define PORTD5_REG PORTD
00334 #define PORTD6_REG PORTD
00335 #define PORTD7_REG PORTD
00336
00337
00338 #define VALUE_20_REG OTGTCON
00339 #define VALUE_21_REG OTGTCON
00340 #define VALUE_22_REG OTGTCON
00341 #define PAGE0_REG OTGTCON
00342 #define PAGE1_REG OTGTCON
00343 #define OTGTCON_7_REG OTGTCON
00344
00345
00346 #define TCNT1H0_REG TCNT1H
00347 #define TCNT1H1_REG TCNT1H
00348 #define TCNT1H2_REG TCNT1H
00349 #define TCNT1H3_REG TCNT1H
00350 #define TCNT1H4_REG TCNT1H
00351 #define TCNT1H5_REG TCNT1H
00352 #define TCNT1H6_REG TCNT1H
00353 #define TCNT1H7_REG TCNT1H
00354
00355
00356 #define PORTC0_REG PORTC
00357 #define PORTC1_REG PORTC
00358 #define PORTC2_REG PORTC
00359 #define PORTC3_REG PORTC
00360 #define PORTC4_REG PORTC
00361 #define PORTC5_REG PORTC
00362 #define PORTC6_REG PORTC
00363 #define PORTC7_REG PORTC
00364
00365
00366 #define PORTA0_REG PORTA
00367 #define PORTA1_REG PORTA
00368 #define PORTA2_REG PORTA
00369 #define PORTA3_REG PORTA
00370 #define PORTA4_REG PORTA
00371 #define PORTA5_REG PORTA
00372 #define PORTA6_REG PORTA
00373 #define PORTA7_REG PORTA
00374
00375
00376 #define PBYCT8_REG UPBCHX
00377 #define PBYCT9_REG UPBCHX
00378 #define PBYCT10_REG UPBCHX
00379
00380
00381 #define INT0_REG EIMSK
00382 #define INT1_REG EIMSK
00383 #define INT2_REG EIMSK
00384 #define INT3_REG EIMSK
00385 #define INT4_REG EIMSK
00386 #define INT5_REG EIMSK
00387 #define INT6_REG EIMSK
00388 #define INT7_REG EIMSK
00389
00390
00391 #define UDR1_0_REG UDR1
00392 #define UDR1_1_REG UDR1
00393 #define UDR1_2_REG UDR1
00394 #define UDR1_3_REG UDR1
00395 #define UDR1_4_REG UDR1
00396 #define UDR1_5_REG UDR1
00397 #define UDR1_6_REG UDR1
00398 #define UDR1_7_REG UDR1
00399
00400
00401 #define GPIOR20_REG GPIOR2
00402 #define GPIOR21_REG GPIOR2
00403 #define GPIOR22_REG GPIOR2
00404 #define GPIOR23_REG GPIOR2
00405 #define GPIOR24_REG GPIOR2
00406 #define GPIOR25_REG GPIOR2
00407 #define GPIOR26_REG GPIOR2
00408 #define GPIOR27_REG GPIOR2
00409
00410
00411 #define ISC40_REG EICRB
00412 #define ISC41_REG EICRB
00413 #define ISC50_REG EICRB
00414 #define ISC51_REG EICRB
00415 #define ISC60_REG EICRB
00416 #define ISC61_REG EICRB
00417 #define ISC70_REG EICRB
00418 #define ISC71_REG EICRB
00419
00420
00421 #define UEDATX_0_REG UEDATX
00422 #define UEDATX_1_REG UEDATX
00423 #define UEDATX_2_REG UEDATX
00424 #define UEDATX_3_REG UEDATX
00425 #define UEDATX_4_REG UEDATX
00426 #define UEDATX_5_REG UEDATX
00427 #define UEDATX_6_REG UEDATX
00428 #define UEDATX_7_REG UEDATX
00429
00430
00431 #define ISC00_REG EICRA
00432 #define ISC01_REG EICRA
00433 #define ISC10_REG EICRA
00434 #define ISC11_REG EICRA
00435 #define ISC20_REG EICRA
00436 #define ISC21_REG EICRA
00437 #define ISC30_REG EICRA
00438 #define ISC31_REG EICRA
00439
00440
00441 #define SRPI_REG OTGINT
00442 #define VBERRI_REG OTGINT
00443 #define BCERRI_REG OTGINT
00444 #define ROLEEXI_REG OTGINT
00445 #define HNPERRI_REG OTGINT
00446 #define STOI_REG OTGINT
00447
00448
00449 #define EPDIR_REG UECFG0X
00450 #define EPTYPE0_REG UECFG0X
00451 #define EPTYPE1_REG UECFG0X
00452
00453
00454 #define ADC0D_REG DIDR0
00455 #define ADC1D_REG DIDR0
00456 #define ADC2D_REG DIDR0
00457 #define ADC3D_REG DIDR0
00458 #define ADC4D_REG DIDR0
00459 #define ADC5D_REG DIDR0
00460 #define ADC6D_REG DIDR0
00461 #define ADC7D_REG DIDR0
00462
00463
00464 #define AIN0D_REG DIDR1
00465 #define AIN1D_REG DIDR1
00466
00467
00468 #define DDF0_REG DDRF
00469 #define DDF1_REG DDRF
00470 #define DDF2_REG DDRF
00471 #define DDF3_REG DDRF
00472 #define DDF4_REG DDRF
00473 #define DDF5_REG DDRF
00474 #define DDF6_REG DDRF
00475 #define DDF7_REG DDRF
00476
00477
00478 #define TCR2BUB_REG ASSR
00479 #define TCR2AUB_REG ASSR
00480 #define OCR2BUB_REG ASSR
00481 #define OCR2AUB_REG ASSR
00482 #define TCN2UB_REG ASSR
00483 #define AS2_REG ASSR
00484 #define EXCLK_REG ASSR
00485
00486
00487 #define CLKPS0_REG CLKPR
00488 #define CLKPS1_REG CLKPR
00489 #define CLKPS2_REG CLKPR
00490 #define CLKPS3_REG CLKPR
00491 #define CLKPCE_REG CLKPR
00492
00493
00494 #define DCONNE_REG UHIEN
00495 #define DDISCE_REG UHIEN
00496 #define RSTE_REG UHIEN
00497 #define RSMEDE_REG UHIEN
00498 #define RXRSME_REG UHIEN
00499 #define HSOFE_REG UHIEN
00500 #define HWUPE_REG UHIEN
00501
00502
00503 #define C_REG SREG
00504 #define Z_REG SREG
00505 #define N_REG SREG
00506 #define V_REG SREG
00507 #define S_REG SREG
00508 #define H_REG SREG
00509 #define T_REG SREG
00510 #define I_REG SREG
00511
00512
00513 #define UENUM_0_REG UENUM
00514 #define UENUM_1_REG UENUM
00515 #define UENUM_2_REG UENUM
00516
00517
00518 #define UBRR_0_REG UBRR1L
00519 #define UBRR_1_REG UBRR1L
00520 #define UBRR_2_REG UBRR1L
00521 #define UBRR_3_REG UBRR1L
00522 #define UBRR_4_REG UBRR1L
00523 #define UBRR_5_REG UBRR1L
00524 #define UBRR_6_REG UBRR1L
00525 #define UBRR_7_REG UBRR1L
00526
00527
00528 #define DDC0_REG DDRC
00529 #define DDC1_REG DDRC
00530 #define DDC2_REG DDRC
00531 #define DDC3_REG DDRC
00532 #define DDC4_REG DDRC
00533 #define DDC5_REG DDRC
00534 #define DDC6_REG DDRC
00535 #define DDC7_REG DDRC
00536
00537
00538 #define OCR3AL0_REG OCR3AL
00539 #define OCR3AL1_REG OCR3AL
00540 #define OCR3AL2_REG OCR3AL
00541 #define OCR3AL3_REG OCR3AL
00542 #define OCR3AL4_REG OCR3AL
00543 #define OCR3AL5_REG OCR3AL
00544 #define OCR3AL6_REG OCR3AL
00545 #define OCR3AL7_REG OCR3AL
00546
00547
00548 #define DDA0_REG DDRA
00549 #define DDA1_REG DDRA
00550 #define DDA2_REG DDRA
00551 #define DDA3_REG DDRA
00552 #define DDA4_REG DDRA
00553 #define DDA5_REG DDRA
00554 #define DDA6_REG DDRA
00555 #define DDA7_REG DDRA
00556
00557
00558 #define UBRR_8_REG UBRR1H
00559 #define UBRR_9_REG UBRR1H
00560 #define UBRR_10_REG UBRR1H
00561 #define UBRR_11_REG UBRR1H
00562
00563
00564 #define OCR3AH0_REG OCR3AH
00565 #define OCR3AH1_REG OCR3AH
00566 #define OCR3AH2_REG OCR3AH
00567 #define OCR3AH3_REG OCR3AH
00568 #define OCR3AH4_REG OCR3AH
00569 #define OCR3AH5_REG OCR3AH
00570 #define OCR3AH6_REG OCR3AH
00571 #define OCR3AH7_REG OCR3AH
00572
00573
00574 #define CS10_REG TCCR1B
00575 #define CS11_REG TCCR1B
00576 #define CS12_REG TCCR1B
00577 #define WGM12_REG TCCR1B
00578 #define WGM13_REG TCCR1B
00579 #define ICES1_REG TCCR1B
00580 #define ICNC1_REG TCCR1B
00581
00582
00583 #define UHADDR_0_REG UHADDR
00584 #define UHADDR_1_REG UHADDR
00585 #define UHADDR_2_REG UHADDR
00586 #define UHADDR_3_REG UHADDR
00587 #define UHADDR_4_REG UHADDR
00588 #define UHADDR_5_REG UHADDR
00589 #define UHADDR_6_REG UHADDR
00590
00591
00592 #define CAL0_REG OSCCAL
00593 #define CAL1_REG OSCCAL
00594 #define CAL2_REG OSCCAL
00595 #define CAL3_REG OSCCAL
00596 #define CAL4_REG OSCCAL
00597 #define CAL5_REG OSCCAL
00598 #define CAL6_REG OSCCAL
00599 #define CAL7_REG OSCCAL
00600
00601
00602 #define DDD0_REG DDRD
00603 #define DDD1_REG DDRD
00604 #define DDD2_REG DDRD
00605 #define DDD3_REG DDRD
00606 #define DDD4_REG DDRD
00607 #define DDD5_REG DDRD
00608 #define DDD6_REG DDRD
00609 #define DDD7_REG DDRD
00610
00611
00612 #define GPIOR10_REG GPIOR1
00613 #define GPIOR11_REG GPIOR1
00614 #define GPIOR12_REG GPIOR1
00615 #define GPIOR13_REG GPIOR1
00616 #define GPIOR14_REG GPIOR1
00617 #define GPIOR15_REG GPIOR1
00618 #define GPIOR16_REG GPIOR1
00619 #define GPIOR17_REG GPIOR1
00620
00621
00622 #define GPIOR00_REG GPIOR0
00623 #define GPIOR01_REG GPIOR0
00624 #define GPIOR02_REG GPIOR0
00625 #define GPIOR03_REG GPIOR0
00626 #define GPIOR04_REG GPIOR0
00627 #define GPIOR05_REG GPIOR0
00628 #define GPIOR06_REG GPIOR0
00629 #define GPIOR07_REG GPIOR0
00630
00631
00632 #define TWBR0_REG TWBR
00633 #define TWBR1_REG TWBR
00634 #define TWBR2_REG TWBR
00635 #define TWBR3_REG TWBR
00636 #define TWBR4_REG TWBR
00637 #define TWBR5_REG TWBR
00638 #define TWBR6_REG TWBR
00639 #define TWBR7_REG TWBR
00640
00641
00642 #define DETACH_REG UDCON
00643 #define RMWKUP_REG UDCON
00644 #define LSM_REG UDCON
00645
00646
00647 #define UHFLEN_0_REG UHFLEN
00648 #define UHFLEN_1_REG UHFLEN
00649 #define UHFLEN_2_REG UHFLEN
00650 #define UHFLEN_3_REG UHFLEN
00651 #define UHFLEN_4_REG UHFLEN
00652 #define UHFLEN_5_REG UHFLEN
00653 #define UHFLEN_6_REG UHFLEN
00654 #define UHFLEN_7_REG UHFLEN
00655
00656
00657 #define UHFNUMH_0_REG UHFNUMH
00658 #define UHFNUMH_1_REG UHFNUMH
00659 #define UHFNUMH_2_REG UHFNUMH
00660
00661
00662 #define UHFNUML_0_REG UHFNUML
00663 #define UHFNUML_1_REG UHFNUML
00664 #define UHFNUML_2_REG UHFNUML
00665 #define UHFNUML_3_REG UHFNUML
00666 #define UHFNUML_4_REG UHFNUML
00667 #define UHFNUML_5_REG UHFNUML
00668 #define UHFNUML_6_REG UHFNUML
00669 #define UHFNUML_7_REG UHFNUML
00670
00671
00672 #define PCIE0_REG PCICR
00673
00674
00675 #define VBUSTI_REG USBINT
00676 #define IDTI_REG USBINT
00677
00678
00679 #define TCNT2_0_REG TCNT2
00680 #define TCNT2_1_REG TCNT2
00681 #define TCNT2_2_REG TCNT2
00682 #define TCNT2_3_REG TCNT2
00683 #define TCNT2_4_REG TCNT2
00684 #define TCNT2_5_REG TCNT2
00685 #define TCNT2_6_REG TCNT2
00686 #define TCNT2_7_REG TCNT2
00687
00688
00689 #define TCNT0_0_REG TCNT0
00690 #define TCNT0_1_REG TCNT0
00691 #define TCNT0_2_REG TCNT0
00692 #define TCNT0_3_REG TCNT0
00693 #define TCNT0_4_REG TCNT0
00694 #define TCNT0_5_REG TCNT0
00695 #define TCNT0_6_REG TCNT0
00696 #define TCNT0_7_REG TCNT0
00697
00698
00699 #define TWGCE_REG TWAR
00700 #define TWA0_REG TWAR
00701 #define TWA1_REG TWAR
00702 #define TWA2_REG TWAR
00703 #define TWA3_REG TWAR
00704 #define TWA4_REG TWAR
00705 #define TWA5_REG TWAR
00706 #define TWA6_REG TWAR
00707
00708
00709 #define UVREGE_REG UHWCON
00710 #define UVCONE_REG UHWCON
00711 #define UIDE_REG UHWCON
00712 #define UIMOD_REG UHWCON
00713
00714
00715 #define CS00_REG TCCR0B
00716 #define CS01_REG TCCR0B
00717 #define CS02_REG TCCR0B
00718 #define WGM02_REG TCCR0B
00719 #define FOC0B_REG TCCR0B
00720 #define FOC0A_REG TCCR0B
00721
00722
00723 #define FNCERR_REG UDMFN
00724
00725
00726 #define WGM00_REG TCCR0A
00727 #define WGM01_REG TCCR0A
00728 #define COM0B0_REG TCCR0A
00729 #define COM0B1_REG TCCR0A
00730 #define COM0A0_REG TCCR0A
00731 #define COM0A1_REG TCCR0A
00732
00733
00734 #define PDAT0_REG UPDATX
00735 #define PDAT1_REG UPDATX
00736 #define PDAT2_REG UPDATX
00737 #define PDAT3_REG UPDATX
00738 #define PDAT4_REG UPDATX
00739 #define PDAT5_REG UPDATX
00740 #define PDAT6_REG UPDATX
00741 #define PDAT7_REG UPDATX
00742
00743
00744 #define OCR2B_0_REG OCR2B
00745 #define OCR2B_1_REG OCR2B
00746 #define OCR2B_2_REG OCR2B
00747 #define OCR2B_3_REG OCR2B
00748 #define OCR2B_4_REG OCR2B
00749 #define OCR2B_5_REG OCR2B
00750 #define OCR2B_6_REG OCR2B
00751 #define OCR2B_7_REG OCR2B
00752
00753
00754 #define SOFEN_REG UHCON
00755 #define RESET_REG UHCON
00756 #define RESUME_REG UHCON
00757
00758
00759 #define TOV3_REG TIFR3
00760 #define OCF3A_REG TIFR3
00761 #define OCF3B_REG TIFR3
00762 #define OCF3C_REG TIFR3
00763 #define ICF3_REG TIFR3
00764
00765
00766 #define SPR0_REG SPCR
00767 #define SPR1_REG SPCR
00768 #define CPHA_REG SPCR
00769 #define CPOL_REG SPCR
00770 #define MSTR_REG SPCR
00771 #define DORD_REG SPCR
00772 #define SPE_REG SPCR
00773 #define SPIE_REG SPCR
00774
00775
00776 #define TOV1_REG TIFR1
00777 #define OCF1A_REG TIFR1
00778 #define OCF1B_REG TIFR1
00779 #define OCF1C_REG TIFR1
00780 #define ICF1_REG TIFR1
00781
00782
00783 #define EEAR8_REG EEARH
00784 #define EEAR9_REG EEARH
00785 #define EEAR10_REG EEARH
00786 #define EEAR11_REG EEARH
00787
00788
00789 #define PINB0_REG PINB
00790 #define PINB1_REG PINB
00791 #define PINB2_REG PINB
00792 #define PINB3_REG PINB
00793 #define PINB4_REG PINB
00794 #define PINB5_REG PINB
00795 #define PINB6_REG PINB
00796 #define PINB7_REG PINB
00797
00798
00799 #define PINT0_REG UPINT
00800 #define PINT1_REG UPINT
00801 #define PINT2_REG UPINT
00802 #define PINT3_REG UPINT
00803 #define PINT4_REG UPINT
00804 #define PINT5_REG UPINT
00805 #define PINT6_REG UPINT
00806
00807
00808 #define UEBCLX_0_REG UEBCLX
00809 #define UEBCLX_1_REG UEBCLX
00810 #define UEBCLX_2_REG UEBCLX
00811 #define UEBCLX_3_REG UEBCLX
00812 #define UEBCLX_4_REG UEBCLX
00813 #define UEBCLX_5_REG UEBCLX
00814 #define UEBCLX_6_REG UEBCLX
00815 #define UEBCLX_7_REG UEBCLX
00816
00817
00818 #define OCR3CH0_REG OCR3CH
00819 #define OCR3CH1_REG OCR3CH
00820 #define OCR3CH2_REG OCR3CH
00821 #define OCR3CH3_REG OCR3CH
00822 #define OCR3CH4_REG OCR3CH
00823 #define OCR3CH5_REG OCR3CH
00824 #define OCR3CH6_REG OCR3CH
00825 #define OCR3CH7_REG OCR3CH
00826
00827
00828 #define CURRBK0_REG UESTA1X
00829 #define CURRBK1_REG UESTA1X
00830 #define CTRLDIR_REG UESTA1X
00831
00832
00833 #define OCR3CL0_REG OCR3CL
00834 #define OCR3CL1_REG OCR3CL
00835 #define OCR3CL2_REG OCR3CL
00836 #define OCR3CL3_REG OCR3CL
00837 #define OCR3CL4_REG OCR3CL
00838 #define OCR3CL5_REG OCR3CL
00839 #define OCR3CL6_REG OCR3CL
00840 #define OCR3CL7_REG OCR3CL
00841
00842
00843 #define PSRSYNC_REG GTCCR
00844 #define TSM_REG GTCCR
00845 #define PSRASY_REG GTCCR
00846
00847
00848 #define NBUSYK0_REG UPSTAX
00849 #define NBUSYK1_REG UPSTAX
00850
00851
00852
00853
00854
00855
00856
00857 #define SP8_REG SPH
00858 #define SP9_REG SPH
00859 #define SP10_REG SPH
00860 #define SP11_REG SPH
00861 #define SP12_REG SPH
00862 #define SP13_REG SPH
00863 #define SP14_REG SPH
00864 #define SP15_REG SPH
00865
00866
00867 #define FOC3C_REG TCCR3C
00868 #define FOC3B_REG TCCR3C
00869 #define FOC3A_REG TCCR3C
00870
00871
00872 #define CS30_REG TCCR3B
00873 #define CS31_REG TCCR3B
00874 #define CS32_REG TCCR3B
00875 #define WGM32_REG TCCR3B
00876 #define WGM33_REG TCCR3B
00877 #define ICES3_REG TCCR3B
00878 #define ICNC3_REG TCCR3B
00879
00880
00881 #define WGM30_REG TCCR3A
00882 #define WGM31_REG TCCR3A
00883 #define COM3C0_REG TCCR3A
00884 #define COM3C1_REG TCCR3A
00885 #define COM3B0_REG TCCR3A
00886 #define COM3B1_REG TCCR3A
00887 #define COM3A0_REG TCCR3A
00888 #define COM3A1_REG TCCR3A
00889
00890
00891 #define TXINI_REG UEINTX
00892 #define STALLEDI_REG UEINTX
00893 #define RXOUTI_REG UEINTX
00894 #define RXSTPI_REG UEINTX
00895 #define NAKOUTI_REG UEINTX
00896
00897 #define NAKINI_REG UEINTX
00898
00899
00900
00901 #define OCR1BL0_REG OCR1BL
00902 #define OCR1BL1_REG OCR1BL
00903 #define OCR1BL2_REG OCR1BL
00904 #define OCR1BL3_REG OCR1BL
00905 #define OCR1BL4_REG OCR1BL
00906 #define OCR1BL5_REG OCR1BL
00907 #define OCR1BL6_REG OCR1BL
00908 #define OCR1BL7_REG OCR1BL
00909
00910
00911 #define TCNT3H0_REG TCNT3H
00912 #define TCNT3H1_REG TCNT3H
00913 #define TCNT3H2_REG TCNT3H
00914 #define TCNT3H3_REG TCNT3H
00915 #define TCNT3H4_REG TCNT3H
00916 #define TCNT3H5_REG TCNT3H
00917 #define TCNT3H6_REG TCNT3H
00918 #define TCNT3H7_REG TCNT3H
00919
00920
00921 #define PEPNUM0_REG UPCFG0X
00922 #define PEPNUM1_REG UPCFG0X
00923 #define PEPNUM2_REG UPCFG0X
00924 #define PEPNUM3_REG UPCFG0X
00925 #define PTOKEN0_REG UPCFG0X
00926 #define PTOKEN1_REG UPCFG0X
00927 #define PTYPE0_REG UPCFG0X
00928 #define PTYPE1_REG UPCFG0X
00929
00930
00931 #define OCR1BH0_REG OCR1BH
00932 #define OCR1BH1_REG OCR1BH
00933 #define OCR1BH2_REG OCR1BH
00934 #define OCR1BH3_REG OCR1BH
00935 #define OCR1BH4_REG OCR1BH
00936 #define OCR1BH5_REG OCR1BH
00937 #define OCR1BH6_REG OCR1BH
00938 #define OCR1BH7_REG OCR1BH
00939
00940
00941 #define TCNT3L0_REG TCNT3L
00942 #define TCNT3L1_REG TCNT3L
00943 #define TCNT3L2_REG TCNT3L
00944 #define TCNT3L3_REG TCNT3L
00945 #define TCNT3L4_REG TCNT3L
00946 #define TCNT3L5_REG TCNT3L
00947 #define TCNT3L6_REG TCNT3L
00948 #define TCNT3L7_REG TCNT3L
00949
00950
00951 #define SP0_REG SPL
00952 #define SP1_REG SPL
00953 #define SP2_REG SPL
00954 #define SP3_REG SPL
00955 #define SP4_REG SPL
00956 #define SP5_REG SPL
00957 #define SP6_REG SPL
00958 #define SP7_REG SPL
00959
00960
00961 #define DATATGL_REG UPERRX
00962 #define DATAPID_REG UPERRX
00963 #define PID_REG UPERRX
00964 #define TIMEOUT_REG UPERRX
00965 #define CRC16_REG UPERRX
00966 #define COUNTER0_REG UPERRX
00967 #define COUNTER1_REG UPERRX
00968
00969
00970 #define VBUSTE_REG USBCON
00971 #define IDTE_REG USBCON
00972 #define OTGPADE_REG USBCON
00973 #define FRZCLK_REG USBCON
00974 #define HOST_REG USBCON
00975 #define USBE_REG USBCON
00976
00977
00978 #define PEN_REG UPCONX
00979
00980 #define INMODE_REG UPCONX
00981 #define PFREEZE_REG UPCONX
00982
00983
00984 #define PORF_REG MCUSR
00985 #define EXTRF_REG MCUSR
00986 #define BORF_REG MCUSR
00987 #define WDRF_REG MCUSR
00988 #define JTRF_REG MCUSR
00989
00990
00991 #define EERE_REG EECR
00992 #define EEPE_REG EECR
00993 #define EEMPE_REG EECR
00994 #define EERIE_REG EECR
00995 #define EEPM0_REG EECR
00996 #define EEPM1_REG EECR
00997
00998
00999 #define SE_REG SMCR
01000 #define SM0_REG SMCR
01001 #define SM1_REG SMCR
01002 #define SM2_REG SMCR
01003
01004
01005 #define PBYCT0_REG UPBCLX
01006 #define PBYCT1_REG UPBCLX
01007 #define PBYCT2_REG UPBCLX
01008 #define PBYCT3_REG UPBCLX
01009 #define PBYCT4_REG UPBCLX
01010 #define PBYCT5_REG UPBCLX
01011 #define PBYCT6_REG UPBCLX
01012 #define PBYCT7_REG UPBCLX
01013
01014
01015 #define DCONNI_REG UHINT
01016 #define DDISCI_REG UHINT
01017 #define RSTI_REG UHINT
01018 #define RSMEDI_REG UHINT
01019 #define RXRSMI_REG UHINT
01020 #define HSOFI_REG UHINT
01021 #define UHUPI_REG UHINT
01022
01023
01024 #define TWIE_REG TWCR
01025 #define TWEN_REG TWCR
01026 #define TWWC_REG TWCR
01027 #define TWSTO_REG TWCR
01028 #define TWSTA_REG TWCR
01029 #define TWEA_REG TWCR
01030 #define TWINT_REG TWCR
01031
01032
01033 #define PCIF0_REG PCIFR
01034
01035
01036 #define WGM20_REG TCCR2A
01037 #define WGM21_REG TCCR2A
01038 #define COM2B0_REG TCCR2A
01039 #define COM2B1_REG TCCR2A
01040 #define COM2A0_REG TCCR2A
01041 #define COM2A1_REG TCCR2A
01042
01043
01044 #define CS20_REG TCCR2B
01045 #define CS21_REG TCCR2B
01046 #define CS22_REG TCCR2B
01047 #define WGM22_REG TCCR2B
01048 #define FOC2B_REG TCCR2B
01049 #define FOC2A_REG TCCR2B
01050
01051
01052 #define PNUM0_REG UPNUM
01053 #define PNUM1_REG UPNUM
01054 #define PNUM2_REG UPNUM
01055
01056
01057 #define TWPS0_REG TWSR
01058 #define TWPS1_REG TWSR
01059 #define TWS3_REG TWSR
01060 #define TWS4_REG TWSR
01061 #define TWS5_REG TWSR
01062 #define TWS6_REG TWSR
01063 #define TWS7_REG TWSR
01064
01065
01066 #define EEAR0_REG EEARL
01067 #define EEAR1_REG EEARL
01068 #define EEAR2_REG EEARL
01069 #define EEAR3_REG EEARL
01070 #define EEAR4_REG EEARL
01071 #define EEAR5_REG EEARL
01072 #define EEAR6_REG EEARL
01073 #define EEAR7_REG EEARL
01074
01075
01076 #define IVCE_REG MCUCR
01077 #define IVSEL_REG MCUCR
01078 #define PUD_REG MCUCR
01079 #define JTD_REG MCUCR
01080
01081
01082 #define OCR1CL0_REG OCR1CL
01083 #define OCR1CL1_REG OCR1CL
01084 #define OCR1CL2_REG OCR1CL
01085 #define OCR1CL3_REG OCR1CL
01086 #define OCR1CL4_REG OCR1CL
01087 #define OCR1CL5_REG OCR1CL
01088 #define OCR1CL6_REG OCR1CL
01089 #define OCR1CL7_REG OCR1CL
01090
01091
01092 #define OCR1CH0_REG OCR1CH
01093 #define OCR1CH1_REG OCR1CH
01094 #define OCR1CH2_REG OCR1CH
01095 #define OCR1CH3_REG OCR1CH
01096 #define OCR1CH4_REG OCR1CH
01097 #define OCR1CH5_REG OCR1CH
01098 #define OCR1CH6_REG OCR1CH
01099 #define OCR1CH7_REG OCR1CH
01100
01101
01102
01103 #define PBK0_REG UPCFG1X
01104 #define PBK1_REG UPCFG1X
01105 #define PSIZE0_REG UPCFG1X
01106 #define PSIZE1_REG UPCFG1X
01107 #define PSIZE2_REG UPCFG1X
01108
01109
01110 #define OCDR0_REG OCDR
01111 #define OCDR1_REG OCDR
01112 #define OCDR2_REG OCDR
01113 #define OCDR3_REG OCDR
01114 #define OCDR4_REG OCDR
01115 #define OCDR5_REG OCDR
01116 #define OCDR6_REG OCDR
01117 #define OCDR7_REG OCDR
01118
01119
01120 #define PINA0_REG PINA
01121 #define PINA1_REG PINA
01122 #define PINA2_REG PINA
01123 #define PINA3_REG PINA
01124 #define PINA4_REG PINA
01125 #define PINA5_REG PINA
01126 #define PINA6_REG PINA
01127 #define PINA7_REG PINA
01128
01129
01130 #define VBUS_REG USBSTA
01131 #define ID_REG USBSTA
01132 #define SPEED_REG USBSTA
01133
01134
01135 #define TXINE_REG UEIENX
01136 #define STALLEDE_REG UEIENX
01137 #define RXOUTE_REG UEIENX
01138 #define RXSTPE_REG UEIENX
01139 #define NAKOUTE_REG UEIENX
01140 #define NAKINE_REG UEIENX
01141
01142
01143
01144 #define VBUSRQC_REG OTGCON
01145 #define VBUSREQ_REG OTGCON
01146 #define VBUSHWC_REG OTGCON
01147 #define SRPSEL_REG OTGCON
01148 #define SRPREQ_REG OTGCON
01149 #define HNPREQ_REG OTGCON
01150
01151
01152 #define TXB81_REG UCSR1B
01153 #define RXB81_REG UCSR1B
01154 #define UCSZ12_REG UCSR1B
01155 #define TXEN1_REG UCSR1B
01156 #define RXEN1_REG UCSR1B
01157 #define UDRIE1_REG UCSR1B
01158 #define TXCIE1_REG UCSR1B
01159 #define RXCIE1_REG UCSR1B
01160
01161
01162 #define UCPOL1_REG UCSR1C
01163 #define UCSZ10_REG UCSR1C
01164 #define UCSZ11_REG UCSR1C
01165 #define USBS1_REG UCSR1C
01166 #define UPM10_REG UCSR1C
01167 #define UPM11_REG UCSR1C
01168 #define UMSEL10_REG UCSR1C
01169 #define UMSEL11_REG UCSR1C
01170
01171
01172 #define MPCM1_REG UCSR1A
01173 #define U2X1_REG UCSR1A
01174 #define UPE1_REG UCSR1A
01175 #define DOR1_REG UCSR1A
01176 #define FE1_REG UCSR1A
01177 #define UDRE1_REG UCSR1A
01178 #define TXC1_REG UCSR1A
01179 #define RXC1_REG UCSR1A
01180
01181
01182 #define INRQ0_REG UPINRQX
01183 #define INRQ1_REG UPINRQX
01184 #define INRQ2_REG UPINRQX
01185 #define INRQ3_REG UPINRQX
01186 #define INRQ4_REG UPINRQX
01187 #define INRQ5_REG UPINRQX
01188 #define INRQ6_REG UPINRQX
01189 #define INRQ7_REG UPINRQX
01190
01191
01192 #define EIND0_REG EIND
01193
01194
01195 #define UDFNUML_0_REG UDFNUML
01196 #define UDFNUML_1_REG UDFNUML
01197 #define UDFNUML_2_REG UDFNUML
01198 #define UDFNUML_3_REG UDFNUML
01199 #define UDFNUML_4_REG UDFNUML
01200 #define UDFNUML_5_REG UDFNUML
01201 #define UDFNUML_6_REG UDFNUML
01202 #define UDFNUML_7_REG UDFNUML
01203
01204
01205 #define TWD0_REG TWDR
01206 #define TWD1_REG TWDR
01207 #define TWD2_REG TWDR
01208 #define TWD3_REG TWDR
01209 #define TWD4_REG TWDR
01210 #define TWD5_REG TWDR
01211 #define TWD6_REG TWDR
01212 #define TWD7_REG TWDR
01213
01214
01215 #define UDFNUMH_0_REG UDFNUMH
01216 #define UDFNUMH_1_REG UDFNUMH
01217 #define UDFNUMH_2_REG UDFNUMH
01218
01219
01220 #define OCR1AH0_REG OCR1AH
01221 #define OCR1AH1_REG OCR1AH
01222 #define OCR1AH2_REG OCR1AH
01223 #define OCR1AH3_REG OCR1AH
01224 #define OCR1AH4_REG OCR1AH
01225 #define OCR1AH5_REG OCR1AH
01226 #define OCR1AH6_REG OCR1AH
01227 #define OCR1AH7_REG OCR1AH
01228
01229
01230 #define ADPS0_REG ADCSRA
01231 #define ADPS1_REG ADCSRA
01232 #define ADPS2_REG ADCSRA
01233 #define ADIE_REG ADCSRA
01234 #define ADIF_REG ADCSRA
01235 #define ADATE_REG ADCSRA
01236 #define ADSC_REG ADCSRA
01237 #define ADEN_REG ADCSRA
01238
01239
01240 #define ADTS0_REG ADCSRB
01241 #define ADTS1_REG ADCSRB
01242 #define ADTS2_REG ADCSRB
01243 #define ADHSM_REG ADCSRB
01244 #define ACME_REG ADCSRB
01245
01246
01247 #define RXINI_REG UPINTX
01248 #define RXSTALLI_REG UPINTX
01249 #define TXOUTI_REG UPINTX
01250 #define TXSTPI_REG UPINTX
01251 #define PERRI_REG UPINTX
01252
01253 #define NAKEDI_REG UPINTX
01254
01255
01256
01257 #define WGM10_REG TCCR1A
01258 #define WGM11_REG TCCR1A
01259 #define COM1C0_REG TCCR1A
01260 #define COM1C1_REG TCCR1A
01261 #define COM1B0_REG TCCR1A
01262 #define COM1B1_REG TCCR1A
01263 #define COM1A0_REG TCCR1A
01264 #define COM1A1_REG TCCR1A
01265
01266
01267 #define OCROA_0_REG OCR0A
01268 #define OCROA_1_REG OCR0A
01269 #define OCROA_2_REG OCR0A
01270 #define OCROA_3_REG OCR0A
01271 #define OCROA_4_REG OCR0A
01272 #define OCROA_5_REG OCR0A
01273 #define OCROA_6_REG OCR0A
01274 #define OCROA_7_REG OCR0A
01275
01276
01277 #define UPCFG2X_0_REG UPCFG2X
01278 #define UPCFG2X_1_REG UPCFG2X
01279 #define UPCFG2X_2_REG UPCFG2X
01280 #define UPCFG2X_3_REG UPCFG2X
01281 #define UPCFG2X_4_REG UPCFG2X
01282 #define UPCFG2X_5_REG UPCFG2X
01283 #define UPCFG2X_6_REG UPCFG2X
01284 #define UPCFG2X_7_REG UPCFG2X
01285
01286
01287 #define ACIS0_REG ACSR
01288 #define ACIS1_REG ACSR
01289 #define ACIC_REG ACSR
01290 #define ACIE_REG ACSR
01291 #define ACI_REG ACSR
01292 #define ACO_REG ACSR
01293 #define ACBG_REG ACSR
01294 #define ACD_REG ACSR
01295
01296
01297 #define PORTF0_REG PORTF
01298 #define PORTF1_REG PORTF
01299 #define PORTF2_REG PORTF
01300 #define PORTF3_REG PORTF
01301 #define PORTF4_REG PORTF
01302 #define PORTF5_REG PORTF
01303 #define PORTF6_REG PORTF
01304 #define PORTF7_REG PORTF
01305
01306
01307 #define FOC1C_REG TCCR1C
01308 #define FOC1B_REG TCCR1C
01309 #define FOC1A_REG TCCR1C
01310
01311
01312 #define ICR3H0_REG ICR3H
01313 #define ICR3H1_REG ICR3H
01314 #define ICR3H2_REG ICR3H
01315 #define ICR3H3_REG ICR3H
01316 #define ICR3H4_REG ICR3H
01317 #define ICR3H5_REG ICR3H
01318 #define ICR3H6_REG ICR3H
01319 #define ICR3H7_REG ICR3H
01320
01321
01322 #define DDE0_REG DDRE
01323 #define DDE1_REG DDRE
01324 #define DDE2_REG DDRE
01325 #define DDE3_REG DDRE
01326 #define DDE4_REG DDRE
01327 #define DDE5_REG DDRE
01328 #define DDE6_REG DDRE
01329 #define DDE7_REG DDRE
01330
01331
01332 #define UADD0_REG UDADDR
01333 #define UADD1_REG UDADDR
01334 #define UADD2_REG UDADDR
01335 #define UADD3_REG UDADDR
01336 #define UADD4_REG UDADDR
01337 #define UADD5_REG UDADDR
01338 #define UADD6_REG UDADDR
01339 #define ADDEN_REG UDADDR
01340
01341
01342 #define ICR3L0_REG ICR3L
01343 #define ICR3L1_REG ICR3L
01344 #define ICR3L2_REG ICR3L
01345 #define ICR3L3_REG ICR3L
01346 #define ICR3L4_REG ICR3L
01347 #define ICR3L5_REG ICR3L
01348 #define ICR3L6_REG ICR3L
01349 #define ICR3L7_REG ICR3L
01350
01351
01352 #define PORTE0_REG PORTE
01353 #define PORTE1_REG PORTE
01354 #define PORTE2_REG PORTE
01355 #define PORTE3_REG PORTE
01356 #define PORTE4_REG PORTE
01357 #define PORTE5_REG PORTE
01358 #define PORTE6_REG PORTE
01359 #define PORTE7_REG PORTE
01360
01361
01362 #define SPMEN_REG SPMCSR
01363 #define PGERS_REG SPMCSR
01364 #define PGWRT_REG SPMCSR
01365 #define BLBSET_REG SPMCSR
01366 #define RWWSRE_REG SPMCSR
01367 #define SIGRD_REG SPMCSR
01368 #define RWWSB_REG SPMCSR
01369 #define SPMIE_REG SPMCSR
01370
01371
01372 #define NBUSYBK0_REG UESTA0X
01373 #define NBUSYBK1_REG UESTA0X
01374
01375
01376
01377
01378
01379
01380
01381 #define PORTB0_REG PORTB
01382 #define PORTB1_REG PORTB
01383 #define PORTB2_REG PORTB
01384 #define PORTB3_REG PORTB
01385 #define PORTB4_REG PORTB
01386 #define PORTB5_REG PORTB
01387 #define PORTB6_REG PORTB
01388 #define PORTB7_REG PORTB
01389
01390
01391 #define ADCL0_REG ADCL
01392 #define ADCL1_REG ADCL
01393 #define ADCL2_REG ADCL
01394 #define ADCL3_REG ADCL
01395 #define ADCL4_REG ADCL
01396 #define ADCL5_REG ADCL
01397 #define ADCL6_REG ADCL
01398 #define ADCL7_REG ADCL
01399
01400
01401 #define ADCH0_REG ADCH
01402 #define ADCH1_REG ADCH
01403 #define ADCH2_REG ADCH
01404 #define ADCH3_REG ADCH
01405 #define ADCH4_REG ADCH
01406 #define ADCH5_REG ADCH
01407 #define ADCH6_REG ADCH
01408 #define ADCH7_REG ADCH
01409
01410
01411 #define OCR3BL0_REG OCR3BL
01412 #define OCR3BL1_REG OCR3BL
01413 #define OCR3BL2_REG OCR3BL
01414 #define OCR3BL3_REG OCR3BL
01415 #define OCR3BL4_REG OCR3BL
01416 #define OCR3BL5_REG OCR3BL
01417 #define OCR3BL6_REG OCR3BL
01418 #define OCR3BL7_REG OCR3BL
01419
01420
01421 #define OCR3BH0_REG OCR3BH
01422 #define OCR3BH1_REG OCR3BH
01423 #define OCR3BH2_REG OCR3BH
01424 #define OCR3BH3_REG OCR3BH
01425 #define OCR3BH4_REG OCR3BH
01426 #define OCR3BH5_REG OCR3BH
01427 #define OCR3BH6_REG OCR3BH
01428 #define OCR3BH7_REG OCR3BH
01429
01430
01431 #define TOIE2_REG TIMSK2
01432 #define OCIE2A_REG TIMSK2
01433 #define OCIE2B_REG TIMSK2
01434
01435
01436 #define TOIE3_REG TIMSK3
01437 #define OCIE3A_REG TIMSK3
01438 #define OCIE3B_REG TIMSK3
01439 #define OCIE3C_REG TIMSK3
01440 #define ICIE3_REG TIMSK3
01441
01442
01443 #define TOIE0_REG TIMSK0
01444 #define OCIE0A_REG TIMSK0
01445 #define OCIE0B_REG TIMSK0
01446
01447
01448 #define TOIE1_REG TIMSK1
01449 #define OCIE1A_REG TIMSK1
01450 #define OCIE1B_REG TIMSK1
01451 #define OCIE1C_REG TIMSK1
01452 #define ICIE1_REG TIMSK1
01453
01454
01455 #define PLOCK_REG PLLCSR
01456 #define PLLE_REG PLLCSR
01457 #define PLLP0_REG PLLCSR
01458 #define PLLP1_REG PLLCSR
01459 #define PLLP2_REG PLLCSR
01460
01461
01462 #define PCINT0_REG PCMSK0
01463 #define PCINT1_REG PCMSK0
01464 #define PCINT2_REG PCMSK0
01465 #define PCINT3_REG PCMSK0
01466 #define PCINT4_REG PCMSK0
01467 #define PCINT5_REG PCMSK0
01468 #define PCINT6_REG PCMSK0
01469 #define PCINT7_REG PCMSK0
01470
01471
01472 #define XMM0_REG XMCRB
01473 #define XMM1_REG XMCRB
01474 #define XMM2_REG XMCRB
01475 #define XMBK_REG XMCRB
01476
01477
01478 #define SRW00_REG XMCRA
01479 #define SRW01_REG XMCRA
01480 #define SRW10_REG XMCRA
01481 #define SRW11_REG XMCRA
01482 #define SRL0_REG XMCRA
01483 #define SRL1_REG XMCRA
01484 #define SRL2_REG XMCRA
01485 #define SRE_REG XMCRA
01486
01487
01488 #define PINC0_REG PINC
01489 #define PINC1_REG PINC
01490 #define PINC2_REG PINC
01491 #define PINC3_REG PINC
01492 #define PINC4_REG PINC
01493 #define PINC5_REG PINC
01494 #define PINC6_REG PINC
01495 #define PINC7_REG PINC
01496
01497
01498 #define TOV2_REG TIFR2
01499 #define OCF2A_REG TIFR2
01500 #define OCF2B_REG TIFR2
01501
01502
01503 #define INTF0_REG EIFR
01504 #define INTF1_REG EIFR
01505 #define INTF2_REG EIFR
01506 #define INTF3_REG EIFR
01507 #define INTF4_REG EIFR
01508 #define INTF5_REG EIFR
01509 #define INTF6_REG EIFR
01510 #define INTF7_REG EIFR
01511
01512
01513 #define PINF0_REG PINF
01514 #define PINF1_REG PINF
01515 #define PINF2_REG PINF
01516 #define PINF3_REG PINF
01517 #define PINF4_REG PINF
01518 #define PINF5_REG PINF
01519 #define PINF6_REG PINF
01520 #define PINF7_REG PINF
01521
01522
01523 #define PINE0_REG PINE
01524 #define PINE1_REG PINE
01525 #define PINE2_REG PINE
01526 #define PINE3_REG PINE
01527 #define PINE4_REG PINE
01528 #define PINE5_REG PINE
01529 #define PINE6_REG PINE
01530 #define PINE7_REG PINE
01531
01532
01533 #define PIND0_REG PIND
01534 #define PIND1_REG PIND
01535 #define PIND2_REG PIND
01536 #define PIND3_REG PIND
01537 #define PIND4_REG PIND
01538 #define PIND5_REG PIND
01539 #define PIND6_REG PIND
01540 #define PIND7_REG PIND
01541
01542
01543 #define TWAM0_REG TWAMR
01544 #define TWAM1_REG TWAMR
01545 #define TWAM2_REG TWAMR
01546 #define TWAM3_REG TWAMR
01547 #define TWAM4_REG TWAMR
01548 #define TWAM5_REG TWAMR
01549 #define TWAM6_REG TWAMR
01550
01551
01552 #define PRADC_REG PRR0
01553 #define PRSPI_REG PRR0
01554 #define PRTIM1_REG PRR0
01555 #define PRTIM0_REG PRR0
01556 #define PRTIM2_REG PRR0
01557 #define PRTWI_REG PRR0
01558
01559
01560 #define OCR1AL0_REG OCR1AL
01561 #define OCR1AL1_REG OCR1AL
01562 #define OCR1AL2_REG OCR1AL
01563 #define OCR1AL3_REG OCR1AL
01564 #define OCR1AL4_REG OCR1AL
01565 #define OCR1AL5_REG OCR1AL
01566 #define OCR1AL6_REG OCR1AL
01567 #define OCR1AL7_REG OCR1AL
01568
01569
01570 #define TOV0_REG TIFR0
01571 #define OCF0A_REG TIFR0
01572 #define OCF0B_REG TIFR0
01573
01574
01575 #define PRUSART1_REG PRR1
01576 #define PRTIM3_REG PRR1
01577 #define PRUSB_REG PRR1
01578
01579
01580 #define DDB0_REG DDRB
01581 #define DDB1_REG DDRB
01582 #define DDB2_REG DDRB
01583 #define DDB3_REG DDRB
01584 #define DDB4_REG DDRB
01585 #define DDB5_REG DDRB
01586 #define DDB6_REG DDRB
01587 #define DDB7_REG DDRB
01588
01589
01590 #define PRST0_REG UPRST
01591 #define PRST1_REG UPRST
01592 #define PRST2_REG UPRST
01593 #define PRST3_REG UPRST
01594 #define PRST4_REG UPRST
01595 #define PRST5_REG UPRST
01596 #define PRST6_REG UPRST
01597
01598
01599