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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085
00086 #define TIMER0_AVAILABLE
00087 #define TIMER1_AVAILABLE
00088 #define TIMER1A_AVAILABLE
00089 #define TIMER1B_AVAILABLE
00090 #define TIMER2_AVAILABLE
00091
00092
00093 #define SIG_OVERFLOW0_NUM 0
00094 #define SIG_OVERFLOW1_NUM 1
00095 #define SIG_OVERFLOW2_NUM 2
00096 #define SIG_OVERFLOW_TOTAL_NUM 3
00097
00098
00099 #define SIG_OUTPUT_COMPARE0_NUM 0
00100 #define SIG_OUTPUT_COMPARE1A_NUM 1
00101 #define SIG_OUTPUT_COMPARE1B_NUM 2
00102 #define SIG_OUTPUT_COMPARE2_NUM 3
00103 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00104
00105
00106 #define PWM0_NUM 0
00107 #define PWM1A_NUM 1
00108 #define PWM1B_NUM 2
00109 #define PWM2_NUM 3
00110 #define PWM_TOTAL_NUM 4
00111
00112
00113 #define SIG_INPUT_CAPTURE1_NUM 0
00114 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00115
00116
00117
00118 #define WDP0_REG WDTCR
00119 #define WDP1_REG WDTCR
00120 #define WDP2_REG WDTCR
00121 #define WDE_REG WDTCR
00122 #define WDCE_REG WDTCR
00123
00124
00125 #define ICR1H0_REG ICR1H
00126 #define ICR1H1_REG ICR1H
00127 #define ICR1H2_REG ICR1H
00128 #define ICR1H3_REG ICR1H
00129 #define ICR1H4_REG ICR1H
00130 #define ICR1H5_REG ICR1H
00131 #define ICR1H6_REG ICR1H
00132 #define ICR1H7_REG ICR1H
00133
00134
00135 #define MUX0_REG ADMUX
00136 #define MUX1_REG ADMUX
00137 #define MUX2_REG ADMUX
00138 #define MUX3_REG ADMUX
00139 #define MUX4_REG ADMUX
00140 #define ADLAR_REG ADMUX
00141 #define REFS0_REG ADMUX
00142 #define REFS1_REG ADMUX
00143
00144
00145 #define CS00_REG TCCR0
00146 #define CS01_REG TCCR0
00147 #define CS02_REG TCCR0
00148 #define WGM01_REG TCCR0
00149 #define COM00_REG TCCR0
00150 #define COM01_REG TCCR0
00151 #define WGM00_REG TCCR0
00152 #define FOC0_REG TCCR0
00153
00154
00155 #define C_REG SREG
00156 #define Z_REG SREG
00157 #define N_REG SREG
00158 #define V_REG SREG
00159 #define S_REG SREG
00160 #define H_REG SREG
00161 #define T_REG SREG
00162 #define I_REG SREG
00163
00164
00165 #define DDB0_REG DDRB
00166 #define DDB1_REG DDRB
00167 #define DDB2_REG DDRB
00168 #define DDB3_REG DDRB
00169 #define DDB4_REG DDRB
00170 #define DDB5_REG DDRB
00171 #define DDB6_REG DDRB
00172 #define DDB7_REG DDRB
00173
00174
00175 #define IVCE_REG GICR
00176 #define IVSEL_REG GICR
00177 #define INT2_REG GICR
00178 #define INT0_REG GICR
00179 #define INT1_REG GICR
00180
00181
00182 #define SPI2X_REG SPSR
00183 #define WCOL_REG SPSR
00184 #define SPIF_REG SPSR
00185
00186
00187 #define TWD0_REG TWDR
00188 #define TWD1_REG TWDR
00189 #define TWD2_REG TWDR
00190 #define TWD3_REG TWDR
00191 #define TWD4_REG TWDR
00192 #define TWD5_REG TWDR
00193 #define TWD6_REG TWDR
00194 #define TWD7_REG TWDR
00195
00196
00197 #define EEDR0_REG EEDR
00198 #define EEDR1_REG EEDR
00199 #define EEDR2_REG EEDR
00200 #define EEDR3_REG EEDR
00201 #define EEDR4_REG EEDR
00202 #define EEDR5_REG EEDR
00203 #define EEDR6_REG EEDR
00204 #define EEDR7_REG EEDR
00205
00206
00207 #define DDC0_REG DDRC
00208 #define DDC1_REG DDRC
00209 #define DDC2_REG DDRC
00210 #define DDC3_REG DDRC
00211 #define DDC4_REG DDRC
00212 #define DDC5_REG DDRC
00213 #define DDC6_REG DDRC
00214 #define DDC7_REG DDRC
00215
00216
00217 #define DDA0_REG DDRA
00218 #define DDA1_REG DDRA
00219 #define DDA2_REG DDRA
00220 #define DDA3_REG DDRA
00221 #define DDA4_REG DDRA
00222 #define DDA5_REG DDRA
00223 #define DDA6_REG DDRA
00224 #define DDA7_REG DDRA
00225
00226
00227 #define WGM10_REG TCCR1A
00228 #define WGM11_REG TCCR1A
00229 #define FOC1B_REG TCCR1A
00230 #define FOC1A_REG TCCR1A
00231 #define COM1B0_REG TCCR1A
00232 #define COM1B1_REG TCCR1A
00233 #define COM1A0_REG TCCR1A
00234 #define COM1A1_REG TCCR1A
00235
00236
00237 #define DDD0_REG DDRD
00238 #define DDD1_REG DDRD
00239 #define DDD2_REG DDRD
00240 #define DDD3_REG DDRD
00241 #define DDD4_REG DDRD
00242 #define DDD5_REG DDRD
00243 #define DDD6_REG DDRD
00244 #define DDD7_REG DDRD
00245
00246
00247 #define CS10_REG TCCR1B
00248 #define CS11_REG TCCR1B
00249 #define CS12_REG TCCR1B
00250 #define WGM12_REG TCCR1B
00251 #define WGM13_REG TCCR1B
00252 #define ICES1_REG TCCR1B
00253 #define ICNC1_REG TCCR1B
00254
00255
00256 #define INTF2_REG GIFR
00257 #define INTF0_REG GIFR
00258 #define INTF1_REG GIFR
00259
00260
00261 #define TOIE0_REG TIMSK
00262 #define OCIE0_REG TIMSK
00263 #define TOIE1_REG TIMSK
00264 #define OCIE1B_REG TIMSK
00265 #define OCIE1A_REG TIMSK
00266 #define TICIE1_REG TIMSK
00267 #define TOIE2_REG TIMSK
00268 #define OCIE2_REG TIMSK
00269
00270
00271 #define ADPS0_REG ADCSRA
00272 #define ADPS1_REG ADCSRA
00273 #define ADPS2_REG ADCSRA
00274 #define ADIE_REG ADCSRA
00275 #define ADIF_REG ADCSRA
00276 #define ADATE_REG ADCSRA
00277 #define ADSC_REG ADCSRA
00278 #define ADEN_REG ADCSRA
00279
00280
00281 #define MPCM_REG UCSRA
00282 #define U2X_REG UCSRA
00283 #define UPE_REG UCSRA
00284 #define DOR_REG UCSRA
00285 #define FE_REG UCSRA
00286 #define UDRE_REG UCSRA
00287 #define TXC_REG UCSRA
00288 #define RXC_REG UCSRA
00289
00290
00291 #define SPDR0_REG SPDR
00292 #define SPDR1_REG SPDR
00293 #define SPDR2_REG SPDR
00294 #define SPDR3_REG SPDR
00295 #define SPDR4_REG SPDR
00296 #define SPDR5_REG SPDR
00297 #define SPDR6_REG SPDR
00298 #define SPDR7_REG SPDR
00299
00300
00301 #define ADTS0_REG SFIOR
00302 #define ADTS1_REG SFIOR
00303 #define ADTS2_REG SFIOR
00304 #define PSR10_REG SFIOR
00305 #define PSR2_REG SFIOR
00306 #define PUD_REG SFIOR
00307 #define ACME_REG SFIOR
00308
00309
00310 #define ACIS0_REG ACSR
00311 #define ACIS1_REG ACSR
00312 #define ACIC_REG ACSR
00313 #define ACIE_REG ACSR
00314 #define ACI_REG ACSR
00315 #define ACO_REG ACSR
00316 #define ACBG_REG ACSR
00317 #define ACD_REG ACSR
00318
00319
00320 #define SP8_REG SPH
00321 #define SP9_REG SPH
00322 #define SP10_REG SPH
00323
00324
00325 #define OCR1BL0_REG OCR1BL
00326 #define OCR1BL1_REG OCR1BL
00327 #define OCR1BL2_REG OCR1BL
00328 #define OCR1BL3_REG OCR1BL
00329 #define OCR1BL4_REG OCR1BL
00330 #define OCR1BL5_REG OCR1BL
00331 #define OCR1BL6_REG OCR1BL
00332 #define OCR1BL7_REG OCR1BL
00333
00334
00335 #define TXB8_REG UCSRB
00336 #define RXB8_REG UCSRB
00337 #define UCSZ2_REG UCSRB
00338 #define TXEN_REG UCSRB
00339 #define RXEN_REG UCSRB
00340 #define UDRIE_REG UCSRB
00341 #define TXCIE_REG UCSRB
00342 #define RXCIE_REG UCSRB
00343
00344
00345 #define UCPOL_REG UCSRC
00346 #define UCSZ0_REG UCSRC
00347 #define UCSZ1_REG UCSRC
00348 #define USBS_REG UCSRC
00349 #define UPM0_REG UCSRC
00350 #define UPM1_REG UCSRC
00351 #define UMSEL_REG UCSRC
00352
00353
00354
00355 #define SP0_REG SPL
00356 #define SP1_REG SPL
00357 #define SP2_REG SPL
00358 #define SP3_REG SPL
00359 #define SP4_REG SPL
00360 #define SP5_REG SPL
00361 #define SP6_REG SPL
00362 #define SP7_REG SPL
00363
00364
00365 #define OCR1BH0_REG OCR1BH
00366 #define OCR1BH1_REG OCR1BH
00367 #define OCR1BH2_REG OCR1BH
00368 #define OCR1BH3_REG OCR1BH
00369 #define OCR1BH4_REG OCR1BH
00370 #define OCR1BH5_REG OCR1BH
00371 #define OCR1BH6_REG OCR1BH
00372 #define OCR1BH7_REG OCR1BH
00373
00374
00375 #define UDR0_REG UDR
00376 #define UDR1_REG UDR
00377 #define UDR2_REG UDR
00378 #define UDR3_REG UDR
00379 #define UDR4_REG UDR
00380 #define UDR5_REG UDR
00381 #define UDR6_REG UDR
00382 #define UDR7_REG UDR
00383
00384
00385 #define PIND0_REG PIND
00386 #define PIND1_REG PIND
00387 #define PIND2_REG PIND
00388 #define PIND3_REG PIND
00389 #define PIND4_REG PIND
00390 #define PIND5_REG PIND
00391 #define PIND6_REG PIND
00392 #define PIND7_REG PIND
00393
00394
00395 #define SPMEN_REG SPMCR
00396 #define PGERS_REG SPMCR
00397 #define PGWRT_REG SPMCR
00398 #define BLBSET_REG SPMCR
00399 #define RWWSRE_REG SPMCR
00400 #define RWWSB_REG SPMCR
00401 #define SPMIE_REG SPMCR
00402
00403
00404 #define UBRR8_REG UBRRH
00405 #define UBRR9_REG UBRRH
00406 #define UBRR10_REG UBRRH
00407 #define UBRR11_REG UBRRH
00408
00409
00410
00411 #define TWBR0_REG TWBR
00412 #define TWBR1_REG TWBR
00413 #define TWBR2_REG TWBR
00414 #define TWBR3_REG TWBR
00415 #define TWBR4_REG TWBR
00416 #define TWBR5_REG TWBR
00417 #define TWBR6_REG TWBR
00418 #define TWBR7_REG TWBR
00419
00420
00421 #define ADCL0_REG ADCL
00422 #define ADCL1_REG ADCL
00423 #define ADCL2_REG ADCL
00424 #define ADCL3_REG ADCL
00425 #define ADCL4_REG ADCL
00426 #define ADCL5_REG ADCL
00427 #define ADCL6_REG ADCL
00428 #define ADCL7_REG ADCL
00429
00430
00431 #define UBRR0_REG UBRRL
00432 #define UBRR1_REG UBRRL
00433 #define UBRR2_REG UBRRL
00434 #define UBRR3_REG UBRRL
00435 #define UBRR4_REG UBRRL
00436 #define UBRR5_REG UBRRL
00437 #define UBRR6_REG UBRRL
00438 #define UBRR7_REG UBRRL
00439
00440
00441 #define EERE_REG EECR
00442 #define EEWE_REG EECR
00443 #define EEMWE_REG EECR
00444 #define EERIE_REG EECR
00445
00446
00447 #define CAL0_REG OSCCAL
00448 #define CAL1_REG OSCCAL
00449 #define CAL2_REG OSCCAL
00450 #define CAL3_REG OSCCAL
00451 #define CAL4_REG OSCCAL
00452 #define CAL5_REG OSCCAL
00453 #define CAL6_REG OSCCAL
00454 #define CAL7_REG OSCCAL
00455
00456
00457 #define TCNT1L0_REG TCNT1L
00458 #define TCNT1L1_REG TCNT1L
00459 #define TCNT1L2_REG TCNT1L
00460 #define TCNT1L3_REG TCNT1L
00461 #define TCNT1L4_REG TCNT1L
00462 #define TCNT1L5_REG TCNT1L
00463 #define TCNT1L6_REG TCNT1L
00464 #define TCNT1L7_REG TCNT1L
00465
00466
00467 #define PORTB0_REG PORTB
00468 #define PORTB1_REG PORTB
00469 #define PORTB2_REG PORTB
00470 #define PORTB3_REG PORTB
00471 #define PORTB4_REG PORTB
00472 #define PORTB5_REG PORTB
00473 #define PORTB6_REG PORTB
00474 #define PORTB7_REG PORTB
00475
00476
00477 #define PORTD0_REG PORTD
00478 #define PORTD1_REG PORTD
00479 #define PORTD2_REG PORTD
00480 #define PORTD3_REG PORTD
00481 #define PORTD4_REG PORTD
00482 #define PORTD5_REG PORTD
00483 #define PORTD6_REG PORTD
00484 #define PORTD7_REG PORTD
00485
00486
00487 #define TCNT1H0_REG TCNT1H
00488 #define TCNT1H1_REG TCNT1H
00489 #define TCNT1H2_REG TCNT1H
00490 #define TCNT1H3_REG TCNT1H
00491 #define TCNT1H4_REG TCNT1H
00492 #define TCNT1H5_REG TCNT1H
00493 #define TCNT1H6_REG TCNT1H
00494 #define TCNT1H7_REG TCNT1H
00495
00496
00497 #define PORTC0_REG PORTC
00498 #define PORTC1_REG PORTC
00499 #define PORTC2_REG PORTC
00500 #define PORTC3_REG PORTC
00501 #define PORTC4_REG PORTC
00502 #define PORTC5_REG PORTC
00503 #define PORTC6_REG PORTC
00504 #define PORTC7_REG PORTC
00505
00506
00507 #define ADCH0_REG ADCH
00508 #define ADCH1_REG ADCH
00509 #define ADCH2_REG ADCH
00510 #define ADCH3_REG ADCH
00511 #define ADCH4_REG ADCH
00512 #define ADCH5_REG ADCH
00513 #define ADCH6_REG ADCH
00514 #define ADCH7_REG ADCH
00515
00516
00517 #define PORTA0_REG PORTA
00518 #define PORTA1_REG PORTA
00519 #define PORTA2_REG PORTA
00520 #define PORTA3_REG PORTA
00521 #define PORTA4_REG PORTA
00522 #define PORTA5_REG PORTA
00523 #define PORTA6_REG PORTA
00524 #define PORTA7_REG PORTA
00525
00526
00527 #define TWIE_REG TWCR
00528 #define TWEN_REG TWCR
00529 #define TWWC_REG TWCR
00530 #define TWSTO_REG TWCR
00531 #define TWSTA_REG TWCR
00532 #define TWEA_REG TWCR
00533 #define TWINT_REG TWCR
00534
00535
00536 #define TCNT0_0_REG TCNT0
00537 #define TCNT0_1_REG TCNT0
00538 #define TCNT0_2_REG TCNT0
00539 #define TCNT0_3_REG TCNT0
00540 #define TCNT0_4_REG TCNT0
00541 #define TCNT0_5_REG TCNT0
00542 #define TCNT0_6_REG TCNT0
00543 #define TCNT0_7_REG TCNT0
00544
00545
00546 #define ISC2_REG MCUCSR
00547 #define PORF_REG MCUCSR
00548 #define EXTRF_REG MCUCSR
00549 #define BORF_REG MCUCSR
00550 #define WDRF_REG MCUCSR
00551
00552
00553 #define TWGCE_REG TWAR
00554 #define TWA0_REG TWAR
00555 #define TWA1_REG TWAR
00556 #define TWA2_REG TWAR
00557 #define TWA3_REG TWAR
00558 #define TWA4_REG TWAR
00559 #define TWA5_REG TWAR
00560 #define TWA6_REG TWAR
00561
00562
00563 #define CS20_REG TCCR2
00564 #define CS21_REG TCCR2
00565 #define CS22_REG TCCR2
00566 #define WGM21_REG TCCR2
00567 #define COM20_REG TCCR2
00568 #define COM21_REG TCCR2
00569 #define WGM20_REG TCCR2
00570 #define FOC2_REG TCCR2
00571
00572
00573 #define TOV0_REG TIFR
00574 #define OCF0_REG TIFR
00575 #define TOV1_REG TIFR
00576 #define OCF1B_REG TIFR
00577 #define OCF1A_REG TIFR
00578 #define ICF1_REG TIFR
00579 #define TOV2_REG TIFR
00580 #define OCF2_REG TIFR
00581
00582
00583 #define EEAR8_REG EEARH
00584
00585
00586 #define TCNT2_0_REG TCNT2
00587 #define TCNT2_1_REG TCNT2
00588 #define TCNT2_2_REG TCNT2
00589 #define TCNT2_3_REG TCNT2
00590 #define TCNT2_4_REG TCNT2
00591 #define TCNT2_5_REG TCNT2
00592 #define TCNT2_6_REG TCNT2
00593 #define TCNT2_7_REG TCNT2
00594
00595
00596 #define EEAR0_REG EEARL
00597 #define EEAR1_REG EEARL
00598 #define EEAR2_REG EEARL
00599 #define EEAR3_REG EEARL
00600 #define EEAR4_REG EEARL
00601 #define EEAR5_REG EEARL
00602 #define EEAR6_REG EEARL
00603 #define EEAR7_REG EEARL
00604
00605
00606 #define TWPS0_REG TWSR
00607 #define TWPS1_REG TWSR
00608 #define TWS3_REG TWSR
00609 #define TWS4_REG TWSR
00610 #define TWS5_REG TWSR
00611 #define TWS6_REG TWSR
00612 #define TWS7_REG TWSR
00613
00614
00615 #define PINC0_REG PINC
00616 #define PINC1_REG PINC
00617 #define PINC2_REG PINC
00618 #define PINC3_REG PINC
00619 #define PINC4_REG PINC
00620 #define PINC5_REG PINC
00621 #define PINC6_REG PINC
00622 #define PINC7_REG PINC
00623
00624
00625 #define PINB0_REG PINB
00626 #define PINB1_REG PINB
00627 #define PINB2_REG PINB
00628 #define PINB3_REG PINB
00629 #define PINB4_REG PINB
00630 #define PINB5_REG PINB
00631 #define PINB6_REG PINB
00632 #define PINB7_REG PINB
00633
00634
00635 #define PINA0_REG PINA
00636 #define PINA1_REG PINA
00637 #define PINA2_REG PINA
00638 #define PINA3_REG PINA
00639 #define PINA4_REG PINA
00640 #define PINA5_REG PINA
00641 #define PINA6_REG PINA
00642 #define PINA7_REG PINA
00643
00644
00645 #define ISC00_REG MCUCR
00646 #define ISC01_REG MCUCR
00647 #define ISC10_REG MCUCR
00648 #define ISC11_REG MCUCR
00649 #define SM0_REG MCUCR
00650 #define SM1_REG MCUCR
00651 #define SE_REG MCUCR
00652 #define SM2_REG MCUCR
00653
00654
00655 #define OCR1AH0_REG OCR1AH
00656 #define OCR1AH1_REG OCR1AH
00657 #define OCR1AH2_REG OCR1AH
00658 #define OCR1AH3_REG OCR1AH
00659 #define OCR1AH4_REG OCR1AH
00660 #define OCR1AH5_REG OCR1AH
00661 #define OCR1AH6_REG OCR1AH
00662 #define OCR1AH7_REG OCR1AH
00663
00664
00665 #define OCR1AL0_REG OCR1AL
00666 #define OCR1AL1_REG OCR1AL
00667 #define OCR1AL2_REG OCR1AL
00668 #define OCR1AL3_REG OCR1AL
00669 #define OCR1AL4_REG OCR1AL
00670 #define OCR1AL5_REG OCR1AL
00671 #define OCR1AL6_REG OCR1AL
00672 #define OCR1AL7_REG OCR1AL
00673
00674
00675 #define SPR0_REG SPCR
00676 #define SPR1_REG SPCR
00677 #define CPHA_REG SPCR
00678 #define CPOL_REG SPCR
00679 #define MSTR_REG SPCR
00680 #define DORD_REG SPCR
00681 #define SPE_REG SPCR
00682 #define SPIE_REG SPCR
00683
00684
00685 #define TCR2UB_REG ASSR
00686 #define OCR2UB_REG ASSR
00687 #define TCN2UB_REG ASSR
00688 #define AS2_REG ASSR
00689
00690
00691 #define OCR0_0_REG OCR0
00692 #define OCR0_1_REG OCR0
00693 #define OCR0_2_REG OCR0
00694 #define OCR0_3_REG OCR0
00695 #define OCR0_4_REG OCR0
00696 #define OCR0_5_REG OCR0
00697 #define OCR0_6_REG OCR0
00698 #define OCR0_7_REG OCR0
00699
00700
00701 #define OCR2_0_REG OCR2
00702 #define OCR2_1_REG OCR2
00703 #define OCR2_2_REG OCR2
00704 #define OCR2_3_REG OCR2
00705 #define OCR2_4_REG OCR2
00706 #define OCR2_5_REG OCR2
00707 #define OCR2_6_REG OCR2
00708 #define OCR2_7_REG OCR2
00709
00710
00711 #define ICR1L0_REG ICR1L
00712 #define ICR1L1_REG ICR1L
00713 #define ICR1L2_REG ICR1L
00714 #define ICR1L3_REG ICR1L
00715 #define ICR1L4_REG ICR1L
00716 #define ICR1L5_REG ICR1L
00717 #define ICR1L6_REG ICR1L
00718 #define ICR1L7_REG ICR1L
00719
00720
00721 #define ADC0_PORT PORTA
00722 #define ADC0_BIT 0
00723
00724 #define ADC1_PORT PORTA
00725 #define ADC1_BIT 1
00726
00727 #define ADC2_PORT PORTA
00728 #define ADC2_BIT 2
00729
00730 #define ADC3_PORT PORTA
00731 #define ADC3_BIT 3
00732
00733 #define ADC4_PORT PORTA
00734 #define ADC4_BIT 4
00735
00736 #define ADc5_PORT PORTA
00737 #define ADc5_BIT 5
00738
00739 #define ADC6_PORT PORTA
00740 #define ADC6_BIT 6
00741
00742 #define ADC7_PORT PORTA
00743 #define ADC7_BIT 7
00744
00745 #define XCK_PORT PORTB
00746 #define XCK_BIT 0
00747 #define T0_PORT PORTB
00748 #define T0_BIT 0
00749
00750 #define T1_PORT PORTB
00751 #define T1_BIT 1
00752
00753 #define AIN0_PORT PORTB
00754 #define AIN0_BIT 2
00755 #define INT2_PORT PORTB
00756 #define INT2_BIT 2
00757
00758 #define AIN1_PORT PORTB
00759 #define AIN1_BIT 3
00760 #define OC0_PORT PORTB
00761 #define OC0_BIT 3
00762
00763 #define SS_PORT PORTB
00764 #define SS_BIT 4
00765
00766 #define MOSI_PORT PORTB
00767 #define MOSI_BIT 5
00768
00769 #define MISO_PORT PORTB
00770 #define MISO_BIT 6
00771
00772 #define SCK_PORT PORTB
00773 #define SCK_BIT 7
00774
00775 #define SCL_PORT PORTC
00776 #define SCL_BIT 0
00777
00778 #define SDA_PORT PORTC
00779 #define SDA_BIT 1
00780
00781
00782
00783
00784
00785 #define TOSC1_PORT PORTC
00786 #define TOSC1_BIT 6
00787
00788 #define TOSC2_PORT PORTC
00789 #define TOSC2_BIT 7
00790
00791 #define RXD_PORT PORTD
00792 #define RXD_BIT 0
00793
00794 #define TXD_PORT PORTD
00795 #define TXD_BIT 1
00796
00797 #define INT0_PORT PORTD
00798 #define INT0_BIT 2
00799
00800 #define INT1_PORT PORTD
00801 #define INT1_BIT 3
00802
00803 #define OC1B_PORT PORTD
00804 #define OC1B_BIT 4
00805
00806 #define OC1A_PORT PORTD
00807 #define OC1A_BIT 5
00808
00809 #define ICP_PORT PORTD
00810 #define ICP_BIT 6
00811
00812 #define OC2_PORT PORTD
00813 #define OC2_BIT 7
00814
00815