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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER1_AVAILABLE
00069 #define TIMER1A_AVAILABLE
00070 #define TIMER1B_AVAILABLE
00071
00072
00073 #define SIG_OVERFLOW0_NUM 0
00074 #define SIG_OVERFLOW1_NUM 1
00075 #define SIG_OVERFLOW_TOTAL_NUM 2
00076
00077
00078 #define SIG_OUTPUT_COMPARE0_NUM 0
00079 #define SIG_OUTPUT_COMPARE1A_NUM 1
00080 #define SIG_OUTPUT_COMPARE1B_NUM 2
00081 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 3
00082
00083
00084 #define PWM0_NUM 0
00085 #define PWM1A_NUM 1
00086 #define PWM1B_NUM 2
00087 #define PWM_TOTAL_NUM 3
00088
00089
00090 #define SIG_INPUT_CAPTURE1_NUM 0
00091 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00092
00093
00094
00095 #define UCPOL_REG UCSRC
00096 #define UCSZ0_REG UCSRC
00097 #define UCSZ1_REG UCSRC
00098 #define USBS_REG UCSRC
00099 #define UPM0_REG UCSRC
00100 #define UPM1_REG UCSRC
00101 #define UMSEL_REG UCSRC
00102
00103
00104
00105 #define WDP0_REG WDTCR
00106 #define WDP1_REG WDTCR
00107 #define WDP2_REG WDTCR
00108 #define WDE_REG WDTCR
00109 #define WDCE_REG WDTCR
00110
00111
00112 #define ICR1H0_REG ICR1H
00113 #define ICR1H1_REG ICR1H
00114 #define ICR1H2_REG ICR1H
00115 #define ICR1H3_REG ICR1H
00116 #define ICR1H4_REG ICR1H
00117 #define ICR1H5_REG ICR1H
00118 #define ICR1H6_REG ICR1H
00119 #define ICR1H7_REG ICR1H
00120
00121
00122 #define CS00_REG TCCR0
00123 #define CS01_REG TCCR0
00124 #define CS02_REG TCCR0
00125 #define WGM01_REG TCCR0
00126 #define COM00_REG TCCR0
00127 #define COM01_REG TCCR0
00128 #define WGM00_REG TCCR0
00129 #define FOC0_REG TCCR0
00130
00131
00132 #define C_REG SREG
00133 #define Z_REG SREG
00134 #define N_REG SREG
00135 #define V_REG SREG
00136 #define S_REG SREG
00137 #define H_REG SREG
00138 #define T_REG SREG
00139 #define I_REG SREG
00140
00141
00142 #define DDB0_REG DDRB
00143 #define DDB1_REG DDRB
00144 #define DDB2_REG DDRB
00145 #define DDB3_REG DDRB
00146 #define DDB4_REG DDRB
00147 #define DDB5_REG DDRB
00148 #define DDB6_REG DDRB
00149 #define DDB7_REG DDRB
00150
00151
00152 #define IVCE_REG GICR
00153 #define IVSEL_REG GICR
00154 #define INT2_REG GICR
00155 #define INT0_REG GICR
00156 #define INT1_REG GICR
00157
00158
00159 #define SPI2X_REG SPSR
00160 #define WCOL_REG SPSR
00161 #define SPIF_REG SPSR
00162
00163
00164 #define EEDR0_REG EEDR
00165 #define EEDR1_REG EEDR
00166 #define EEDR2_REG EEDR
00167 #define EEDR3_REG EEDR
00168 #define EEDR4_REG EEDR
00169 #define EEDR5_REG EEDR
00170 #define EEDR6_REG EEDR
00171 #define EEDR7_REG EEDR
00172
00173
00174 #define DDC0_REG DDRC
00175 #define DDC1_REG DDRC
00176 #define DDC2_REG DDRC
00177 #define DDC3_REG DDRC
00178 #define DDC4_REG DDRC
00179 #define DDC5_REG DDRC
00180 #define DDC6_REG DDRC
00181 #define DDC7_REG DDRC
00182
00183
00184 #define DDA0_REG DDRA
00185 #define DDA1_REG DDRA
00186 #define DDA2_REG DDRA
00187 #define DDA3_REG DDRA
00188 #define DDA4_REG DDRA
00189 #define DDA5_REG DDRA
00190 #define DDA6_REG DDRA
00191 #define DDA7_REG DDRA
00192
00193
00194 #define WGM10_REG TCCR1A
00195 #define WGM11_REG TCCR1A
00196 #define FOC1B_REG TCCR1A
00197 #define FOC1A_REG TCCR1A
00198 #define COM1B0_REG TCCR1A
00199 #define COM1B1_REG TCCR1A
00200 #define COM1A0_REG TCCR1A
00201 #define COM1A1_REG TCCR1A
00202
00203
00204 #define DDD0_REG DDRD
00205 #define DDD1_REG DDRD
00206 #define DDD2_REG DDRD
00207 #define DDD3_REG DDRD
00208 #define DDD4_REG DDRD
00209 #define DDD5_REG DDRD
00210 #define DDD6_REG DDRD
00211 #define DDD7_REG DDRD
00212
00213
00214 #define CS10_REG TCCR1B
00215 #define CS11_REG TCCR1B
00216 #define CS12_REG TCCR1B
00217 #define WGM12_REG TCCR1B
00218 #define WGM13_REG TCCR1B
00219 #define ICES1_REG TCCR1B
00220 #define ICNC1_REG TCCR1B
00221
00222
00223 #define INTF2_REG GIFR
00224 #define INTF0_REG GIFR
00225 #define INTF1_REG GIFR
00226
00227
00228 #define OCIE0_REG TIMSK
00229 #define TOIE0_REG TIMSK
00230 #define TICIE1_REG TIMSK
00231 #define OCIE1B_REG TIMSK
00232 #define OCIE1A_REG TIMSK
00233 #define TOIE1_REG TIMSK
00234
00235
00236 #define MPCM_REG UCSRA
00237 #define U2X_REG UCSRA
00238 #define UPE_REG UCSRA
00239 #define DOR_REG UCSRA
00240 #define FE_REG UCSRA
00241 #define UDRE_REG UCSRA
00242 #define TXC_REG UCSRA
00243 #define RXC_REG UCSRA
00244
00245
00246 #define SPDR0_REG SPDR
00247 #define SPDR1_REG SPDR
00248 #define SPDR2_REG SPDR
00249 #define SPDR3_REG SPDR
00250 #define SPDR4_REG SPDR
00251 #define SPDR5_REG SPDR
00252 #define SPDR6_REG SPDR
00253 #define SPDR7_REG SPDR
00254
00255
00256 #define PSR10_REG SFIOR
00257 #define PUD_REG SFIOR
00258 #define XMM0_REG SFIOR
00259 #define XMM1_REG SFIOR
00260 #define XMM2_REG SFIOR
00261 #define XMBK_REG SFIOR
00262
00263
00264 #define ACIS0_REG ACSR
00265 #define ACIS1_REG ACSR
00266 #define ACIC_REG ACSR
00267 #define ACIE_REG ACSR
00268 #define ACI_REG ACSR
00269 #define ACO_REG ACSR
00270 #define ACBG_REG ACSR
00271 #define ACD_REG ACSR
00272
00273
00274 #define SP8_REG SPH
00275 #define SP9_REG SPH
00276 #define SP10_REG SPH
00277 #define SP11_REG SPH
00278 #define SP12_REG SPH
00279 #define SP13_REG SPH
00280 #define SP14_REG SPH
00281 #define SP15_REG SPH
00282
00283
00284 #define OCR1BL0_REG OCR1BL
00285 #define OCR1BL1_REG OCR1BL
00286 #define OCR1BL2_REG OCR1BL
00287 #define OCR1BL3_REG OCR1BL
00288 #define OCR1BL4_REG OCR1BL
00289 #define OCR1BL5_REG OCR1BL
00290 #define OCR1BL6_REG OCR1BL
00291 #define OCR1BL7_REG OCR1BL
00292
00293
00294 #define TXB8_REG UCSRB
00295 #define RXB8_REG UCSRB
00296 #define UCSZ2_REG UCSRB
00297 #define TXEN_REG UCSRB
00298 #define RXEN_REG UCSRB
00299 #define UDRIE_REG UCSRB
00300 #define TXCIE_REG UCSRB
00301 #define RXCIE_REG UCSRB
00302
00303
00304 #define ISC2_REG EMCUCR
00305 #define SRW11_REG EMCUCR
00306 #define SRW00_REG EMCUCR
00307 #define SRW01_REG EMCUCR
00308 #define SRL0_REG EMCUCR
00309 #define SRL1_REG EMCUCR
00310 #define SRL2_REG EMCUCR
00311 #define SM0_REG EMCUCR
00312
00313
00314 #define SP0_REG SPL
00315 #define SP1_REG SPL
00316 #define SP2_REG SPL
00317 #define SP3_REG SPL
00318 #define SP4_REG SPL
00319 #define SP5_REG SPL
00320 #define SP6_REG SPL
00321 #define SP7_REG SPL
00322
00323
00324 #define OCR1BH0_REG OCR1BH
00325 #define OCR1BH1_REG OCR1BH
00326 #define OCR1BH2_REG OCR1BH
00327 #define OCR1BH3_REG OCR1BH
00328 #define OCR1BH4_REG OCR1BH
00329 #define OCR1BH5_REG OCR1BH
00330 #define OCR1BH6_REG OCR1BH
00331 #define OCR1BH7_REG OCR1BH
00332
00333
00334 #define UDR0_REG UDR
00335 #define UDR1_REG UDR
00336 #define UDR2_REG UDR
00337 #define UDR3_REG UDR
00338 #define UDR4_REG UDR
00339 #define UDR5_REG UDR
00340 #define UDR6_REG UDR
00341 #define UDR7_REG UDR
00342
00343
00344 #define PIND0_REG PIND
00345 #define PIND1_REG PIND
00346 #define PIND2_REG PIND
00347 #define PIND3_REG PIND
00348 #define PIND4_REG PIND
00349 #define PIND5_REG PIND
00350 #define PIND6_REG PIND
00351 #define PIND7_REG PIND
00352
00353
00354 #define SPMEN_REG SPMCR
00355 #define PGERS_REG SPMCR
00356 #define PGWRT_REG SPMCR
00357 #define BLBSET_REG SPMCR
00358 #define RWWSRE_REG SPMCR
00359 #define RWWSB_REG SPMCR
00360 #define SPMIE_REG SPMCR
00361
00362
00363 #define UBRR8_REG UBRRH
00364 #define UBRR9_REG UBRRH
00365 #define UBRR10_REG UBRRH
00366 #define UBRR11_REG UBRRH
00367
00368
00369
00370 #define DDE0_REG DDRE
00371 #define DDE1_REG DDRE
00372 #define DDE2_REG DDRE
00373
00374
00375 #define UBRR0_REG UBRRL
00376 #define UBRR1_REG UBRRL
00377 #define UBRR2_REG UBRRL
00378 #define UBRR3_REG UBRRL
00379 #define UBRR4_REG UBRRL
00380 #define UBRR5_REG UBRRL
00381 #define UBRR6_REG UBRRL
00382 #define UBRR7_REG UBRRL
00383
00384
00385 #define EERE_REG EECR
00386 #define EEWE_REG EECR
00387 #define EEMWE_REG EECR
00388 #define EERIE_REG EECR
00389
00390
00391 #define CAL0_REG OSCCAL
00392 #define CAL1_REG OSCCAL
00393 #define CAL2_REG OSCCAL
00394 #define CAL3_REG OSCCAL
00395 #define CAL4_REG OSCCAL
00396 #define CAL5_REG OSCCAL
00397 #define CAL6_REG OSCCAL
00398 #define CAL7_REG OSCCAL
00399
00400
00401 #define TCNT1L0_REG TCNT1L
00402 #define TCNT1L1_REG TCNT1L
00403 #define TCNT1L2_REG TCNT1L
00404 #define TCNT1L3_REG TCNT1L
00405 #define TCNT1L4_REG TCNT1L
00406 #define TCNT1L5_REG TCNT1L
00407 #define TCNT1L6_REG TCNT1L
00408 #define TCNT1L7_REG TCNT1L
00409
00410
00411 #define PORTB0_REG PORTB
00412 #define PORTB1_REG PORTB
00413 #define PORTB2_REG PORTB
00414 #define PORTB3_REG PORTB
00415 #define PORTB4_REG PORTB
00416 #define PORTB5_REG PORTB
00417 #define PORTB6_REG PORTB
00418 #define PORTB7_REG PORTB
00419
00420
00421 #define PORTD0_REG PORTD
00422 #define PORTD1_REG PORTD
00423 #define PORTD2_REG PORTD
00424 #define PORTD3_REG PORTD
00425 #define PORTD4_REG PORTD
00426 #define PORTD5_REG PORTD
00427 #define PORTD6_REG PORTD
00428 #define PORTD7_REG PORTD
00429
00430
00431 #define PORTE0_REG PORTE
00432 #define PORTE1_REG PORTE
00433 #define PORTE2_REG PORTE
00434
00435
00436 #define TCNT1H0_REG TCNT1H
00437 #define TCNT1H1_REG TCNT1H
00438 #define TCNT1H2_REG TCNT1H
00439 #define TCNT1H3_REG TCNT1H
00440 #define TCNT1H4_REG TCNT1H
00441 #define TCNT1H5_REG TCNT1H
00442 #define TCNT1H6_REG TCNT1H
00443 #define TCNT1H7_REG TCNT1H
00444
00445
00446 #define PORTC0_REG PORTC
00447 #define PORTC1_REG PORTC
00448 #define PORTC2_REG PORTC
00449 #define PORTC3_REG PORTC
00450 #define PORTC4_REG PORTC
00451 #define PORTC5_REG PORTC
00452 #define PORTC6_REG PORTC
00453 #define PORTC7_REG PORTC
00454
00455
00456 #define PORTA0_REG PORTA
00457 #define PORTA1_REG PORTA
00458 #define PORTA2_REG PORTA
00459 #define PORTA3_REG PORTA
00460 #define PORTA4_REG PORTA
00461 #define PORTA5_REG PORTA
00462 #define PORTA6_REG PORTA
00463 #define PORTA7_REG PORTA
00464
00465
00466 #define TCNT0_0_REG TCNT0
00467 #define TCNT0_1_REG TCNT0
00468 #define TCNT0_2_REG TCNT0
00469 #define TCNT0_3_REG TCNT0
00470 #define TCNT0_4_REG TCNT0
00471 #define TCNT0_5_REG TCNT0
00472 #define TCNT0_6_REG TCNT0
00473 #define TCNT0_7_REG TCNT0
00474
00475
00476 #define PORF_REG MCUCSR
00477 #define EXTRF_REG MCUCSR
00478 #define BORF_REG MCUCSR
00479 #define WDRF_REG MCUCSR
00480 #define SM2_REG MCUCSR
00481
00482
00483 #define OCF0_REG TIFR
00484 #define TOV0_REG TIFR
00485 #define ICF1_REG TIFR
00486 #define OCF1B_REG TIFR
00487 #define OCF1A_REG TIFR
00488 #define TOV1_REG TIFR
00489
00490
00491 #define EEAR8_REG EEARH
00492
00493
00494 #define EEAR0_REG EEARL
00495 #define EEAR1_REG EEARL
00496 #define EEAR2_REG EEARL
00497 #define EEAR3_REG EEARL
00498 #define EEAR4_REG EEARL
00499 #define EEAR5_REG EEARL
00500 #define EEAR6_REG EEARL
00501 #define EEAR7_REG EEARL
00502
00503
00504 #define PINC0_REG PINC
00505 #define PINC1_REG PINC
00506 #define PINC2_REG PINC
00507 #define PINC3_REG PINC
00508 #define PINC4_REG PINC
00509 #define PINC5_REG PINC
00510 #define PINC6_REG PINC
00511 #define PINC7_REG PINC
00512
00513
00514 #define PINB0_REG PINB
00515 #define PINB1_REG PINB
00516 #define PINB2_REG PINB
00517 #define PINB3_REG PINB
00518 #define PINB4_REG PINB
00519 #define PINB5_REG PINB
00520 #define PINB6_REG PINB
00521 #define PINB7_REG PINB
00522
00523
00524 #define PINA0_REG PINA
00525 #define PINA1_REG PINA
00526 #define PINA2_REG PINA
00527 #define PINA3_REG PINA
00528 #define PINA4_REG PINA
00529 #define PINA5_REG PINA
00530 #define PINA6_REG PINA
00531 #define PINA7_REG PINA
00532
00533
00534 #define PINE0_REG PINE
00535 #define PINE1_REG PINE
00536 #define PINE2_REG PINE
00537
00538
00539 #define ISC00_REG MCUCR
00540 #define ISC01_REG MCUCR
00541 #define ISC10_REG MCUCR
00542 #define ISC11_REG MCUCR
00543 #define SM1_REG MCUCR
00544 #define SE_REG MCUCR
00545 #define SRW10_REG MCUCR
00546 #define SRE_REG MCUCR
00547
00548
00549 #define OCR1AH0_REG OCR1AH
00550 #define OCR1AH1_REG OCR1AH
00551 #define OCR1AH2_REG OCR1AH
00552 #define OCR1AH3_REG OCR1AH
00553 #define OCR1AH4_REG OCR1AH
00554 #define OCR1AH5_REG OCR1AH
00555 #define OCR1AH6_REG OCR1AH
00556 #define OCR1AH7_REG OCR1AH
00557
00558
00559 #define OCR1AL0_REG OCR1AL
00560 #define OCR1AL1_REG OCR1AL
00561 #define OCR1AL2_REG OCR1AL
00562 #define OCR1AL3_REG OCR1AL
00563 #define OCR1AL4_REG OCR1AL
00564 #define OCR1AL5_REG OCR1AL
00565 #define OCR1AL6_REG OCR1AL
00566 #define OCR1AL7_REG OCR1AL
00567
00568
00569 #define OCR0_0_REG OCR0
00570 #define OCR0_1_REG OCR0
00571 #define OCR0_2_REG OCR0
00572 #define OCR0_3_REG OCR0
00573 #define OCR0_4_REG OCR0
00574 #define OCR0_5_REG OCR0
00575 #define OCR0_6_REG OCR0
00576 #define OCR0_7_REG OCR0
00577
00578
00579 #define SPR0_REG SPCR
00580 #define SPR1_REG SPCR
00581 #define CPHA_REG SPCR
00582 #define CPOL_REG SPCR
00583 #define MSTR_REG SPCR
00584 #define DORD_REG SPCR
00585 #define SPE_REG SPCR
00586 #define SPIE_REG SPCR
00587
00588
00589 #define ICR1L0_REG ICR1L
00590 #define ICR1L1_REG ICR1L
00591 #define ICR1L2_REG ICR1L
00592 #define ICR1L3_REG ICR1L
00593 #define ICR1L4_REG ICR1L
00594 #define ICR1L5_REG ICR1L
00595 #define ICR1L6_REG ICR1L
00596 #define ICR1L7_REG ICR1L
00597
00598
00599 #define AD0_PORT PORTA
00600 #define AD0_BIT 0
00601
00602 #define AD1_PORT PORTA
00603 #define AD1_BIT 1
00604
00605 #define AD2_PORT PORTA
00606 #define AD2_BIT 2
00607
00608 #define AD3_PORT PORTA
00609 #define AD3_BIT 3
00610
00611 #define AD4_PORT PORTA
00612 #define AD4_BIT 4
00613
00614 #define AD5_PORT PORTA
00615 #define AD5_BIT 5
00616
00617 #define AD6_PORT PORTA
00618 #define AD6_BIT 6
00619
00620 #define AD7_PORT PORTA
00621 #define AD7_BIT 7
00622
00623 #define OC0_PORT PORTB
00624 #define OC0_BIT 0
00625 #define T0_PORT PORTB
00626 #define T0_BIT 0
00627
00628 #define T1_PORT PORTB
00629 #define T1_BIT 1
00630
00631 #define AIN0_PORT PORTB
00632 #define AIN0_BIT 2
00633
00634 #define AIN1_PORT PORTB
00635 #define AIN1_BIT 3
00636
00637 #define SS_PORT PORTB
00638 #define SS_BIT 4
00639
00640 #define MOSI_PORT PORTB
00641 #define MOSI_BIT 5
00642
00643 #define MISO_PORT PORTB
00644 #define MISO_BIT 6
00645
00646 #define SCK_PORT PORTB
00647 #define SCK_BIT 7
00648
00649 #define A8_PORT PORTC
00650 #define A8_BIT 0
00651
00652 #define A9_PORT PORTC
00653 #define A9_BIT 1
00654
00655 #define A10_PORT PORTC
00656 #define A10_BIT 2
00657
00658 #define A11_PORT PORTC
00659 #define A11_BIT 3
00660
00661 #define A12_PORT PORTC
00662 #define A12_BIT 4
00663
00664 #define A13_PORT PORTC
00665 #define A13_BIT 5
00666
00667 #define A14_PORT PORTC
00668 #define A14_BIT 6
00669
00670 #define A15_PORT PORTC
00671 #define A15_BIT 7
00672
00673 #define RXD_PORT PORTD
00674 #define RXD_BIT 0
00675
00676 #define TXD_PORT PORTD
00677 #define TXD_BIT 1
00678
00679 #define INT0_PORT PORTD
00680 #define INT0_BIT 2
00681
00682 #define INT1_PORT PORTD
00683 #define INT1_BIT 3
00684
00685 #define XCK_PORT PORTD
00686 #define XCK_BIT 4
00687
00688 #define OC1A_PORT PORTD
00689 #define OC1A_BIT 5
00690
00691 #define WR_PORT PORTD
00692 #define WR_BIT 6
00693
00694 #define RD_PORT PORTD
00695 #define RD_BIT 7
00696
00697 #define ICP_PORT PORTE
00698 #define ICP_BIT 0
00699 #define INT2_PORT PORTE
00700 #define INT2_BIT 0
00701
00702 #define ALE_PORT PORTE
00703 #define ALE_BIT 1
00704
00705 #define OC1B_PORT PORTE
00706 #define OC1B_BIT 2
00707
00708