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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER1_AVAILABLE
00069
00070
00071 #define SIG_OVERFLOW0_NUM 0
00072 #define SIG_OVERFLOW1_NUM 1
00073 #define SIG_OVERFLOW_TOTAL_NUM 2
00074
00075
00076 #define SIG_OUTPUT_COMPARE1_NUM 0
00077 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
00078
00079
00080 #define PWM1_NUM 0
00081 #define PWM_TOTAL_NUM 1
00082
00083
00084 #define SIG_INPUT_CAPTURE1_NUM 0
00085 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00086
00087
00088
00089 #define WDP0_REG WDTCR
00090 #define WDP1_REG WDTCR
00091 #define WDP2_REG WDTCR
00092 #define WDE_REG WDTCR
00093 #define WDTOE_REG WDTCR
00094
00095
00096 #define INT0_REG GIMSK
00097 #define INT1_REG GIMSK
00098
00099
00100 #define MUX0_REG ADMUX
00101 #define MUX1_REG ADMUX
00102 #define MUX2_REG ADMUX
00103 #define ADCBG_REG ADMUX
00104
00105
00106 #define CS00_REG TCCR0
00107 #define CS01_REG TCCR0
00108 #define CS02_REG TCCR0
00109
00110
00111 #define C_REG SREG
00112 #define Z_REG SREG
00113 #define N_REG SREG
00114 #define V_REG SREG
00115 #define S_REG SREG
00116 #define H_REG SREG
00117 #define T_REG SREG
00118 #define I_REG SREG
00119
00120
00121 #define DDB0_REG DDRB
00122 #define DDB1_REG DDRB
00123 #define DDB2_REG DDRB
00124 #define DDB3_REG DDRB
00125 #define DDB4_REG DDRB
00126 #define DDB5_REG DDRB
00127
00128
00129 #define EEDR0_REG EEDR
00130 #define EEDR1_REG EEDR
00131 #define EEDR2_REG EEDR
00132 #define EEDR3_REG EEDR
00133 #define EEDR4_REG EEDR
00134 #define EEDR5_REG EEDR
00135 #define EEDR6_REG EEDR
00136 #define EEDR7_REG EEDR
00137
00138
00139 #define DDC0_REG DDRC
00140 #define DDC1_REG DDRC
00141 #define DDC2_REG DDRC
00142 #define DDC3_REG DDRC
00143 #define DDC4_REG DDRC
00144 #define DDC5_REG DDRC
00145
00146
00147 #define PIND0_REG PIND
00148 #define PIND1_REG PIND
00149 #define PIND2_REG PIND
00150 #define PIND3_REG PIND
00151 #define PIND4_REG PIND
00152 #define PIND5_REG PIND
00153 #define PIND6_REG PIND
00154 #define PIND7_REG PIND
00155
00156
00157 #define PWM10_REG TCCR1A
00158 #define PWM11_REG TCCR1A
00159 #define COM10_REG TCCR1A
00160 #define COM11_REG TCCR1A
00161
00162
00163 #define DDD0_REG DDRD
00164 #define DDD1_REG DDRD
00165 #define DDD2_REG DDRD
00166 #define DDD3_REG DDRD
00167 #define DDD4_REG DDRD
00168 #define DDD5_REG DDRD
00169 #define DDD6_REG DDRD
00170 #define DDD7_REG DDRD
00171
00172
00173 #define CS10_REG TCCR1B
00174 #define CS11_REG TCCR1B
00175 #define CS12_REG TCCR1B
00176 #define CTC1_REG TCCR1B
00177 #define ICES1_REG TCCR1B
00178 #define ICNC1_REG TCCR1B
00179
00180
00181 #define INTF0_REG GIFR
00182 #define INTF1_REG GIFR
00183
00184
00185 #define TOIE0_REG TIMSK
00186 #define TICIE1_REG TIMSK
00187 #define OCIE1_REG TIMSK
00188 #define TOIE1_REG TIMSK
00189
00190
00191 #define SPDR0_REG SPDR
00192 #define SPDR1_REG SPDR
00193 #define SPDR2_REG SPDR
00194 #define SPDR3_REG SPDR
00195 #define SPDR4_REG SPDR
00196 #define SPDR5_REG SPDR
00197 #define SPDR6_REG SPDR
00198 #define SPDR7_REG SPDR
00199
00200
00201 #define UBRRHI0_REG UBRRHI
00202 #define UBRRHI1_REG UBRRHI
00203 #define UBRRHI2_REG UBRRHI
00204 #define UBRRHI3_REG UBRRHI
00205
00206
00207 #define WCOL_REG SPSR
00208 #define SPIF_REG SPSR
00209
00210
00211 #define ACIS0_REG ACSR
00212 #define ACIS1_REG ACSR
00213 #define ACIC_REG ACSR
00214 #define ACIE_REG ACSR
00215 #define ACI_REG ACSR
00216 #define ACO_REG ACSR
00217 #define AINBG_REG ACSR
00218 #define ACD_REG ACSR
00219
00220
00221 #define ICR1H0_REG ICR1H
00222 #define ICR1H1_REG ICR1H
00223 #define ICR1H2_REG ICR1H
00224 #define ICR1H3_REG ICR1H
00225 #define ICR1H4_REG ICR1H
00226 #define ICR1H5_REG ICR1H
00227 #define ICR1H6_REG ICR1H
00228 #define ICR1H7_REG ICR1H
00229
00230
00231 #define MPCM_REG UCSRA
00232 #define OR_REG UCSRA
00233 #define FE_REG UCSRA
00234 #define UDRE_REG UCSRA
00235 #define TXC_REG UCSRA
00236 #define RXC_REG UCSRA
00237
00238
00239 #define TXB8_REG UCSRB
00240 #define RXB8_REG UCSRB
00241 #define CHR9_REG UCSRB
00242 #define TXEN_REG UCSRB
00243 #define RXEN_REG UCSRB
00244 #define UDRIE_REG UCSRB
00245 #define TXCIE_REG UCSRB
00246 #define RXCIE_REG UCSRB
00247
00248
00249 #define ICR1L0_REG ICR1L
00250 #define ICR1L1_REG ICR1L
00251 #define ICR1L2_REG ICR1L
00252 #define ICR1L3_REG ICR1L
00253 #define ICR1L4_REG ICR1L
00254 #define ICR1L5_REG ICR1L
00255 #define ICR1L6_REG ICR1L
00256 #define ICR1L7_REG ICR1L
00257
00258
00259 #define UBRR0_REG UBRR
00260 #define UBRR1_REG UBRR
00261 #define UBRR2_REG UBRR
00262 #define UBRR3_REG UBRR
00263 #define UBRR4_REG UBRR
00264 #define UBRR5_REG UBRR
00265 #define UBRR6_REG UBRR
00266 #define UBRR7_REG UBRR
00267
00268
00269 #define ADC0_REG ADCL
00270 #define ADC1_REG ADCL
00271 #define ADC2_REG ADCL
00272 #define ADC3_REG ADCL
00273 #define ADC4_REG ADCL
00274 #define ADC5_REG ADCL
00275 #define ADC6_REG ADCL
00276 #define ADC7_REG ADCL
00277
00278
00279 #define PORF_REG MCUSR
00280 #define EXTRF_REG MCUSR
00281 #define BORF_REG MCUSR
00282 #define WDRF_REG MCUSR
00283
00284
00285 #define EERE_REG EECR
00286 #define EEWE_REG EECR
00287 #define EEMWE_REG EECR
00288 #define EERIE_REG EECR
00289
00290
00291 #define TCNT1L0_REG TCNT1L
00292 #define TCNT1L1_REG TCNT1L
00293 #define TCNT1L2_REG TCNT1L
00294 #define TCNT1L3_REG TCNT1L
00295 #define TCNT1L4_REG TCNT1L
00296 #define TCNT1L5_REG TCNT1L
00297 #define TCNT1L6_REG TCNT1L
00298 #define TCNT1L7_REG TCNT1L
00299
00300
00301 #define PORTB0_REG PORTB
00302 #define PORTB1_REG PORTB
00303 #define PORTB2_REG PORTB
00304 #define PORTB3_REG PORTB
00305 #define PORTB4_REG PORTB
00306 #define PORTB5_REG PORTB
00307
00308
00309 #define PORTD0_REG PORTD
00310 #define PORTD1_REG PORTD
00311 #define PORTD2_REG PORTD
00312 #define PORTD3_REG PORTD
00313 #define PORTD4_REG PORTD
00314 #define PORTD5_REG PORTD
00315 #define PORTD6_REG PORTD
00316 #define PORTD7_REG PORTD
00317
00318
00319 #define EEAR0_REG EEAR
00320 #define EEAR1_REG EEAR
00321 #define EEAR2_REG EEAR
00322 #define EEAR3_REG EEAR
00323 #define EEAR4_REG EEAR
00324 #define EEAR5_REG EEAR
00325 #define EEAR6_REG EEAR
00326 #define EEAR7_REG EEAR
00327
00328
00329 #define TCNT1H0_REG TCNT1H
00330 #define TCNT1H1_REG TCNT1H
00331 #define TCNT1H2_REG TCNT1H
00332 #define TCNT1H3_REG TCNT1H
00333 #define TCNT1H4_REG TCNT1H
00334 #define TCNT1H5_REG TCNT1H
00335 #define TCNT1H6_REG TCNT1H
00336 #define TCNT1H7_REG TCNT1H
00337
00338
00339 #define PORTC0_REG PORTC
00340 #define PORTC1_REG PORTC
00341 #define PORTC2_REG PORTC
00342 #define PORTC3_REG PORTC
00343 #define PORTC4_REG PORTC
00344 #define PORTC5_REG PORTC
00345
00346
00347 #define ADC8_REG ADCH
00348 #define ADC9_REG ADCH
00349
00350
00351 #define TCNT00_REG TCNT0
00352 #define TCNT01_REG TCNT0
00353 #define TCNT02_REG TCNT0
00354 #define TCNT03_REG TCNT0
00355 #define TCNT04_REG TCNT0
00356 #define TCNT05_REG TCNT0
00357 #define TCNT06_REG TCNT0
00358 #define TCNT07_REG TCNT0
00359
00360
00361 #define TOV0_REG TIFR
00362 #define ICF1_REG TIFR
00363 #define OCF1_REG TIFR
00364 #define TOV1_REG TIFR
00365
00366
00367 #define UDR0_REG UDR
00368 #define UDR1_REG UDR
00369 #define UDR2_REG UDR
00370 #define UDR3_REG UDR
00371 #define UDR4_REG UDR
00372 #define UDR5_REG UDR
00373 #define UDR6_REG UDR
00374 #define UDR7_REG UDR
00375
00376
00377 #define OCR1AL0_REG OCR1L
00378 #define OCR1AL1_REG OCR1L
00379 #define OCR1AL2_REG OCR1L
00380 #define OCR1AL3_REG OCR1L
00381 #define OCR1AL4_REG OCR1L
00382 #define OCR1AL5_REG OCR1L
00383 #define OCR1AL6_REG OCR1L
00384 #define OCR1AL7_REG OCR1L
00385
00386
00387 #define ADPS0_REG ADCSR
00388 #define ADPS1_REG ADCSR
00389 #define ADPS2_REG ADCSR
00390 #define ADIE_REG ADCSR
00391 #define ADIF_REG ADCSR
00392 #define ADFR_REG ADCSR
00393 #define ADSC_REG ADCSR
00394 #define ADEN_REG ADCSR
00395
00396
00397 #define OCR1AH0_REG OCR1H
00398 #define OCR1AH1_REG OCR1H
00399 #define OCR1AH2_REG OCR1H
00400 #define OCR1AH3_REG OCR1H
00401 #define OCR1AH4_REG OCR1H
00402 #define OCR1AH5_REG OCR1H
00403 #define OCR1AH6_REG OCR1H
00404 #define OCR1AH7_REG OCR1H
00405
00406
00407 #define PINC0_REG PINC
00408 #define PINC1_REG PINC
00409 #define PINC2_REG PINC
00410 #define PINC3_REG PINC
00411 #define PINC4_REG PINC
00412 #define PINC5_REG PINC
00413
00414
00415 #define PINB0_REG PINB
00416 #define PINB1_REG PINB
00417 #define PINB2_REG PINB
00418 #define PINB3_REG PINB
00419 #define PINB4_REG PINB
00420 #define PINB5_REG PINB
00421
00422
00423 #define SP0_REG SP
00424 #define SP1_REG SP
00425 #define SP2_REG SP
00426 #define SP3_REG SP
00427 #define SP4_REG SP
00428 #define SP5_REG SP
00429 #define SP6_REG SP
00430 #define SP7_REG SP
00431
00432
00433 #define ISC00_REG MCUCR
00434 #define ISC01_REG MCUCR
00435 #define ISC10_REG MCUCR
00436 #define ISC11_REG MCUCR
00437 #define SM_REG MCUCR
00438 #define SE_REG MCUCR
00439
00440
00441 #define SPR0_REG SPCR
00442 #define SPR1_REG SPCR
00443 #define CPHA_REG SPCR
00444 #define CPOL_REG SPCR
00445 #define MSTR_REG SPCR
00446 #define DORD_REG SPCR
00447 #define SPE_REG SPCR
00448 #define SPIE_REG SPCR
00449
00450
00451 #define ADC0_PORT PORTC
00452 #define ADC0_BIT 0
00453
00454 #define ADC1_PORT PORTC
00455 #define ADC1_BIT 1
00456
00457 #define ADC2_PORT PORTC
00458 #define ADC2_BIT 2
00459
00460 #define ADC3_PORT PORTC
00461 #define ADC3_BIT 3
00462
00463 #define ADC4_PORT PORTC
00464 #define ADC4_BIT 4
00465
00466 #define ADC5_PORT PORTC
00467 #define ADC5_BIT 5
00468
00469 #define RXD_PORT PORTD
00470 #define RXD_BIT 0
00471
00472 #define TXD_PORT PORTD
00473 #define TXD_BIT 1
00474
00475 #define INT0_PORT PORTD
00476 #define INT0_BIT 2
00477
00478