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00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047
00048
00049
00050
00051 #define TIMER0_AVAILABLE
00052 #define TIMER1_AVAILABLE
00053 #define TIMER1A_AVAILABLE
00054 #define TIMER1B_AVAILABLE
00055
00056
00057 #define SIG_OVERFLOW0_NUM 0
00058 #define SIG_OVERFLOW1_NUM 1
00059 #define SIG_OVERFLOW_TOTAL_NUM 2
00060
00061
00062 #define SIG_OUTPUT_COMPARE1A_NUM 0
00063 #define SIG_OUTPUT_COMPARE1B_NUM 1
00064 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 2
00065
00066
00067 #define PWM1A_NUM 0
00068 #define PWM1B_NUM 1
00069 #define PWM_TOTAL_NUM 2
00070
00071
00072 #define SIG_INPUT_CAPTURE1_NUM 0
00073 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00074
00075
00076
00077 #define WDP0_REG WDTCR
00078 #define WDP1_REG WDTCR
00079 #define WDP2_REG WDTCR
00080 #define WDE_REG WDTCR
00081 #define WDTOE_REG WDTCR
00082
00083
00084 #define INT0_REG GIMSK
00085 #define INT1_REG GIMSK
00086
00087
00088 #define ICR1H0_REG ICR1H
00089 #define ICR1H1_REG ICR1H
00090 #define ICR1H2_REG ICR1H
00091 #define ICR1H3_REG ICR1H
00092 #define ICR1H4_REG ICR1H
00093 #define ICR1H5_REG ICR1H
00094 #define ICR1H6_REG ICR1H
00095 #define ICR1H7_REG ICR1H
00096
00097
00098 #define CS00_REG TCCR0
00099 #define CS01_REG TCCR0
00100 #define CS02_REG TCCR0
00101
00102
00103 #define C_REG SREG
00104 #define Z_REG SREG
00105 #define N_REG SREG
00106 #define V_REG SREG
00107 #define S_REG SREG
00108 #define H_REG SREG
00109 #define T_REG SREG
00110 #define I_REG SREG
00111
00112
00113 #define DDB0_REG DDRB
00114 #define DDB1_REG DDRB
00115 #define DDB2_REG DDRB
00116 #define DDB3_REG DDRB
00117 #define DDB4_REG DDRB
00118 #define DDB5_REG DDRB
00119 #define DDB6_REG DDRB
00120 #define DDB7_REG DDRB
00121
00122
00123 #define OR_REG USR
00124 #define FE_REG USR
00125 #define UDRE_REG USR
00126 #define TXC_REG USR
00127 #define RXC_REG USR
00128
00129
00130 #define EEDR0_REG EEDR
00131 #define EEDR1_REG EEDR
00132 #define EEDR2_REG EEDR
00133 #define EEDR3_REG EEDR
00134 #define EEDR4_REG EEDR
00135 #define EEDR5_REG EEDR
00136 #define EEDR6_REG EEDR
00137 #define EEDR7_REG EEDR
00138
00139
00140 #define DDC0_REG DDRC
00141 #define DDC1_REG DDRC
00142 #define DDC2_REG DDRC
00143 #define DDC3_REG DDRC
00144 #define DDC4_REG DDRC
00145 #define DDC5_REG DDRC
00146 #define DDC6_REG DDRC
00147 #define DDC7_REG DDRC
00148
00149
00150 #define DDA0_REG DDRA
00151 #define DDA1_REG DDRA
00152 #define DDA2_REG DDRA
00153 #define DDA3_REG DDRA
00154 #define DDA4_REG DDRA
00155 #define DDA5_REG DDRA
00156 #define DDA6_REG DDRA
00157 #define DDA7_REG DDRA
00158
00159
00160 #define PWM10_REG TCCR1A
00161 #define PWM11_REG TCCR1A
00162 #define COM1B0_REG TCCR1A
00163 #define COM1B1_REG TCCR1A
00164 #define COM1A0_REG TCCR1A
00165 #define COM1A1_REG TCCR1A
00166
00167
00168 #define DDD0_REG DDRD
00169 #define DDD1_REG DDRD
00170 #define DDD2_REG DDRD
00171 #define DDD3_REG DDRD
00172 #define DDD4_REG DDRD
00173 #define DDD5_REG DDRD
00174 #define DDD6_REG DDRD
00175 #define DDD7_REG DDRD
00176
00177
00178 #define CS10_REG TCCR1B
00179 #define CS11_REG TCCR1B
00180 #define CS12_REG TCCR1B
00181 #define CTC1_REG TCCR1B
00182 #define ICES1_REG TCCR1B
00183 #define ICNC1_REG TCCR1B
00184
00185
00186 #define INTF0_REG GIFR
00187 #define INTF1_REG GIFR
00188
00189
00190 #define TICIE1_REG TIMSK
00191 #define OCIE1B_REG TIMSK
00192 #define OCIE1A_REG TIMSK
00193 #define TOIE1_REG TIMSK
00194 #define TOIE0_REG TIMSK
00195
00196
00197 #define TXB8_REG UCR
00198 #define RXB8_REG UCR
00199 #define CHR9_REG UCR
00200 #define TXEN_REG UCR
00201 #define RXEN_REG UCR
00202 #define UDRIE_REG UCR
00203 #define TXCIE_REG UCR
00204 #define RXCIE_REG UCR
00205
00206
00207 #define SPDR0_REG SPDR
00208 #define SPDR1_REG SPDR
00209 #define SPDR2_REG SPDR
00210 #define SPDR3_REG SPDR
00211 #define SPDR4_REG SPDR
00212 #define SPDR5_REG SPDR
00213 #define SPDR6_REG SPDR
00214 #define SPDR7_REG SPDR
00215
00216
00217 #define WCOL_REG SPSR
00218 #define SPIF_REG SPSR
00219
00220
00221 #define ACIS0_REG ACSR
00222 #define ACIS1_REG ACSR
00223 #define ACIC_REG ACSR
00224 #define ACIE_REG ACSR
00225 #define ACI_REG ACSR
00226 #define ACO_REG ACSR
00227 #define ACD_REG ACSR
00228
00229
00230 #define SP8_REG SPH
00231 #define SP9_REG SPH
00232 #define SP10_REG SPH
00233 #define SP11_REG SPH
00234 #define SP12_REG SPH
00235 #define SP13_REG SPH
00236 #define SP14_REG SPH
00237 #define SP15_REG SPH
00238
00239
00240 #define OCR1BL0_REG OCR1BL
00241 #define OCR1BL1_REG OCR1BL
00242 #define OCR1BL2_REG OCR1BL
00243 #define OCR1BL3_REG OCR1BL
00244 #define OCR1BL4_REG OCR1BL
00245 #define OCR1BL5_REG OCR1BL
00246 #define OCR1BL6_REG OCR1BL
00247 #define OCR1BL7_REG OCR1BL
00248
00249
00250 #define ICR1L0_REG ICR1L
00251 #define ICR1L1_REG ICR1L
00252 #define ICR1L2_REG ICR1L
00253 #define ICR1L3_REG ICR1L
00254 #define ICR1L4_REG ICR1L
00255 #define ICR1L5_REG ICR1L
00256 #define ICR1L6_REG ICR1L
00257 #define ICR1L7_REG ICR1L
00258
00259
00260 #define OCR1BH0_REG OCR1BH
00261 #define OCR1BH1_REG OCR1BH
00262 #define OCR1BH2_REG OCR1BH
00263 #define OCR1BH3_REG OCR1BH
00264 #define OCR1BH4_REG OCR1BH
00265 #define OCR1BH5_REG OCR1BH
00266 #define OCR1BH6_REG OCR1BH
00267 #define OCR1BH7_REG OCR1BH
00268
00269
00270 #define PIND0_REG PIND
00271 #define PIND1_REG PIND
00272 #define PIND2_REG PIND
00273 #define PIND3_REG PIND
00274 #define PIND4_REG PIND
00275 #define PIND5_REG PIND
00276 #define PIND6_REG PIND
00277 #define PIND7_REG PIND
00278
00279
00280 #define SP0_REG SPL
00281 #define SP1_REG SPL
00282 #define SP2_REG SPL
00283 #define SP3_REG SPL
00284 #define SP4_REG SPL
00285 #define SP5_REG SPL
00286 #define SP6_REG SPL
00287 #define SP7_REG SPL
00288
00289
00290 #define EERE_REG EECR
00291 #define EEWE_REG EECR
00292 #define EEMWE_REG EECR
00293
00294
00295 #define TCNT1L0_REG TCNT1L
00296 #define TCNT1L1_REG TCNT1L
00297 #define TCNT1L2_REG TCNT1L
00298 #define TCNT1L3_REG TCNT1L
00299 #define TCNT1L4_REG TCNT1L
00300 #define TCNT1L5_REG TCNT1L
00301 #define TCNT1L6_REG TCNT1L
00302 #define TCNT1L7_REG TCNT1L
00303
00304
00305 #define PORTB0_REG PORTB
00306 #define PORTB1_REG PORTB
00307 #define PORTB2_REG PORTB
00308 #define PORTB3_REG PORTB
00309 #define PORTB4_REG PORTB
00310 #define PORTB5_REG PORTB
00311 #define PORTB6_REG PORTB
00312 #define PORTB7_REG PORTB
00313
00314
00315 #define PORTD0_REG PORTD
00316 #define PORTD1_REG PORTD
00317 #define PORTD2_REG PORTD
00318 #define PORTD3_REG PORTD
00319 #define PORTD4_REG PORTD
00320 #define PORTD5_REG PORTD
00321 #define PORTD6_REG PORTD
00322 #define PORTD7_REG PORTD
00323
00324
00325 #define EEAR0_REG EEAR
00326 #define EEAR1_REG EEAR
00327 #define EEAR2_REG EEAR
00328 #define EEAR3_REG EEAR
00329 #define EEAR4_REG EEAR
00330 #define EEAR5_REG EEAR
00331 #define EEAR6_REG EEAR
00332 #define EEAR7_REG EEAR
00333
00334
00335 #define TCNT1H0_REG TCNT1H
00336 #define TCNT1H1_REG TCNT1H
00337 #define TCNT1H2_REG TCNT1H
00338 #define TCNT1H3_REG TCNT1H
00339 #define TCNT1H4_REG TCNT1H
00340 #define TCNT1H5_REG TCNT1H
00341 #define TCNT1H6_REG TCNT1H
00342 #define TCNT1H7_REG TCNT1H
00343
00344
00345 #define PORTC0_REG PORTC
00346 #define PORTC1_REG PORTC
00347 #define PORTC2_REG PORTC
00348 #define PORTC3_REG PORTC
00349 #define PORTC4_REG PORTC
00350 #define PORTC5_REG PORTC
00351 #define PORTC6_REG PORTC
00352 #define PORTC7_REG PORTC
00353
00354
00355 #define PORTA0_REG PORTA
00356 #define PORTA1_REG PORTA
00357 #define PORTA2_REG PORTA
00358 #define PORTA3_REG PORTA
00359 #define PORTA4_REG PORTA
00360 #define PORTA5_REG PORTA
00361 #define PORTA6_REG PORTA
00362 #define PORTA7_REG PORTA
00363
00364
00365 #define TCNT00_REG TCNT0
00366 #define TCNT01_REG TCNT0
00367 #define TCNT02_REG TCNT0
00368 #define TCNT03_REG TCNT0
00369 #define TCNT04_REG TCNT0
00370 #define TCNT05_REG TCNT0
00371 #define TCNT06_REG TCNT0
00372 #define TCNT07_REG TCNT0
00373
00374
00375 #define UBRR0_REG UBRR
00376 #define UBRR1_REG UBRR
00377 #define UBRR2_REG UBRR
00378 #define UBRR3_REG UBRR
00379 #define UBRR4_REG UBRR
00380 #define UBRR5_REG UBRR
00381 #define UBRR6_REG UBRR
00382 #define UBRR7_REG UBRR
00383
00384
00385 #define ICF1_REG TIFR
00386 #define OCF1B_REG TIFR
00387 #define OCF1A_REG TIFR
00388 #define TOV1_REG TIFR
00389 #define TOV0_REG TIFR
00390
00391
00392 #define UDR0_REG UDR
00393 #define UDR1_REG UDR
00394 #define UDR2_REG UDR
00395 #define UDR3_REG UDR
00396 #define UDR4_REG UDR
00397 #define UDR5_REG UDR
00398 #define UDR6_REG UDR
00399 #define UDR7_REG UDR
00400
00401
00402 #define PINC0_REG PINC
00403 #define PINC1_REG PINC
00404 #define PINC2_REG PINC
00405 #define PINC3_REG PINC
00406 #define PINC4_REG PINC
00407 #define PINC5_REG PINC
00408 #define PINC6_REG PINC
00409 #define PINC7_REG PINC
00410
00411
00412 #define PINB0_REG PINB
00413 #define PINB1_REG PINB
00414 #define PINB2_REG PINB
00415 #define PINB3_REG PINB
00416 #define PINB4_REG PINB
00417 #define PINB5_REG PINB
00418 #define PINB6_REG PINB
00419 #define PINB7_REG PINB
00420
00421
00422 #define PINA0_REG PINA
00423 #define PINA1_REG PINA
00424 #define PINA2_REG PINA
00425 #define PINA3_REG PINA
00426 #define PINA4_REG PINA
00427 #define PINA5_REG PINA
00428 #define PINA6_REG PINA
00429 #define PINA7_REG PINA
00430
00431
00432 #define ISC00_REG MCUCR
00433 #define ISC01_REG MCUCR
00434 #define ISC10_REG MCUCR
00435 #define ISC11_REG MCUCR
00436 #define SM_REG MCUCR
00437 #define SE_REG MCUCR
00438 #define SRW_REG MCUCR
00439 #define SRE_REG MCUCR
00440
00441
00442 #define OCR1AH0_REG OCR1AH
00443 #define OCR1AH1_REG OCR1AH
00444 #define OCR1AH2_REG OCR1AH
00445 #define OCR1AH3_REG OCR1AH
00446 #define OCR1AH4_REG OCR1AH
00447 #define OCR1AH5_REG OCR1AH
00448 #define OCR1AH6_REG OCR1AH
00449 #define OCR1AH7_REG OCR1AH
00450
00451
00452 #define OCR1AL0_REG OCR1AL
00453 #define OCR1AL1_REG OCR1AL
00454 #define OCR1AL2_REG OCR1AL
00455 #define OCR1AL3_REG OCR1AL
00456 #define OCR1AL4_REG OCR1AL
00457 #define OCR1AL5_REG OCR1AL
00458 #define OCR1AL6_REG OCR1AL
00459 #define OCR1AL7_REG OCR1AL
00460
00461
00462 #define SPR0_REG SPCR
00463 #define SPR1_REG SPCR
00464 #define CPHA_REG SPCR
00465 #define CPOL_REG SPCR
00466 #define MSTR_REG SPCR
00467 #define DORD_REG SPCR
00468 #define SPE_REG SPCR
00469 #define SPIE_REG SPCR
00470
00471
00472 #define AD0_PORT PORTA
00473 #define AD0_BIT 0
00474
00475 #define AD1_PORT PORTA
00476 #define AD1_BIT 1
00477
00478 #define AD2_PORT PORTA
00479 #define AD2_BIT 2
00480
00481 #define AD3_PORT PORTA
00482 #define AD3_BIT 3
00483
00484 #define AD4_PORT PORTA
00485 #define AD4_BIT 4
00486
00487 #define AD5_PORT PORTA
00488 #define AD5_BIT 5
00489
00490 #define AD6_PORT PORTA
00491 #define AD6_BIT 6
00492
00493 #define AD7_PORT PORTA
00494 #define AD7_BIT 7
00495
00496 #define T0_PORT PORTB
00497 #define T0_BIT 0
00498
00499 #define T1_PORT PORTB
00500 #define T1_BIT 1
00501
00502 #define AIN0_PORT PORTB
00503 #define AIN0_BIT 2
00504
00505 #define AIN1_PORT PORTB
00506 #define AIN1_BIT 3
00507
00508 #define SS_PORT PORTB
00509 #define SS_BIT 4
00510
00511 #define MOSI_PORT PORTB
00512 #define MOSI_BIT 5
00513
00514 #define MISO_PORT PORTB
00515 #define MISO_BIT 6
00516
00517 #define SCK_PORT PORTB
00518 #define SCK_BIT 7
00519
00520 #define A8_PORT PORTC
00521 #define A8_BIT 0
00522
00523 #define A9_PORT PORTC
00524 #define A9_BIT 1
00525
00526 #define A10_PORT PORTC
00527 #define A10_BIT 2
00528
00529 #define A11_PORT PORTC
00530 #define A11_BIT 3
00531
00532 #define A12_PORT PORTC
00533 #define A12_BIT 4
00534
00535 #define A13_PORT PORTC
00536 #define A13_BIT 5
00537
00538 #define A14_PORT PORTC
00539 #define A14_BIT 6
00540
00541 #define A15_PORT PORTC
00542 #define A15_BIT 7
00543
00544 #define RXD_PORT PORTD
00545 #define RXD_BIT 0
00546
00547 #define TXD_PORT PORTD
00548 #define TXD_BIT 1
00549
00550 #define INT0_PORT PORTD
00551 #define INT0_BIT 2
00552
00553 #define INT1_PORT PORTD
00554 #define INT1_BIT 3
00555
00556
00557 #define OC1A_PORT PORTD
00558 #define OC1A_BIT 5
00559
00560 #define WR_PORT PORTD
00561 #define WR_BIT 6
00562
00563 #define RD_PORT PORTD
00564 #define RD_BIT 7
00565
00566