00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014
00015
00016
00017
00018
00019
00020
00021
00022
00023
00024
00025
00026
00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER1_AVAILABLE
00069
00070
00071 #define SIG_OVERFLOW0_NUM 0
00072 #define SIG_OVERFLOW1_NUM 1
00073 #define SIG_OVERFLOW_TOTAL_NUM 2
00074
00075
00076 #define SIG_OUTPUT_COMPARE1_NUM 0
00077 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 1
00078
00079
00080 #define PWM1_NUM 0
00081 #define PWM_TOTAL_NUM 1
00082
00083
00084 #define SIG_INPUT_CAPTURE1_NUM 0
00085 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00086
00087
00088
00089 #define WDP0_REG WDTCR
00090 #define WDP1_REG WDTCR
00091 #define WDP2_REG WDTCR
00092 #define WDE_REG WDTCR
00093 #define WDTOE_REG WDTCR
00094
00095
00096 #define INT0_REG GIMSK
00097 #define INT1_REG GIMSK
00098
00099
00100 #define CS00_REG TCCR0
00101 #define CS01_REG TCCR0
00102 #define CS02_REG TCCR0
00103
00104
00105 #define C_REG SREG
00106 #define Z_REG SREG
00107 #define N_REG SREG
00108 #define V_REG SREG
00109 #define S_REG SREG
00110 #define H_REG SREG
00111 #define T_REG SREG
00112 #define I_REG SREG
00113
00114
00115 #define DDB0_REG DDRB
00116 #define DDB1_REG DDRB
00117 #define DDB2_REG DDRB
00118 #define DDB3_REG DDRB
00119 #define DDB4_REG DDRB
00120 #define DDB5_REG DDRB
00121 #define DDB6_REG DDRB
00122 #define DDB7_REG DDRB
00123
00124
00125 #define OR_REG USR
00126 #define FE_REG USR
00127 #define UDRE_REG USR
00128 #define TXC_REG USR
00129 #define RXC_REG USR
00130
00131
00132 #define EEDR0_REG EEDR
00133 #define EEDR1_REG EEDR
00134 #define EEDR2_REG EEDR
00135 #define EEDR3_REG EEDR
00136 #define EEDR4_REG EEDR
00137 #define EEDR5_REG EEDR
00138 #define EEDR6_REG EEDR
00139 #define EEDR7_REG EEDR
00140
00141
00142 #define PIND0_REG PIND
00143 #define PIND1_REG PIND
00144 #define PIND2_REG PIND
00145 #define PIND3_REG PIND
00146 #define PIND4_REG PIND
00147 #define PIND5_REG PIND
00148 #define PIND6_REG PIND
00149
00150
00151 #define PWM10_REG TCCR1A
00152 #define PWM11_REG TCCR1A
00153 #define COM1A0_REG TCCR1A
00154 #define COM1A1_REG TCCR1A
00155
00156
00157 #define DDD0_REG DDRD
00158 #define DDD1_REG DDRD
00159 #define DDD2_REG DDRD
00160 #define DDD3_REG DDRD
00161 #define DDD4_REG DDRD
00162 #define DDD5_REG DDRD
00163 #define DDD6_REG DDRD
00164
00165
00166 #define CS10_REG TCCR1B
00167 #define CS11_REG TCCR1B
00168 #define CS12_REG TCCR1B
00169 #define CTC1_REG TCCR1B
00170 #define ICES1_REG TCCR1B
00171 #define ICNC1_REG TCCR1B
00172
00173
00174 #define INTF0_REG GIFR
00175 #define INTF1_REG GIFR
00176
00177
00178 #define TOIE0_REG TIMSK
00179 #define TICIE1_REG TIMSK
00180 #define OCIE1A_REG TIMSK
00181 #define TOIE1_REG TIMSK
00182
00183
00184 #define TXB8_REG UCR
00185 #define RXB8_REG UCR
00186 #define CHR9_REG UCR
00187 #define TXEN_REG UCR
00188 #define RXEN_REG UCR
00189 #define UDRIE_REG UCR
00190 #define TXCIE_REG UCR
00191 #define RXCIE_REG UCR
00192
00193
00194 #define ACIS0_REG ACSR
00195 #define ACIS1_REG ACSR
00196 #define ACIC_REG ACSR
00197 #define ACIE_REG ACSR
00198 #define ACI_REG ACSR
00199 #define ACO_REG ACSR
00200 #define ACD_REG ACSR
00201
00202
00203 #define ICR1H0_REG ICR1H
00204 #define ICR1H1_REG ICR1H
00205 #define ICR1H2_REG ICR1H
00206 #define ICR1H3_REG ICR1H
00207 #define ICR1H4_REG ICR1H
00208 #define ICR1H5_REG ICR1H
00209 #define ICR1H6_REG ICR1H
00210 #define ICR1H7_REG ICR1H
00211
00212
00213 #define ICR1L0_REG ICR1L
00214 #define ICR1L1_REG ICR1L
00215 #define ICR1L2_REG ICR1L
00216 #define ICR1L3_REG ICR1L
00217 #define ICR1L4_REG ICR1L
00218 #define ICR1L5_REG ICR1L
00219 #define ICR1L6_REG ICR1L
00220 #define ICR1L7_REG ICR1L
00221
00222
00223 #define SP0_REG SPL
00224 #define SP1_REG SPL
00225 #define SP2_REG SPL
00226 #define SP3_REG SPL
00227 #define SP4_REG SPL
00228 #define SP5_REG SPL
00229 #define SP6_REG SPL
00230 #define SP7_REG SPL
00231
00232
00233 #define EERE_REG EECR
00234 #define EEWE_REG EECR
00235 #define EEMWE_REG EECR
00236
00237
00238 #define TCNT1L0_REG TCNT1L
00239 #define TCNT1L1_REG TCNT1L
00240 #define TCNT1L2_REG TCNT1L
00241 #define TCNT1L3_REG TCNT1L
00242 #define TCNT1L4_REG TCNT1L
00243 #define TCNT1L5_REG TCNT1L
00244 #define TCNT1L6_REG TCNT1L
00245 #define TCNT1L7_REG TCNT1L
00246
00247
00248 #define TCNT1H0_REG TCNT1H
00249 #define TCNT1H1_REG TCNT1H
00250 #define TCNT1H2_REG TCNT1H
00251 #define TCNT1H3_REG TCNT1H
00252 #define TCNT1H4_REG TCNT1H
00253 #define TCNT1H5_REG TCNT1H
00254 #define TCNT1H6_REG TCNT1H
00255 #define TCNT1H7_REG TCNT1H
00256
00257
00258 #define PORTD0_REG PORTD
00259 #define PORTD1_REG PORTD
00260 #define PORTD2_REG PORTD
00261 #define PORTD3_REG PORTD
00262 #define PORTD4_REG PORTD
00263 #define PORTD5_REG PORTD
00264 #define PORTD6_REG PORTD
00265
00266
00267 #define EEAR0_REG EEAR
00268 #define EEAR1_REG EEAR
00269 #define EEAR2_REG EEAR
00270 #define EEAR3_REG EEAR
00271 #define EEAR4_REG EEAR
00272 #define EEAR5_REG EEAR
00273 #define EEAR6_REG EEAR
00274
00275
00276 #define PORTB0_REG PORTB
00277 #define PORTB1_REG PORTB
00278 #define PORTB2_REG PORTB
00279 #define PORTB3_REG PORTB
00280 #define PORTB4_REG PORTB
00281 #define PORTB5_REG PORTB
00282 #define PORTB6_REG PORTB
00283 #define PORTB7_REG PORTB
00284
00285
00286 #define TCNT00_REG TCNT0
00287 #define TCNT01_REG TCNT0
00288 #define TCNT02_REG TCNT0
00289 #define TCNT03_REG TCNT0
00290 #define TCNT04_REG TCNT0
00291 #define TCNT05_REG TCNT0
00292 #define TCNT06_REG TCNT0
00293 #define TCNT07_REG TCNT0
00294
00295
00296 #define UBRR0_REG UBRR
00297 #define UBRR1_REG UBRR
00298 #define UBRR2_REG UBRR
00299 #define UBRR3_REG UBRR
00300 #define UBRR4_REG UBRR
00301 #define UBRR5_REG UBRR
00302 #define UBRR6_REG UBRR
00303 #define UBRR7_REG UBRR
00304
00305
00306 #define TOV0_REG TIFR
00307 #define ICF1_REG TIFR
00308 #define OCF1A_REG TIFR
00309 #define TOV1_REG TIFR
00310
00311
00312 #define UDR0_REG UDR
00313 #define UDR1_REG UDR
00314 #define UDR2_REG UDR
00315 #define UDR3_REG UDR
00316 #define UDR4_REG UDR
00317 #define UDR5_REG UDR
00318 #define UDR6_REG UDR
00319 #define UDR7_REG UDR
00320
00321
00322 #define PINB0_REG PINB
00323 #define PINB1_REG PINB
00324 #define PINB2_REG PINB
00325 #define PINB3_REG PINB
00326 #define PINB4_REG PINB
00327 #define PINB5_REG PINB
00328 #define PINB6_REG PINB
00329 #define PINB7_REG PINB
00330
00331
00332 #define ISC00_REG MCUCR
00333 #define ISC01_REG MCUCR
00334 #define ISC10_REG MCUCR
00335 #define ISC11_REG MCUCR
00336 #define SM_REG MCUCR
00337 #define SE_REG MCUCR
00338
00339
00340 #define OCR1AH0_REG OCR1AH
00341 #define OCR1AH1_REG OCR1AH
00342 #define OCR1AH2_REG OCR1AH
00343 #define OCR1AH3_REG OCR1AH
00344 #define OCR1AH4_REG OCR1AH
00345 #define OCR1AH5_REG OCR1AH
00346 #define OCR1AH6_REG OCR1AH
00347 #define OCR1AH7_REG OCR1AH
00348
00349
00350 #define OCR1AL0_REG OCR1AL
00351 #define OCR1AL1_REG OCR1AL
00352 #define OCR1AL2_REG OCR1AL
00353 #define OCR1AL3_REG OCR1AL
00354 #define OCR1AL4_REG OCR1AL
00355 #define OCR1AL5_REG OCR1AL
00356 #define OCR1AL6_REG OCR1AL
00357 #define OCR1AL7_REG OCR1AL
00358
00359
00360 #define AIN0_PORT PORTB
00361 #define AIN0_BIT 0
00362
00363 #define AIN1_PORT PORTB
00364 #define AIN1_BIT 1
00365
00366
00367 #define OC1_PORT PORTB
00368 #define OC1_BIT 3
00369
00370
00371 #define MOSI_PORT PORTB
00372 #define MOSI_BIT 5
00373
00374 #define MISO_PORT PORTB
00375 #define MISO_BIT 6
00376
00377 #define SCK_PORT PORTB
00378 #define SCK_BIT 7
00379
00380 #define RXD_PORT PORTD
00381 #define RXD_BIT 0
00382
00383 #define TXD_PORT PORTD
00384 #define TXD_BIT 1
00385
00386 #define INT0_PORT PORTD
00387 #define INT0_BIT 2
00388
00389 #define INT1_PORT PORTD
00390 #define INT1_BIT 3
00391
00392 #define T0_PORT PORTD
00393 #define T0_BIT 4
00394
00395 #define T1_PORT PORTD
00396 #define T1_BIT 5
00397
00398 #define ICP_PORT PORTD
00399 #define ICP_BIT 6
00400
00401