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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066
00067 #define TIMER0_AVAILABLE
00068 #define TIMER0B_AVAILABLE
00069 #define TIMER1_AVAILABLE
00070 #define TIMER1A_AVAILABLE
00071 #define TIMER1B_AVAILABLE
00072
00073
00074 #define SIG_OVERFLOW0_NUM 0
00075 #define SIG_OVERFLOW1_NUM 1
00076 #define SIG_OVERFLOW_TOTAL_NUM 2
00077
00078
00079 #define SIG_OUTPUT_COMPARE0_NUM 0
00080 #define SIG_OUTPUT_COMPARE0B_NUM 1
00081 #define SIG_OUTPUT_COMPARE1A_NUM 2
00082 #define SIG_OUTPUT_COMPARE1B_NUM 3
00083 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 4
00084
00085
00086 #define PWM0_NUM 0
00087 #define PWM0B_NUM 1
00088 #define PWM1A_NUM 2
00089 #define PWM1B_NUM 3
00090 #define PWM_TOTAL_NUM 4
00091
00092
00093 #define SIG_INPUT_CAPTURE1_NUM 0
00094 #define SIG_INPUT_CAPTURE_TOTAL_NUM 1
00095
00096
00097
00098 #define EUDR0_REG EUDR
00099 #define EUDR1_REG EUDR
00100 #define EUDR2_REG EUDR
00101 #define EUDR3_REG EUDR
00102 #define EUDR4_REG EUDR
00103 #define EUDR5_REG EUDR
00104 #define EUDR6_REG EUDR
00105 #define EUDR7_REG EUDR
00106
00107
00108 #define MUX0_REG ADMUX
00109 #define MUX1_REG ADMUX
00110 #define MUX2_REG ADMUX
00111 #define MUX3_REG ADMUX
00112 #define ADLAR_REG ADMUX
00113 #define REFS0_REG ADMUX
00114 #define REFS1_REG ADMUX
00115
00116
00117 #define OCR2SB_8_REG OCR2SBH
00118 #define OCR2SB_9_REG OCR2SBH
00119 #define OCR2SB_10_REG OCR2SBH
00120 #define OCR2SB_11_REG OCR2SBH
00121
00122
00123 #define OCR2SB_0_REG OCR2SBL
00124 #define OCR2SB_1_REG OCR2SBL
00125 #define OCR2SB_2_REG OCR2SBL
00126 #define OCR2SB_3_REG OCR2SBL
00127 #define OCR2SB_4_REG OCR2SBL
00128 #define OCR2SB_5_REG OCR2SBL
00129 #define OCR2SB_6_REG OCR2SBL
00130 #define OCR2SB_7_REG OCR2SBL
00131
00132
00133 #define WDP0_REG WDTCSR
00134 #define WDP1_REG WDTCSR
00135 #define WDP2_REG WDTCSR
00136 #define WDE_REG WDTCSR
00137 #define WDCE_REG WDTCSR
00138 #define WDP3_REG WDTCSR
00139 #define WDIE_REG WDTCSR
00140 #define WDIF_REG WDTCSR
00141
00142
00143 #define EEDR0_REG EEDR
00144 #define EEDR1_REG EEDR
00145 #define EEDR2_REG EEDR
00146 #define EEDR3_REG EEDR
00147 #define EEDR4_REG EEDR
00148 #define EEDR5_REG EEDR
00149 #define EEDR6_REG EEDR
00150 #define EEDR7_REG EEDR
00151
00152
00153
00154
00155
00156
00157
00158
00159
00160
00161
00162
00163 #define OCR0SA_0_REG OCR0SAL
00164 #define OCR0SA_1_REG OCR0SAL
00165 #define OCR0SA_2_REG OCR0SAL
00166 #define OCR0SA_3_REG OCR0SAL
00167 #define OCR0SA_4_REG OCR0SAL
00168 #define OCR0SA_5_REG OCR0SAL
00169 #define OCR0SA_6_REG OCR0SAL
00170 #define OCR0SA_7_REG OCR0SAL
00171
00172
00173 #define SPDR0_REG SPDR
00174 #define SPDR1_REG SPDR
00175 #define SPDR2_REG SPDR
00176 #define SPDR3_REG SPDR
00177 #define SPDR4_REG SPDR
00178 #define SPDR5_REG SPDR
00179 #define SPDR6_REG SPDR
00180 #define SPDR7_REG SPDR
00181
00182
00183 #define SPI2X_REG SPSR
00184 #define WCOL_REG SPSR
00185 #define SPIF_REG SPSR
00186
00187
00188 #define SP8_REG SPH
00189 #define SP9_REG SPH
00190 #define SP10_REG SPH
00191 #define SP11_REG SPH
00192 #define SP12_REG SPH
00193 #define SP13_REG SPH
00194 #define SP14_REG SPH
00195 #define SP15_REG SPH
00196
00197
00198 #define MPCM_REG UCSRA
00199 #define U2X_REG UCSRA
00200 #define UPE_REG UCSRA
00201 #define DOR_REG UCSRA
00202 #define FE_REG UCSRA
00203 #define UDRE_REG UCSRA
00204 #define TXC_REG UCSRA
00205 #define RXC_REG UCSRA
00206
00207
00208 #define TXB8_REG UCSRB
00209 #define RXB8_REG UCSRB
00210 #define UCSZ2_REG UCSRB
00211 #define TXEN_REG UCSRB
00212 #define RXEN_REG UCSRB
00213 #define UDRIE_REG UCSRB
00214 #define TXCIE_REG UCSRB
00215 #define RXCIE_REG UCSRB
00216
00217
00218 #define UCPOL_REG UCSRC
00219 #define UCSZ0_REG UCSRC
00220 #define UCSZ1_REG UCSRC
00221 #define USBS_REG UCSRC
00222 #define UPM0_REG UCSRC
00223 #define UPM1_REG UCSRC
00224 #define UMSEL0_REG UCSRC
00225
00226
00227 #define SP0_REG SPL
00228 #define SP1_REG SPL
00229 #define SP2_REG SPL
00230 #define SP3_REG SPL
00231 #define SP4_REG SPL
00232 #define SP5_REG SPL
00233 #define SP6_REG SPL
00234 #define SP7_REG SPL
00235
00236
00237 #define AC1M0_REG AC1CON
00238 #define AC1M1_REG AC1CON
00239 #define AC1M2_REG AC1CON
00240 #define AC1ICE_REG AC1CON
00241 #define AC1IS0_REG AC1CON
00242 #define AC1IS1_REG AC1CON
00243 #define AC1IE_REG AC1CON
00244 #define AC1EN_REG AC1CON
00245
00246
00247 #define PRADC_REG PRR
00248 #define PRUSART0_REG PRR
00249 #define PRSPI_REG PRR
00250 #define PRTIM0_REG PRR
00251 #define PRTIM1_REG PRR
00252 #define PRPSC0_REG PRR
00253 #define PRPSC1_REG PRR
00254 #define PRPSC2_REG PRR
00255
00256
00257 #define PCLKSEL0_REG PCNF0
00258 #define POP0_REG PCNF0
00259 #define PMODE00_REG PCNF0
00260 #define PMODE01_REG PCNF0
00261 #define PLOCK0_REG PCNF0
00262 #define PALOCK0_REG PCNF0
00263 #define PFIFTY0_REG PCNF0
00264
00265
00266 #define POME2_REG PCNF2
00267 #define PCLKSEL2_REG PCNF2
00268 #define POP2_REG PCNF2
00269 #define PMODE20_REG PCNF2
00270 #define PMODE21_REG PCNF2
00271 #define PLOCK2_REG PCNF2
00272 #define PALOCK2_REG PCNF2
00273 #define PFIFTY2_REG PCNF2
00274
00275
00276 #define TCNT1L0_REG TCNT1L
00277 #define TCNT1L1_REG TCNT1L
00278 #define TCNT1L2_REG TCNT1L
00279 #define TCNT1L3_REG TCNT1L
00280 #define TCNT1L4_REG TCNT1L
00281 #define TCNT1L5_REG TCNT1L
00282 #define TCNT1L6_REG TCNT1L
00283 #define TCNT1L7_REG TCNT1L
00284
00285
00286 #define PORTD0_REG PORTD
00287 #define PORTD1_REG PORTD
00288 #define PORTD2_REG PORTD
00289 #define PORTD3_REG PORTD
00290 #define PORTD4_REG PORTD
00291 #define PORTD5_REG PORTD
00292 #define PORTD6_REG PORTD
00293 #define PORTD7_REG PORTD
00294
00295
00296 #define PORTE0_REG PORTE
00297 #define PORTE1_REG PORTE
00298 #define PORTE2_REG PORTE
00299
00300
00301 #define TCNT1H0_REG TCNT1H
00302 #define TCNT1H1_REG TCNT1H
00303 #define TCNT1H2_REG TCNT1H
00304 #define TCNT1H3_REG TCNT1H
00305 #define TCNT1H4_REG TCNT1H
00306 #define TCNT1H5_REG TCNT1H
00307 #define TCNT1H6_REG TCNT1H
00308 #define TCNT1H7_REG TCNT1H
00309
00310
00311 #define AMP1TS0_REG AMP1CSR
00312 #define AMP1TS1_REG AMP1CSR
00313 #define AMP1G0_REG AMP1CSR
00314 #define AMP1G1_REG AMP1CSR
00315 #define AMP1IS_REG AMP1CSR
00316 #define AMP1EN_REG AMP1CSR
00317
00318
00319 #define AC2M0_REG AC2CON
00320 #define AC2M1_REG AC2CON
00321 #define AC2M2_REG AC2CON
00322 #define AC2IS0_REG AC2CON
00323 #define AC2IS1_REG AC2CON
00324 #define AC2IE_REG AC2CON
00325 #define AC2EN_REG AC2CON
00326
00327
00328 #define INT0_REG EIMSK
00329 #define INT1_REG EIMSK
00330 #define INT2_REG EIMSK
00331
00332
00333 #define PRFM0A0_REG PFRC0A
00334 #define PRFM0A1_REG PFRC0A
00335 #define PRFM0A2_REG PFRC0A
00336 #define PRFM0A3_REG PFRC0A
00337 #define PFLTE0A_REG PFRC0A
00338 #define PELEV0A_REG PFRC0A
00339 #define PISEL0A_REG PFRC0A
00340 #define PCAE0A_REG PFRC0A
00341
00342
00343 #define PRFM0B0_REG PFRC0B
00344 #define PRFM0B1_REG PFRC0B
00345 #define PRFM0B2_REG PFRC0B
00346 #define PRFM0B3_REG PFRC0B
00347 #define PFLTE0B_REG PFRC0B
00348 #define PELEV0B_REG PFRC0B
00349 #define PISEL0B_REG PFRC0B
00350 #define PCAE0B_REG PFRC0B
00351
00352
00353 #define ISC00_REG EICRA
00354 #define ISC01_REG EICRA
00355 #define ISC10_REG EICRA
00356 #define ISC11_REG EICRA
00357 #define ISC20_REG EICRA
00358 #define ISC21_REG EICRA
00359
00360
00361 #define ADC0D_REG DIDR0
00362 #define ADC1D_REG DIDR0
00363 #define ADC2D_REG DIDR0
00364 #define ADC3D_REG DIDR0
00365 #define ADC4D_REG DIDR0
00366 #define ADC5D_REG DIDR0
00367 #define ADC6D_REG DIDR0
00368 #define ADC7D_REG DIDR0
00369
00370
00371 #define ADC8D_REG DIDR1
00372 #define ADC9D_REG DIDR1
00373 #define ADC10D_REG DIDR1
00374 #define AMP0ND_REG DIDR1
00375 #define AMP0PD_REG DIDR1
00376 #define ACMP0D_REG DIDR1
00377
00378
00379 #define CLKPS0_REG CLKPR
00380 #define CLKPS1_REG CLKPR
00381 #define CLKPS2_REG CLKPR
00382 #define CLKPS3_REG CLKPR
00383 #define CLKPCE_REG CLKPR
00384
00385
00386 #define OCR0RB_8_REG OCR0RBH
00387 #define OCR0RB_9_REG OCR0RBH
00388 #define OCR0RB_00_REG OCR0RBH
00389 #define OCR0RB_01_REG OCR0RBH
00390 #define OCR0RB_02_REG OCR0RBH
00391 #define OCR0RB_03_REG OCR0RBH
00392 #define OCR0RB_04_REG OCR0RBH
00393 #define OCR0RB_05_REG OCR0RBH
00394
00395
00396 #define C_REG SREG
00397 #define Z_REG SREG
00398 #define N_REG SREG
00399 #define V_REG SREG
00400 #define S_REG SREG
00401 #define H_REG SREG
00402 #define T_REG SREG
00403 #define I_REG SREG
00404
00405
00406 #define DDB0_REG DDRB
00407 #define DDB1_REG DDRB
00408 #define DDB2_REG DDRB
00409 #define DDB3_REG DDRB
00410 #define DDB4_REG DDRB
00411 #define DDB5_REG DDRB
00412 #define DDB6_REG DDRB
00413 #define DDB7_REG DDRB
00414
00415
00416 #define PEOPE2_REG PIM2
00417 #define PEVE2A_REG PIM2
00418 #define PEVE2B_REG PIM2
00419 #define PSEIE2_REG PIM2
00420
00421
00422 #define WGM10_REG TCCR1A
00423 #define WGM11_REG TCCR1A
00424 #define COM1B0_REG TCCR1A
00425 #define COM1B1_REG TCCR1A
00426 #define COM1A0_REG TCCR1A
00427 #define COM1A1_REG TCCR1A
00428
00429
00430 #define FOC1B_REG TCCR1C
00431 #define FOC1A_REG TCCR1C
00432
00433
00434 #define CS10_REG TCCR1B
00435 #define CS11_REG TCCR1B
00436 #define CS12_REG TCCR1B
00437 #define WGM12_REG TCCR1B
00438 #define WGM13_REG TCCR1B
00439 #define ICES1_REG TCCR1B
00440 #define ICNC1_REG TCCR1B
00441
00442
00443 #define CAL0_REG OSCCAL
00444 #define CAL1_REG OSCCAL
00445 #define CAL2_REG OSCCAL
00446 #define CAL3_REG OSCCAL
00447 #define CAL4_REG OSCCAL
00448 #define CAL5_REG OSCCAL
00449 #define CAL6_REG OSCCAL
00450
00451
00452 #define OCR0RA_0_REG OCR0RAL
00453 #define OCR0RA_1_REG OCR0RAL
00454 #define OCR0RA_2_REG OCR0RAL
00455 #define OCR0RA_3_REG OCR0RAL
00456 #define OCR0RA_4_REG OCR0RAL
00457 #define OCR0RA_5_REG OCR0RAL
00458 #define OCR0RA_6_REG OCR0RAL
00459 #define OCR0RA_7_REG OCR0RAL
00460
00461
00462 #define GPIOR10_REG GPIOR1
00463 #define GPIOR11_REG GPIOR1
00464 #define GPIOR12_REG GPIOR1
00465 #define GPIOR13_REG GPIOR1
00466 #define GPIOR14_REG GPIOR1
00467 #define GPIOR15_REG GPIOR1
00468 #define GPIOR16_REG GPIOR1
00469 #define GPIOR17_REG GPIOR1
00470
00471
00472 #define GPIOR00_REG GPIOR0
00473 #define GPIOR01_REG GPIOR0
00474 #define GPIOR02_REG GPIOR0
00475 #define GPIOR03_REG GPIOR0
00476 #define GPIOR04_REG GPIOR0
00477 #define GPIOR05_REG GPIOR0
00478 #define GPIOR06_REG GPIOR0
00479 #define GPIOR07_REG GPIOR0
00480
00481
00482 #define GPIOR30_REG GPIOR3
00483 #define GPIOR31_REG GPIOR3
00484 #define GPIOR32_REG GPIOR3
00485 #define GPIOR33_REG GPIOR3
00486 #define GPIOR34_REG GPIOR3
00487 #define GPIOR35_REG GPIOR3
00488 #define GPIOR36_REG GPIOR3
00489 #define GPIOR37_REG GPIOR3
00490
00491
00492 #define GPIOR20_REG GPIOR2
00493 #define GPIOR21_REG GPIOR2
00494 #define GPIOR22_REG GPIOR2
00495 #define GPIOR23_REG GPIOR2
00496 #define GPIOR24_REG GPIOR2
00497 #define GPIOR25_REG GPIOR2
00498 #define GPIOR26_REG GPIOR2
00499 #define GPIOR27_REG GPIOR2
00500
00501
00502 #define PEOP0_REG PIFR0
00503 #define PRN00_REG PIFR0
00504 #define PRN01_REG PIFR0
00505 #define PEV0A_REG PIFR0
00506 #define PEV0B_REG PIFR0
00507 #define PSEI0_REG PIFR0
00508
00509
00510 #define DDE0_REG DDRE
00511 #define DDE1_REG DDRE
00512 #define DDE2_REG DDRE
00513
00514
00515 #define TCNT0_0_REG TCNT0
00516 #define TCNT0_1_REG TCNT0
00517 #define TCNT0_2_REG TCNT0
00518 #define TCNT0_3_REG TCNT0
00519 #define TCNT0_4_REG TCNT0
00520 #define TCNT0_5_REG TCNT0
00521 #define TCNT0_6_REG TCNT0
00522 #define TCNT0_7_REG TCNT0
00523
00524
00525 #define CS00_REG TCCR0B
00526 #define CS01_REG TCCR0B
00527 #define CS02_REG TCCR0B
00528 #define WGM02_REG TCCR0B
00529 #define FOC0B_REG TCCR0B
00530 #define FOC0A_REG TCCR0B
00531
00532
00533 #define WGM00_REG TCCR0A
00534 #define WGM01_REG TCCR0A
00535 #define COM0B0_REG TCCR0A
00536 #define COM0B1_REG TCCR0A
00537 #define COM0A0_REG TCCR0A
00538 #define COM0A1_REG TCCR0A
00539
00540
00541 #define PRFM2B0_REG PFRC2B
00542 #define PRFM2B1_REG PFRC2B
00543 #define PRFM2B2_REG PFRC2B
00544 #define PRFM2B3_REG PFRC2B
00545 #define PFLTE2B_REG PFRC2B
00546 #define PELEV2B_REG PFRC2B
00547 #define PISEL2B_REG PFRC2B
00548 #define PCAE2B_REG PFRC2B
00549
00550
00551 #define PRFM2A0_REG PFRC2A
00552 #define PRFM2A1_REG PFRC2A
00553 #define PRFM2A2_REG PFRC2A
00554 #define PRFM2A3_REG PFRC2A
00555 #define PFLTE2A_REG PFRC2A
00556 #define PELEV2A_REG PFRC2A
00557 #define PISEL2A_REG PFRC2A
00558 #define PCAE2A_REG PFRC2A
00559
00560
00561 #define OCR2SA_0_REG OCR2SAL
00562 #define OCR2SA_1_REG OCR2SAL
00563 #define OCR2SA_2_REG OCR2SAL
00564 #define OCR2SA_3_REG OCR2SAL
00565 #define OCR2SA_4_REG OCR2SAL
00566 #define OCR2SA_5_REG OCR2SAL
00567 #define OCR2SA_6_REG OCR2SAL
00568 #define OCR2SA_7_REG OCR2SAL
00569
00570
00571 #define URxS0_REG EUCSRA
00572 #define URxS1_REG EUCSRA
00573 #define URxS2_REG EUCSRA
00574 #define URxS3_REG EUCSRA
00575 #define UTxS0_REG EUCSRA
00576 #define UTxS1_REG EUCSRA
00577 #define UTxS2_REG EUCSRA
00578 #define UTxS3_REG EUCSRA
00579
00580
00581 #define BODR_REG EUCSRB
00582 #define EMCH_REG EUCSRB
00583 #define EUSBS_REG EUCSRB
00584 #define EUSART_REG EUCSRB
00585
00586
00587 #define STP0_REG EUCSRC
00588 #define STP1_REG EUCSRC
00589 #define F1617_REG EUCSRC
00590 #define FEM_REG EUCSRC
00591
00592
00593 #define PRUN0_REG PCTL0
00594 #define PCCYC0_REG PCTL0
00595 #define PARUN0_REG PCTL0
00596 #define PAOC0A_REG PCTL0
00597 #define PAOC0B_REG PCTL0
00598 #define PBFM0_REG PCTL0
00599 #define PPRE00_REG PCTL0
00600 #define PPRE01_REG PCTL0
00601
00602
00603 #define PRUN2_REG PCTL2
00604 #define PCCYC2_REG PCTL2
00605 #define PARUN2_REG PCTL2
00606 #define PAOC2A_REG PCTL2
00607 #define PAOC2B_REG PCTL2
00608 #define PBFM2_REG PCTL2
00609 #define PPRE20_REG PCTL2
00610 #define PPRE21_REG PCTL2
00611
00612
00613 #define SPR0_REG SPCR
00614 #define SPR1_REG SPCR
00615 #define CPHA_REG SPCR
00616 #define CPOL_REG SPCR
00617 #define MSTR_REG SPCR
00618 #define DORD_REG SPCR
00619 #define SPE_REG SPCR
00620 #define SPIE_REG SPCR
00621
00622
00623 #define TOV1_REG TIFR1
00624 #define OCF1A_REG TIFR1
00625 #define OCF1B_REG TIFR1
00626 #define ICF1_REG TIFR1
00627
00628
00629 #define PSR10_REG GTCCR
00630 #define ICPSEL1_REG GTCCR
00631 #define TSM_REG GTCCR
00632 #define PSRSYNC_REG GTCCR
00633
00634
00635 #define ICR1H0_REG ICR1H
00636 #define ICR1H1_REG ICR1H
00637 #define ICR1H2_REG ICR1H
00638 #define ICR1H3_REG ICR1H
00639 #define ICR1H4_REG ICR1H
00640 #define ICR1H5_REG ICR1H
00641 #define ICR1H6_REG ICR1H
00642 #define ICR1H7_REG ICR1H
00643
00644
00645 #define POMV2A0_REG POM2
00646 #define POMV2A1_REG POM2
00647 #define POMV2A2_REG POM2
00648 #define POMV2A3_REG POM2
00649 #define POMV2B0_REG POM2
00650 #define POMV2B1_REG POM2
00651 #define POMV2B2_REG POM2
00652 #define POMV2B3_REG POM2
00653
00654
00655 #define OCR2RB_0_REG OCR2RBL
00656 #define OCR2RB_1_REG OCR2RBL
00657 #define OCR2RB_2_REG OCR2RBL
00658 #define OCR2RB_3_REG OCR2RBL
00659 #define OCR2RB_4_REG OCR2RBL
00660 #define OCR2RB_5_REG OCR2RBL
00661 #define OCR2RB_6_REG OCR2RBL
00662 #define OCR2RB_7_REG OCR2RBL
00663
00664
00665 #define PICR2_8_REG PICR2H
00666 #define PICR2_9_REG PICR2H
00667 #define PICR2_10_REG PICR2H
00668 #define PICR2_11_REG PICR2H
00669
00670
00671 #define OCR2RB_8_REG OCR2RBH
00672 #define OCR2RB_9_REG OCR2RBH
00673 #define OCR2RB_10_REG OCR2RBH
00674 #define OCR2RB_11_REG OCR2RBH
00675 #define OCR2RB_12_REG OCR2RBH
00676 #define OCR2RB_13_REG OCR2RBH
00677 #define OCR2RB_14_REG OCR2RBH
00678 #define OCR2RB_15_REG OCR2RBH
00679
00680
00681 #define PICR2_0_REG PICR2L
00682 #define PICR2_1_REG PICR2L
00683 #define PICR2_2_REG PICR2L
00684 #define PICR2_3_REG PICR2L
00685 #define PICR2_4_REG PICR2L
00686 #define PICR2_5_REG PICR2L
00687 #define PICR2_6_REG PICR2L
00688 #define PICR2_7_REG PICR2L
00689
00690
00691 #define OCR1BL0_REG OCR1BL
00692 #define OCR1BL1_REG OCR1BL
00693 #define OCR1BL2_REG OCR1BL
00694 #define OCR1BL3_REG OCR1BL
00695 #define OCR1BL4_REG OCR1BL
00696 #define OCR1BL5_REG OCR1BL
00697 #define OCR1BL6_REG OCR1BL
00698 #define OCR1BL7_REG OCR1BL
00699
00700
00701 #define OCR1BH0_REG OCR1BH
00702 #define OCR1BH1_REG OCR1BH
00703 #define OCR1BH2_REG OCR1BH
00704 #define OCR1BH3_REG OCR1BH
00705 #define OCR1BH4_REG OCR1BH
00706 #define OCR1BH5_REG OCR1BH
00707 #define OCR1BH6_REG OCR1BH
00708 #define OCR1BH7_REG OCR1BH
00709
00710
00711 #define ICR1L0_REG ICR1L
00712 #define ICR1L1_REG ICR1L
00713 #define ICR1L2_REG ICR1L
00714 #define ICR1L3_REG ICR1L
00715 #define ICR1L4_REG ICR1L
00716 #define ICR1L5_REG ICR1L
00717 #define ICR1L6_REG ICR1L
00718 #define ICR1L7_REG ICR1L
00719
00720
00721 #define PORF_REG MCUSR
00722 #define EXTRF_REG MCUSR
00723 #define BORF_REG MCUSR
00724 #define WDRF_REG MCUSR
00725
00726
00727 #define EERE_REG EECR
00728 #define EEWE_REG EECR
00729 #define EEMWE_REG EECR
00730 #define EERIE_REG EECR
00731
00732
00733 #define SE_REG SMCR
00734 #define SM0_REG SMCR
00735 #define SM1_REG SMCR
00736 #define SM2_REG SMCR
00737
00738
00739 #define PLOCK_REG PLLCSR
00740 #define PLLE_REG PLLCSR
00741 #define PLLF_REG PLLCSR
00742
00743
00744 #define OCR2RA_8_REG OCR2RAH
00745 #define OCR2RA_9_REG OCR2RAH
00746 #define OCR2RA_10_REG OCR2RAH
00747 #define OCR2RA_11_REG OCR2RAH
00748
00749
00750 #define OCR2RA_0_REG OCR2RAL
00751 #define OCR2RA_1_REG OCR2RAL
00752 #define OCR2RA_2_REG OCR2RAL
00753 #define OCR2RA_3_REG OCR2RAL
00754 #define OCR2RA_4_REG OCR2RAL
00755 #define OCR2RA_5_REG OCR2RAL
00756 #define OCR2RA_6_REG OCR2RAL
00757 #define OCR2RA_7_REG OCR2RAL
00758
00759
00760 #define OCR0RB_0_REG OCR0RBL
00761 #define OCR0RB_1_REG OCR0RBL
00762 #define OCR0RB_2_REG OCR0RBL
00763 #define OCR0RB_3_REG OCR0RBL
00764 #define OCR0RB_4_REG OCR0RBL
00765 #define OCR0RB_5_REG OCR0RBL
00766 #define OCR0RB_6_REG OCR0RBL
00767 #define OCR0RB_7_REG OCR0RBL
00768
00769
00770 #define OCR0SA_8_REG OCR0SAH
00771 #define OCR0SA_9_REG OCR0SAH
00772 #define OCR0SA_00_REG OCR0SAH
00773 #define OCR0SA_01_REG OCR0SAH
00774
00775
00776 #define EEAR8_REG EEARH
00777 #define EEAR9_REG EEARH
00778 #define EEAR10_REG EEARH
00779 #define EEAR11_REG EEARH
00780
00781
00782 #define EEARL0_REG EEARL
00783 #define EEARL1_REG EEARL
00784 #define EEARL2_REG EEARL
00785 #define EEARL3_REG EEARL
00786 #define EEARL4_REG EEARL
00787 #define EEARL5_REG EEARL
00788 #define EEARL6_REG EEARL
00789 #define EEARL7_REG EEARL
00790
00791
00792 #define IVCE_REG MCUCR
00793 #define IVSEL_REG MCUCR
00794 #define PUD_REG MCUCR
00795 #define SPIPS_REG MCUCR
00796
00797
00798 #define PICR0_8_REG PICR0H
00799 #define PICR0_9_REG PICR0H
00800 #define PICR0_10_REG PICR0H
00801 #define PICR0_11_REG PICR0H
00802
00803
00804 #define INTF0_REG EIFR
00805 #define INTF1_REG EIFR
00806 #define INTF2_REG EIFR
00807
00808
00809 #define MUBRR0_REG MUBRRL
00810 #define MUBRR1_REG MUBRRL
00811 #define MUBRR2_REG MUBRRL
00812 #define MUBRR3_REG MUBRRL
00813 #define MUBRR4_REG MUBRRL
00814 #define MUBRR5_REG MUBRRL
00815 #define MUBRR6_REG MUBRRL
00816 #define MUBRR7_REG MUBRRL
00817
00818
00819 #define MUBRR8_REG MUBRRH
00820 #define MUBRR9_REG MUBRRH
00821 #define MUBRR10_REG MUBRRH
00822 #define MUBRR11_REG MUBRRH
00823 #define MUBRR12_REG MUBRRH
00824 #define MUBRR13_REG MUBRRH
00825 #define MUBRR14_REG MUBRRH
00826 #define MUBRR15_REG MUBRRH
00827
00828
00829 #define OCR2SA_8_REG OCR2SAH
00830 #define OCR2SA_9_REG OCR2SAH
00831 #define OCR2SA_10_REG OCR2SAH
00832 #define OCR2SA_11_REG OCR2SAH
00833
00834
00835 #define OCR0SB_0_REG OCR0SBL
00836 #define OCR0SB_1_REG OCR0SBL
00837 #define OCR0SB_2_REG OCR0SBL
00838 #define OCR0SB_3_REG OCR0SBL
00839 #define OCR0SB_4_REG OCR0SBL
00840 #define OCR0SB_5_REG OCR0SBL
00841 #define OCR0SB_6_REG OCR0SBL
00842 #define OCR0SB_7_REG OCR0SBL
00843
00844
00845 #define OCR0SB_8_REG OCR0SBH
00846 #define OCR0SB_9_REG OCR0SBH
00847 #define OCR0SB_00_REG OCR0SBH
00848 #define OCR0SB_01_REG OCR0SBH
00849
00850
00851 #define PICR0_0_REG PICR0L
00852 #define PICR0_1_REG PICR0L
00853 #define PICR0_2_REG PICR0L
00854 #define PICR0_3_REG PICR0L
00855 #define PICR0_4_REG PICR0L
00856 #define PICR0_5_REG PICR0L
00857 #define PICR0_6_REG PICR0L
00858 #define PICR0_7_REG PICR0L
00859
00860
00861 #define ADPS0_REG ADCSRA
00862 #define ADPS1_REG ADCSRA
00863 #define ADPS2_REG ADCSRA
00864 #define ADIE_REG ADCSRA
00865 #define ADIF_REG ADCSRA
00866 #define ADATE_REG ADCSRA
00867 #define ADSC_REG ADCSRA
00868 #define ADEN_REG ADCSRA
00869
00870
00871 #define POEN0A_REG PSOC0
00872 #define POEN0B_REG PSOC0
00873 #define PSYNC00_REG PSOC0
00874 #define PSYNC01_REG PSOC0
00875
00876
00877 #define ADTS0_REG ADCSRB
00878 #define ADTS1_REG ADCSRB
00879 #define ADTS2_REG ADCSRB
00880 #define ADTS3_REG ADCSRB
00881 #define ADASCR_REG ADCSRB
00882 #define ADHSM_REG ADCSRB
00883
00884
00885
00886
00887
00888
00889
00890
00891
00892
00893
00894
00895 #define AC0O_REG ACSR
00896 #define AC1O_REG ACSR
00897 #define AC2O_REG ACSR
00898 #define AC0IF_REG ACSR
00899 #define AC1IF_REG ACSR
00900 #define AC2IF_REG ACSR
00901 #define ACCKDIV_REG ACSR
00902
00903
00904 #define DDD0_REG DDRD
00905 #define DDD1_REG DDRD
00906 #define DDD2_REG DDRD
00907 #define DDD3_REG DDRD
00908 #define DDD4_REG DDRD
00909 #define DDD5_REG DDRD
00910 #define DDD6_REG DDRD
00911 #define DDD7_REG DDRD
00912
00913
00914 #define UBRR8_REG UBRRH
00915 #define UBRR9_REG UBRRH
00916 #define UBRR10_REG UBRRH
00917 #define UBRR11_REG UBRRH
00918
00919
00920 #define DACL0_REG DACL
00921 #define DACL1_REG DACL
00922 #define DACL2_REG DACL
00923 #define DACL3_REG DACL
00924 #define DACL4_REG DACL
00925 #define DACL5_REG DACL
00926 #define DACL6_REG DACL
00927 #define DACL7_REG DACL
00928
00929
00930 #define UBRR0_REG UBRRL
00931 #define UBRR1_REG UBRRL
00932 #define UBRR2_REG UBRRL
00933 #define UBRR3_REG UBRRL
00934 #define UBRR4_REG UBRRL
00935 #define UBRR5_REG UBRRL
00936 #define UBRR6_REG UBRRL
00937 #define UBRR7_REG UBRRL
00938
00939
00940 #define DACH0_REG DACH
00941 #define DACH1_REG DACH
00942 #define DACH2_REG DACH
00943 #define DACH3_REG DACH
00944 #define DACH4_REG DACH
00945 #define DACH5_REG DACH
00946 #define DACH6_REG DACH
00947 #define DACH7_REG DACH
00948
00949
00950 #define OCR0RA_8_REG OCR0RAH
00951 #define OCR0RA_9_REG OCR0RAH
00952 #define OCR0RA_00_REG OCR0RAH
00953 #define OCR0RA_01_REG OCR0RAH
00954
00955
00956 #define SPMEN_REG SPMCSR
00957 #define PGERS_REG SPMCSR
00958 #define PGWRT_REG SPMCSR
00959 #define BLBSET_REG SPMCSR
00960 #define RWWSRE_REG SPMCSR
00961 #define RWWSB_REG SPMCSR
00962 #define SPMIE_REG SPMCSR
00963
00964
00965 #define PEOPE0_REG PIM0
00966 #define PEVE0A_REG PIM0
00967 #define PEVE0B_REG PIM0
00968 #define PSEIE0_REG PIM0
00969
00970
00971 #define PEOP2_REG PIFR2
00972 #define PRN20_REG PIFR2
00973 #define PRN21_REG PIFR2
00974 #define PEV2A_REG PIFR2
00975 #define PEV2B_REG PIFR2
00976 #define PSEI2_REG PIFR2
00977
00978
00979 #define PORTB0_REG PORTB
00980 #define PORTB1_REG PORTB
00981 #define PORTB2_REG PORTB
00982 #define PORTB3_REG PORTB
00983 #define PORTB4_REG PORTB
00984 #define PORTB5_REG PORTB
00985 #define PORTB6_REG PORTB
00986 #define PORTB7_REG PORTB
00987
00988
00989 #define ADCL0_REG ADCL
00990 #define ADCL1_REG ADCL
00991 #define ADCL2_REG ADCL
00992 #define ADCL3_REG ADCL
00993 #define ADCL4_REG ADCL
00994 #define ADCL5_REG ADCL
00995 #define ADCL6_REG ADCL
00996 #define ADCL7_REG ADCL
00997
00998
00999 #define ADCH0_REG ADCH
01000 #define ADCH1_REG ADCH
01001 #define ADCH2_REG ADCH
01002 #define ADCH3_REG ADCH
01003 #define ADCH4_REG ADCH
01004 #define ADCH5_REG ADCH
01005 #define ADCH6_REG ADCH
01006 #define ADCH7_REG ADCH
01007
01008
01009 #define POEN2A_REG PSOC2
01010 #define POEN2C_REG PSOC2
01011 #define POEN2B_REG PSOC2
01012 #define POEN2D_REG PSOC2
01013 #define PSYNC2_0_REG PSOC2
01014 #define PSYNC2_1_REG PSOC2
01015 #define POS22_REG PSOC2
01016 #define POS23_REG PSOC2
01017
01018
01019 #define TOIE0_REG TIMSK0
01020 #define OCIE0A_REG TIMSK0
01021 #define OCIE0B_REG TIMSK0
01022
01023
01024 #define TOIE1_REG TIMSK1
01025 #define OCIE1A_REG TIMSK1
01026 #define OCIE1B_REG TIMSK1
01027 #define ICIE1_REG TIMSK1
01028
01029
01030 #define AMP0TS0_REG AMP0CSR
01031 #define AMP0TS1_REG AMP0CSR
01032 #define AMP0G0_REG AMP0CSR
01033 #define AMP0G1_REG AMP0CSR
01034 #define AMP0IS_REG AMP0CSR
01035 #define AMP0EN_REG AMP0CSR
01036
01037
01038 #define UDR0_REG UDR
01039 #define UDR1_REG UDR
01040 #define UDR2_REG UDR
01041 #define UDR3_REG UDR
01042 #define UDR4_REG UDR
01043 #define UDR5_REG UDR
01044 #define UDR6_REG UDR
01045 #define UDR7_REG UDR
01046
01047
01048 #define DAEN_REG DACON
01049 #define DALA_REG DACON
01050 #define DATS0_REG DACON
01051 #define DATS1_REG DACON
01052 #define DATS2_REG DACON
01053 #define DAATE_REG DACON
01054
01055
01056 #define PINB0_REG PINB
01057 #define PINB1_REG PINB
01058 #define PINB2_REG PINB
01059 #define PINB3_REG PINB
01060 #define PINB4_REG PINB
01061 #define PINB5_REG PINB
01062 #define PINB6_REG PINB
01063 #define PINB7_REG PINB
01064
01065
01066 #define AC0M0_REG AC0CON
01067 #define AC0M1_REG AC0CON
01068 #define AC0M2_REG AC0CON
01069 #define AC0IS0_REG AC0CON
01070 #define AC0IS1_REG AC0CON
01071 #define AC0IE_REG AC0CON
01072 #define AC0EN_REG AC0CON
01073
01074
01075 #define PINE0_REG PINE
01076 #define PINE1_REG PINE
01077 #define PINE2_REG PINE
01078
01079
01080 #define PIND0_REG PIND
01081 #define PIND1_REG PIND
01082 #define PIND2_REG PIND
01083 #define PIND3_REG PIND
01084 #define PIND4_REG PIND
01085 #define PIND5_REG PIND
01086 #define PIND6_REG PIND
01087 #define PIND7_REG PIND
01088
01089
01090 #define OCR1AH0_REG OCR1AH
01091 #define OCR1AH1_REG OCR1AH
01092 #define OCR1AH2_REG OCR1AH
01093 #define OCR1AH3_REG OCR1AH
01094 #define OCR1AH4_REG OCR1AH
01095 #define OCR1AH5_REG OCR1AH
01096 #define OCR1AH6_REG OCR1AH
01097 #define OCR1AH7_REG OCR1AH
01098
01099
01100 #define OCR1AL0_REG OCR1AL
01101 #define OCR1AL1_REG OCR1AL
01102 #define OCR1AL2_REG OCR1AL
01103 #define OCR1AL3_REG OCR1AL
01104 #define OCR1AL4_REG OCR1AL
01105 #define OCR1AL5_REG OCR1AL
01106 #define OCR1AL6_REG OCR1AL
01107 #define OCR1AL7_REG OCR1AL
01108
01109
01110 #define TOV0_REG TIFR0
01111 #define OCF0A_REG TIFR0
01112 #define OCF0B_REG TIFR0
01113
01114
01115 #define MISO_PORT PORTB
01116 #define MISO_BIT 0
01117 #define PSCOUT20_PORT PORTB
01118 #define PSCOUT20_BIT 0
01119
01120 #define MOSI_PORT PORTB
01121 #define MOSI_BIT 1
01122 #define PSCOUT21_PORT PORTB
01123 #define PSCOUT21_BIT 1
01124
01125 #define ADC5_PORT PORTB
01126 #define ADC5_BIT 2
01127 #define INT1_PORT PORTB
01128 #define INT1_BIT 2
01129
01130 #define AMP0-_PORT PORTB
01131 #define AMP0-_BIT 3
01132
01133 #define AMP0+_PORT PORTB
01134 #define AMP0+_BIT 4
01135
01136 #define ADC6_PORT PORTB
01137 #define ADC6_BIT 5
01138 #define INT2_PORT PORTB
01139 #define INT2_BIT 5
01140
01141 #define ADC7_PORT PORTB
01142 #define ADC7_BIT 6
01143 #define PSCOUT11_PORT PORTB
01144 #define PSCOUT11_BIT 6
01145 #define ICP1B_PORT PORTB
01146 #define ICP1B_BIT 6
01147
01148 #define ADC4_PORT PORTB
01149 #define ADC4_BIT 7
01150 #define PSCOUT01_PORT PORTB
01151 #define PSCOUT01_BIT 7
01152 #define SCK_PORT PORTB
01153 #define SCK_BIT 7
01154
01155 #define PSCOUT00_PORT PORTD
01156 #define PSCOUT00_BIT 0
01157 #define XCK_PORT PORTD
01158 #define XCK_BIT 0
01159 #define SSA_PORT PORTD
01160 #define SSA_BIT 0
01161
01162 #define PSCIN0_PORT PORTD
01163 #define PSCIN0_BIT 1
01164 #define CLK0_PORT PORTD
01165 #define CLK0_BIT 1
01166
01167 #define PSCIN2_PORT PORTD
01168 #define PSCIN2_BIT 2
01169 #define OC1A_PORT PORTD
01170 #define OC1A_BIT 2
01171 #define MISO_A_PORT PORTD
01172 #define MISO_A_BIT 2
01173
01174 #define TXD_PORT PORTD
01175 #define TXD_BIT 3
01176 #define DALI_PORT PORTD
01177 #define DALI_BIT 3
01178 #define OC0A_PORT PORTD
01179 #define OC0A_BIT 3
01180 #define SS_PORT PORTD
01181 #define SS_BIT 3
01182 #define MOSI_A_PORT PORTD
01183 #define MOSI_A_BIT 3
01184
01185 #define ADC1_PORT PORTD
01186 #define ADC1_BIT 4
01187 #define RXD_PORT PORTD
01188 #define RXD_BIT 4
01189 #define DALI_PORT PORTD
01190 #define DALI_BIT 4
01191 #define ICP1_PORT PORTD
01192 #define ICP1_BIT 4
01193 #define SCK_A_PORT PORTD
01194 #define SCK_A_BIT 4
01195
01196 #define ADC2_PORT PORTD
01197 #define ADC2_BIT 5
01198 #define ACMP2_PORT PORTD
01199 #define ACMP2_BIT 5
01200
01201 #define ADC3_PORT PORTD
01202 #define ADC3_BIT 6
01203 #define ACMPM_PORT PORTD
01204 #define ACMPM_BIT 6
01205 #define INT0_PORT PORTD
01206 #define INT0_BIT 6
01207
01208 #define ACMP0_PORT PORTD
01209 #define ACMP0_BIT 7
01210
01211 #define RESET_PORT PORTE
01212 #define RESET_BIT 0
01213 #define OCD_PORT PORTE
01214 #define OCD_BIT 0
01215
01216 #define OC0B_PORT PORTE
01217 #define OC0B_BIT 1
01218 #define XTAL1_PORT PORTE
01219 #define XTAL1_BIT 1
01220
01221 #define ADC0_PORT PORTE
01222 #define ADC0_BIT 2
01223 #define XTAL2_PORT PORTE
01224 #define XTAL2_BIT 2
01225
01226