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00027
00028 #define TIMER0_PRESCALER_DIV_0 0
00029 #define TIMER0_PRESCALER_DIV_1 1
00030 #define TIMER0_PRESCALER_DIV_8 2
00031 #define TIMER0_PRESCALER_DIV_64 3
00032 #define TIMER0_PRESCALER_DIV_256 4
00033 #define TIMER0_PRESCALER_DIV_1024 5
00034 #define TIMER0_PRESCALER_DIV_FALL 6
00035 #define TIMER0_PRESCALER_DIV_RISE 7
00036
00037 #define TIMER0_PRESCALER_REG_0 0
00038 #define TIMER0_PRESCALER_REG_1 1
00039 #define TIMER0_PRESCALER_REG_2 8
00040 #define TIMER0_PRESCALER_REG_3 64
00041 #define TIMER0_PRESCALER_REG_4 256
00042 #define TIMER0_PRESCALER_REG_5 1024
00043 #define TIMER0_PRESCALER_REG_6 -1
00044 #define TIMER0_PRESCALER_REG_7 -2
00045
00046
00047 #define TIMER1_PRESCALER_DIV_0 0
00048 #define TIMER1_PRESCALER_DIV_1 1
00049 #define TIMER1_PRESCALER_DIV_8 2
00050 #define TIMER1_PRESCALER_DIV_64 3
00051 #define TIMER1_PRESCALER_DIV_256 4
00052 #define TIMER1_PRESCALER_DIV_1024 5
00053 #define TIMER1_PRESCALER_DIV_FALL 6
00054 #define TIMER1_PRESCALER_DIV_RISE 7
00055
00056 #define TIMER1_PRESCALER_REG_0 0
00057 #define TIMER1_PRESCALER_REG_1 1
00058 #define TIMER1_PRESCALER_REG_2 8
00059 #define TIMER1_PRESCALER_REG_3 64
00060 #define TIMER1_PRESCALER_REG_4 256
00061 #define TIMER1_PRESCALER_REG_5 1024
00062 #define TIMER1_PRESCALER_REG_6 -1
00063 #define TIMER1_PRESCALER_REG_7 -2
00064
00065
00066 #define TIMER2_PRESCALER_DIV_0 0
00067 #define TIMER2_PRESCALER_DIV_1 1
00068 #define TIMER2_PRESCALER_DIV_8 2
00069 #define TIMER2_PRESCALER_DIV_32 3
00070 #define TIMER2_PRESCALER_DIV_64 4
00071 #define TIMER2_PRESCALER_DIV_128 5
00072 #define TIMER2_PRESCALER_DIV_256 6
00073 #define TIMER2_PRESCALER_DIV_1024 7
00074
00075 #define TIMER2_PRESCALER_REG_0 0
00076 #define TIMER2_PRESCALER_REG_1 1
00077 #define TIMER2_PRESCALER_REG_2 8
00078 #define TIMER2_PRESCALER_REG_3 32
00079 #define TIMER2_PRESCALER_REG_4 64
00080 #define TIMER2_PRESCALER_REG_5 128
00081 #define TIMER2_PRESCALER_REG_6 256
00082 #define TIMER2_PRESCALER_REG_7 1024
00083
00084
00085 #define TIMER3_PRESCALER_DIV_0 0
00086 #define TIMER3_PRESCALER_DIV_1 1
00087 #define TIMER3_PRESCALER_DIV_8 2
00088 #define TIMER3_PRESCALER_DIV_64 3
00089 #define TIMER3_PRESCALER_DIV_256 4
00090 #define TIMER3_PRESCALER_DIV_1024 5
00091 #define TIMER3_PRESCALER_DIV_FALL 6
00092 #define TIMER3_PRESCALER_DIV_RISE 7
00093
00094 #define TIMER3_PRESCALER_REG_0 0
00095 #define TIMER3_PRESCALER_REG_1 1
00096 #define TIMER3_PRESCALER_REG_2 8
00097 #define TIMER3_PRESCALER_REG_3 64
00098 #define TIMER3_PRESCALER_REG_4 256
00099 #define TIMER3_PRESCALER_REG_5 1024
00100 #define TIMER3_PRESCALER_REG_6 -1
00101 #define TIMER3_PRESCALER_REG_7 -2
00102
00103
00104
00105 #define TIMER0_AVAILABLE
00106 #define TIMER1_AVAILABLE
00107 #define TIMER1A_AVAILABLE
00108 #define TIMER1B_AVAILABLE
00109 #define TIMER1C_AVAILABLE
00110 #define TIMER2_AVAILABLE
00111 #define TIMER3_AVAILABLE
00112 #define TIMER3A_AVAILABLE
00113 #define TIMER3B_AVAILABLE
00114 #define TIMER3C_AVAILABLE
00115
00116
00117 #define SIG_OVERFLOW0_NUM 0
00118 #define SIG_OVERFLOW1_NUM 1
00119 #define SIG_OVERFLOW2_NUM 2
00120 #define SIG_OVERFLOW3_NUM 3
00121 #define SIG_OVERFLOW_TOTAL_NUM 4
00122
00123
00124 #define SIG_OUTPUT_COMPARE0_NUM 0
00125 #define SIG_OUTPUT_COMPARE1A_NUM 1
00126 #define SIG_OUTPUT_COMPARE1B_NUM 2
00127 #define SIG_OUTPUT_COMPARE1C_NUM 3
00128 #define SIG_OUTPUT_COMPARE2_NUM 4
00129 #define SIG_OUTPUT_COMPARE3A_NUM 5
00130 #define SIG_OUTPUT_COMPARE3B_NUM 6
00131 #define SIG_OUTPUT_COMPARE3C_NUM 7
00132 #define SIG_OUTPUT_COMPARE_TOTAL_NUM 8
00133
00134
00135 #define PWM0_NUM 0
00136 #define PWM1A_NUM 1
00137 #define PWM1B_NUM 2
00138 #define PWM1C_NUM 3
00139 #define PWM2_NUM 4
00140 #define PWM3A_NUM 5
00141 #define PWM3B_NUM 6
00142 #define PWM3C_NUM 7
00143 #define PWM_TOTAL_NUM 8
00144
00145
00146 #define SIG_INPUT_CAPTURE1_NUM 0
00147 #define SIG_INPUT_CAPTURE3_NUM 1
00148 #define SIG_INPUT_CAPTURE_TOTAL_NUM 2
00149
00150
00151
00152 #define WDP0_REG WDTCR
00153 #define WDP1_REG WDTCR
00154 #define WDP2_REG WDTCR
00155 #define WDE_REG WDTCR
00156 #define WDCE_REG WDTCR
00157
00158
00159 #define MUX0_REG ADMUX
00160 #define MUX1_REG ADMUX
00161 #define MUX2_REG ADMUX
00162 #define MUX3_REG ADMUX
00163 #define MUX4_REG ADMUX
00164 #define ADLAR_REG ADMUX
00165 #define REFS0_REG ADMUX
00166 #define REFS1_REG ADMUX
00167
00168
00169 #define EEDR0_REG EEDR
00170 #define EEDR1_REG EEDR
00171 #define EEDR2_REG EEDR
00172 #define EEDR3_REG EEDR
00173 #define EEDR4_REG EEDR
00174 #define EEDR5_REG EEDR
00175 #define EEDR6_REG EEDR
00176 #define EEDR7_REG EEDR
00177
00178
00179 #define RAMPZ0_REG RAMPZ
00180
00181
00182 #define OCR2A0_REG OCR2A
00183 #define OCR2A1_REG OCR2A
00184 #define OCR2A2_REG OCR2A
00185 #define OCR2A3_REG OCR2A
00186 #define OCR2A4_REG OCR2A
00187 #define OCR2A5_REG OCR2A
00188 #define OCR2A6_REG OCR2A
00189 #define OCR2A7_REG OCR2A
00190
00191
00192 #define SPDR0_REG SPDR
00193 #define SPDR1_REG SPDR
00194 #define SPDR2_REG SPDR
00195 #define SPDR3_REG SPDR
00196 #define SPDR4_REG SPDR
00197 #define SPDR5_REG SPDR
00198 #define SPDR6_REG SPDR
00199 #define SPDR7_REG SPDR
00200
00201
00202 #define SPI2X_REG SPSR
00203 #define WCOL_REG SPSR
00204 #define SPIF_REG SPSR
00205
00206
00207 #define ICR1H0_REG ICR1H
00208 #define ICR1H1_REG ICR1H
00209 #define ICR1H2_REG ICR1H
00210 #define ICR1H3_REG ICR1H
00211 #define ICR1H4_REG ICR1H
00212 #define ICR1H5_REG ICR1H
00213 #define ICR1H6_REG ICR1H
00214 #define ICR1H7_REG ICR1H
00215
00216
00217 #define ICR1L0_REG ICR1L
00218 #define ICR1L1_REG ICR1L
00219 #define ICR1L2_REG ICR1L
00220 #define ICR1L3_REG ICR1L
00221 #define ICR1L4_REG ICR1L
00222 #define ICR1L5_REG ICR1L
00223 #define ICR1L6_REG ICR1L
00224 #define ICR1L7_REG ICR1L
00225
00226
00227 #define EEAR8_REG EEARH
00228 #define EEAR9_REG EEARH
00229 #define EEAR10_REG EEARH
00230 #define EEAR11_REG EEARH
00231
00232
00233 #define ERRP_REG CANGSTA
00234 #define BOFF_REG CANGSTA
00235 #define ENFG_REG CANGSTA
00236 #define RXBSY_REG CANGSTA
00237 #define TXBSY_REG CANGSTA
00238 #define OVRG_REG CANGSTA
00239
00240
00241 #define SWRES_REG CANGCON
00242 #define ENASTB_REG CANGCON
00243 #define TEST_REG CANGCON
00244 #define LISTEN_REG CANGCON
00245 #define SYNTTC_REG CANGCON
00246 #define TTC_REG CANGCON
00247 #define OVRQ_REG CANGCON
00248 #define ABRQ_REG CANGCON
00249
00250
00251 #define PORTG0_REG PORTG
00252 #define PORTG1_REG PORTG
00253 #define PORTG2_REG PORTG
00254 #define PORTG3_REG PORTG
00255 #define PORTG4_REG PORTG
00256
00257
00258 #define UCPOL0_REG UCSR0C
00259 #define UCSZ00_REG UCSR0C
00260 #define UCSZ01_REG UCSR0C
00261 #define USBS0_REG UCSR0C
00262 #define UPM00_REG UCSR0C
00263 #define UPM01_REG UCSR0C
00264 #define UMSEL0_REG UCSR0C
00265
00266
00267 #define TXB80_REG UCSR0B
00268 #define RXB80_REG UCSR0B
00269 #define UCSZ02_REG UCSR0B
00270 #define TXEN0_REG UCSR0B
00271 #define RXEN0_REG UCSR0B
00272 #define UDRIE0_REG UCSR0B
00273 #define TXCIE0_REG UCSR0B
00274 #define RXCIE0_REG UCSR0B
00275
00276
00277 #define TCNT1H0_REG TCNT1H
00278 #define TCNT1H1_REG TCNT1H
00279 #define TCNT1H2_REG TCNT1H
00280 #define TCNT1H3_REG TCNT1H
00281 #define TCNT1H4_REG TCNT1H
00282 #define TCNT1H5_REG TCNT1H
00283 #define TCNT1H6_REG TCNT1H
00284 #define TCNT1H7_REG TCNT1H
00285
00286
00287 #define PORTC0_REG PORTC
00288 #define PORTC1_REG PORTC
00289 #define PORTC2_REG PORTC
00290 #define PORTC3_REG PORTC
00291 #define PORTC4_REG PORTC
00292 #define PORTC5_REG PORTC
00293 #define PORTC6_REG PORTC
00294 #define PORTC7_REG PORTC
00295
00296
00297 #define PORTA0_REG PORTA
00298 #define PORTA1_REG PORTA
00299 #define PORTA2_REG PORTA
00300 #define PORTA3_REG PORTA
00301 #define PORTA4_REG PORTA
00302 #define PORTA5_REG PORTA
00303 #define PORTA6_REG PORTA
00304 #define PORTA7_REG PORTA
00305
00306
00307 #define EEARL0_REG EEARL
00308 #define EEARL1_REG EEARL
00309 #define EEARL2_REG EEARL
00310 #define EEARL3_REG EEARL
00311 #define EEARL4_REG EEARL
00312 #define EEARL5_REG EEARL
00313 #define EEARL6_REG EEARL
00314 #define EEARL7_REG EEARL
00315
00316
00317 #define INT0_REG EIMSK
00318 #define INT1_REG EIMSK
00319 #define INT2_REG EIMSK
00320 #define INT3_REG EIMSK
00321 #define INT4_REG EIMSK
00322 #define INT5_REG EIMSK
00323 #define INT6_REG EIMSK
00324 #define INT7_REG EIMSK
00325
00326
00327 #define UDR10_REG UDR1
00328 #define UDR11_REG UDR1
00329 #define UDR12_REG UDR1
00330 #define UDR13_REG UDR1
00331 #define UDR14_REG UDR1
00332 #define UDR15_REG UDR1
00333 #define UDR16_REG UDR1
00334 #define UDR17_REG UDR1
00335
00336
00337 #define UDR00_REG UDR0
00338 #define UDR01_REG UDR0
00339 #define UDR02_REG UDR0
00340 #define UDR03_REG UDR0
00341 #define UDR04_REG UDR0
00342 #define UDR05_REG UDR0
00343 #define UDR06_REG UDR0
00344 #define UDR07_REG UDR0
00345
00346
00347 #define GPIOR20_REG GPIOR2
00348 #define GPIOR21_REG GPIOR2
00349 #define GPIOR22_REG GPIOR2
00350 #define GPIOR23_REG GPIOR2
00351 #define GPIOR24_REG GPIOR2
00352 #define GPIOR25_REG GPIOR2
00353 #define GPIOR26_REG GPIOR2
00354 #define GPIOR27_REG GPIOR2
00355
00356
00357 #define ISC40_REG EICRB
00358 #define ISC41_REG EICRB
00359 #define ISC50_REG EICRB
00360 #define ISC51_REG EICRB
00361 #define ISC60_REG EICRB
00362 #define ISC61_REG EICRB
00363 #define ISC70_REG EICRB
00364 #define ISC71_REG EICRB
00365
00366
00367 #define ISC00_REG EICRA
00368 #define ISC01_REG EICRA
00369 #define ISC10_REG EICRA
00370 #define ISC11_REG EICRA
00371 #define ISC20_REG EICRA
00372 #define ISC21_REG EICRA
00373 #define ISC30_REG EICRA
00374 #define ISC31_REG EICRA
00375
00376
00377 #define ADC0D_REG DIDR0
00378 #define ADC1D_REG DIDR0
00379 #define ADC2D_REG DIDR0
00380 #define ADC3D_REG DIDR0
00381 #define ADC4D_REG DIDR0
00382 #define ADC5D_REG DIDR0
00383 #define ADC6D_REG DIDR0
00384 #define ADC7D_REG DIDR0
00385
00386
00387 #define AIN0D_REG DIDR1
00388 #define AIN1D_REG DIDR1
00389
00390
00391 #define DDF0_REG DDRF
00392 #define DDF1_REG DDRF
00393 #define DDF2_REG DDRF
00394 #define DDF3_REG DDRF
00395 #define DDF4_REG DDRF
00396 #define DDF5_REG DDRF
00397 #define DDF6_REG DDRF
00398 #define DDF7_REG DDRF
00399
00400
00401 #define TCR2UB_REG ASSR
00402 #define OCR2UB_REG ASSR
00403 #define TCN2UB_REG ASSR
00404 #define AS2_REG ASSR
00405 #define EXCLK_REG ASSR
00406
00407
00408 #define CLKPS0_REG CLKPR
00409 #define CLKPS1_REG CLKPR
00410 #define CLKPS2_REG CLKPR
00411 #define CLKPS3_REG CLKPR
00412 #define CLKPCE_REG CLKPR
00413
00414
00415 #define C_REG SREG
00416 #define Z_REG SREG
00417 #define N_REG SREG
00418 #define V_REG SREG
00419 #define S_REG SREG
00420 #define H_REG SREG
00421 #define T_REG SREG
00422 #define I_REG SREG
00423
00424
00425 #define IDMSK21_REG CANIDM1
00426 #define IDMSK22_REG CANIDM1
00427 #define IDMSK23_REG CANIDM1
00428 #define IDMSK24_REG CANIDM1
00429 #define IDMSK25_REG CANIDM1
00430 #define IDMSK26_REG CANIDM1
00431 #define IDMSK27_REG CANIDM1
00432 #define IDMSK28_REG CANIDM1
00433
00434
00435 #define IDMSK5_REG CANIDM3
00436 #define IDMSK6_REG CANIDM3
00437 #define IDMSK7_REG CANIDM3
00438 #define IDMSK8_REG CANIDM3
00439 #define IDMSK9_REG CANIDM3
00440 #define IDMSK10_REG CANIDM3
00441 #define IDMSK11_REG CANIDM3
00442 #define IDMSK12_REG CANIDM3
00443
00444
00445 #define IDMSK13_REG CANIDM2
00446 #define IDMSK14_REG CANIDM2
00447 #define IDMSK15_REG CANIDM2
00448 #define IDMSK16_REG CANIDM2
00449 #define IDMSK17_REG CANIDM2
00450 #define IDMSK18_REG CANIDM2
00451 #define IDMSK19_REG CANIDM2
00452 #define IDMSK20_REG CANIDM2
00453
00454
00455 #define IDEMSK_REG CANIDM4
00456 #define RTRMSK_REG CANIDM4
00457 #define IDMSK0_REG CANIDM4
00458 #define IDMSK1_REG CANIDM4
00459 #define IDMSK2_REG CANIDM4
00460 #define IDMSK3_REG CANIDM4
00461 #define IDMSK4_REG CANIDM4
00462
00463
00464
00465
00466
00467
00468
00469
00470
00471
00472
00473
00474 #define DDC0_REG DDRC
00475 #define DDC1_REG DDRC
00476 #define DDC2_REG DDRC
00477 #define DDC3_REG DDRC
00478 #define DDC4_REG DDRC
00479 #define DDC5_REG DDRC
00480 #define DDC6_REG DDRC
00481 #define DDC7_REG DDRC
00482
00483
00484 #define OCR3AL0_REG OCR3AL
00485 #define OCR3AL1_REG OCR3AL
00486 #define OCR3AL2_REG OCR3AL
00487 #define OCR3AL3_REG OCR3AL
00488 #define OCR3AL4_REG OCR3AL
00489 #define OCR3AL5_REG OCR3AL
00490 #define OCR3AL6_REG OCR3AL
00491 #define OCR3AL7_REG OCR3AL
00492
00493
00494 #define DDA0_REG DDRA
00495 #define DDA1_REG DDRA
00496 #define DDA2_REG DDRA
00497 #define DDA3_REG DDRA
00498 #define DDA4_REG DDRA
00499 #define DDA5_REG DDRA
00500 #define DDA6_REG DDRA
00501 #define DDA7_REG DDRA
00502
00503
00504
00505
00506
00507
00508
00509
00510 #define DDG0_REG DDRG
00511 #define DDG1_REG DDRG
00512 #define DDG2_REG DDRG
00513 #define DDG3_REG DDRG
00514 #define DDG4_REG DDRG
00515
00516
00517 #define OCR3AH0_REG OCR3AH
00518 #define OCR3AH1_REG OCR3AH
00519 #define OCR3AH2_REG OCR3AH
00520 #define OCR3AH3_REG OCR3AH
00521 #define OCR3AH4_REG OCR3AH
00522 #define OCR3AH5_REG OCR3AH
00523 #define OCR3AH6_REG OCR3AH
00524 #define OCR3AH7_REG OCR3AH
00525
00526
00527 #define CS10_REG TCCR1B
00528 #define CS11_REG TCCR1B
00529 #define CS12_REG TCCR1B
00530 #define WGM12_REG TCCR1B
00531 #define WGM13_REG TCCR1B
00532 #define ICES1_REG TCCR1B
00533 #define ICNC1_REG TCCR1B
00534
00535
00536 #define CAL0_REG OSCCAL
00537 #define CAL1_REG OSCCAL
00538 #define CAL2_REG OSCCAL
00539 #define CAL3_REG OSCCAL
00540 #define CAL4_REG OSCCAL
00541 #define CAL5_REG OSCCAL
00542 #define CAL6_REG OSCCAL
00543
00544
00545 #define DDD0_REG DDRD
00546 #define DDD1_REG DDRD
00547 #define DDD2_REG DDRD
00548 #define DDD3_REG DDRD
00549 #define DDD4_REG DDRD
00550 #define DDD5_REG DDRD
00551 #define DDD6_REG DDRD
00552 #define DDD7_REG DDRD
00553
00554
00555 #define GPIOR10_REG GPIOR1
00556 #define GPIOR11_REG GPIOR1
00557 #define GPIOR12_REG GPIOR1
00558 #define GPIOR13_REG GPIOR1
00559 #define GPIOR14_REG GPIOR1
00560 #define GPIOR15_REG GPIOR1
00561 #define GPIOR16_REG GPIOR1
00562 #define GPIOR17_REG GPIOR1
00563
00564
00565 #define GPIOR00_REG GPIOR0
00566 #define GPIOR01_REG GPIOR0
00567 #define GPIOR02_REG GPIOR0
00568 #define GPIOR03_REG GPIOR0
00569 #define GPIOR04_REG GPIOR0
00570 #define GPIOR05_REG GPIOR0
00571 #define GPIOR06_REG GPIOR0
00572 #define GPIOR07_REG GPIOR0
00573
00574
00575 #define TWBR0_REG TWBR
00576 #define TWBR1_REG TWBR
00577 #define TWBR2_REG TWBR
00578 #define TWBR3_REG TWBR
00579 #define TWBR4_REG TWBR
00580 #define TWBR5_REG TWBR
00581 #define TWBR6_REG TWBR
00582 #define TWBR7_REG TWBR
00583
00584
00585 #define AERG_REG CANGIT
00586 #define FERG_REG CANGIT
00587 #define CERG_REG CANGIT
00588 #define SERG_REG CANGIT
00589 #define BXOK_REG CANGIT
00590 #define OVRTIM_REG CANGIT
00591 #define BOFFIT_REG CANGIT
00592 #define CANIT_REG CANGIT
00593
00594
00595 #define TCNT2_0_REG TCNT2
00596 #define TCNT2_1_REG TCNT2
00597 #define TCNT2_2_REG TCNT2
00598 #define TCNT2_3_REG TCNT2
00599 #define TCNT2_4_REG TCNT2
00600 #define TCNT2_5_REG TCNT2
00601 #define TCNT2_6_REG TCNT2
00602 #define TCNT2_7_REG TCNT2
00603
00604
00605 #define ENOVRT_REG CANGIE
00606 #define ENERG_REG CANGIE
00607 #define ENBX_REG CANGIE
00608 #define ENERR_REG CANGIE
00609 #define ENTX_REG CANGIE
00610 #define ENRX_REG CANGIE
00611 #define ENBOFF_REG CANGIE
00612 #define ENIT_REG CANGIE
00613
00614
00615 #define TCNT0_0_REG TCNT0
00616 #define TCNT0_1_REG TCNT0
00617 #define TCNT0_2_REG TCNT0
00618 #define TCNT0_3_REG TCNT0
00619 #define TCNT0_4_REG TCNT0
00620 #define TCNT0_5_REG TCNT0
00621 #define TCNT0_6_REG TCNT0
00622 #define TCNT0_7_REG TCNT0
00623
00624
00625 #define TWGCE_REG TWAR
00626 #define TWA0_REG TWAR
00627 #define TWA1_REG TWAR
00628 #define TWA2_REG TWAR
00629 #define TWA3_REG TWAR
00630 #define TWA4_REG TWAR
00631 #define TWA5_REG TWAR
00632 #define TWA6_REG TWAR
00633
00634
00635 #define IEMOB0_REG CANIE2
00636 #define IEMOB1_REG CANIE2
00637 #define IEMOB2_REG CANIE2
00638 #define IEMOB3_REG CANIE2
00639 #define IEMOB4_REG CANIE2
00640 #define IEMOB5_REG CANIE2
00641 #define IEMOB6_REG CANIE2
00642 #define IEMOB7_REG CANIE2
00643
00644
00645 #define FOC3C_REG TCCR3C
00646 #define FOC3B_REG TCCR3C
00647 #define FOC3A_REG TCCR3C
00648
00649
00650 #define IEMOB8_REG CANIE1
00651 #define IEMOB9_REG CANIE1
00652 #define IEMOB10_REG CANIE1
00653 #define IEMOB11_REG CANIE1
00654 #define IEMOB12_REG CANIE1
00655 #define IEMOB13_REG CANIE1
00656 #define IEMOB14_REG CANIE1
00657
00658
00659 #define CS00_REG TCCR0A
00660 #define CS01_REG TCCR0A
00661 #define CS02_REG TCCR0A
00662 #define WGM01_REG TCCR0A
00663 #define COM0A0_REG TCCR0A
00664 #define COM0A1_REG TCCR0A
00665 #define WGM00_REG TCCR0A
00666 #define FOC0A_REG TCCR0A
00667
00668
00669 #define TOV2_REG TIFR2
00670 #define OCF2A_REG TIFR2
00671
00672
00673 #define TOV3_REG TIFR3
00674 #define OCF3A_REG TIFR3
00675 #define OCF3B_REG TIFR3
00676 #define OCF3C_REG TIFR3
00677 #define ICF3_REG TIFR3
00678
00679
00680 #define SPR0_REG SPCR
00681 #define SPR1_REG SPCR
00682 #define CPHA_REG SPCR
00683 #define CPOL_REG SPCR
00684 #define MSTR_REG SPCR
00685 #define DORD_REG SPCR
00686 #define SPE_REG SPCR
00687 #define SPIE_REG SPCR
00688
00689
00690 #define TOV1_REG TIFR1
00691 #define OCF1A_REG TIFR1
00692 #define OCF1B_REG TIFR1
00693 #define OCF1C_REG TIFR1
00694 #define ICF1_REG TIFR1
00695
00696
00697 #define RB0TAG_REG CANIDT4
00698 #define RB1TAG_REG CANIDT4
00699 #define RTRTAG_REG CANIDT4
00700 #define IDT0_REG CANIDT4
00701 #define IDT1_REG CANIDT4
00702 #define IDT2_REG CANIDT4
00703 #define IDT3_REG CANIDT4
00704 #define IDT4_REG CANIDT4
00705
00706
00707 #define IDT13_REG CANIDT2
00708 #define IDT14_REG CANIDT2
00709 #define IDT15_REG CANIDT2
00710 #define IDT16_REG CANIDT2
00711 #define IDT17_REG CANIDT2
00712 #define IDT18_REG CANIDT2
00713 #define IDT19_REG CANIDT2
00714 #define IDT20_REG CANIDT2
00715
00716
00717 #define IDT5_REG CANIDT3
00718 #define IDT6_REG CANIDT3
00719 #define IDT7_REG CANIDT3
00720 #define IDT8_REG CANIDT3
00721 #define IDT9_REG CANIDT3
00722 #define IDT10_REG CANIDT3
00723 #define IDT11_REG CANIDT3
00724 #define IDT12_REG CANIDT3
00725
00726
00727 #define IDT21_REG CANIDT1
00728 #define IDT22_REG CANIDT1
00729 #define IDT23_REG CANIDT1
00730 #define IDT24_REG CANIDT1
00731 #define IDT25_REG CANIDT1
00732 #define IDT26_REG CANIDT1
00733 #define IDT27_REG CANIDT1
00734 #define IDT28_REG CANIDT1
00735
00736
00737 #define SIT8_REG CANSIT1
00738 #define SIT9_REG CANSIT1
00739 #define SIT10_REG CANSIT1
00740 #define SIT11_REG CANSIT1
00741 #define SIT12_REG CANSIT1
00742 #define SIT13_REG CANSIT1
00743 #define SIT14_REG CANSIT1
00744
00745
00746 #define OCR3CH0_REG OCR3CH
00747 #define OCR3CH1_REG OCR3CH
00748 #define OCR3CH2_REG OCR3CH
00749 #define OCR3CH3_REG OCR3CH
00750 #define OCR3CH4_REG OCR3CH
00751 #define OCR3CH5_REG OCR3CH
00752 #define OCR3CH6_REG OCR3CH
00753 #define OCR3CH7_REG OCR3CH
00754
00755
00756 #define OCR3CL0_REG OCR3CL
00757 #define OCR3CL1_REG OCR3CL
00758 #define OCR3CL2_REG OCR3CL
00759 #define OCR3CL3_REG OCR3CL
00760 #define OCR3CL4_REG OCR3CL
00761 #define OCR3CL5_REG OCR3CL
00762 #define OCR3CL6_REG OCR3CL
00763 #define OCR3CL7_REG OCR3CL
00764
00765
00766 #define PSR310_REG GTCCR
00767 #define TSM_REG GTCCR
00768 #define PSR2_REG GTCCR
00769
00770
00771 #define DLC0_REG CANCDMOB
00772 #define DLC1_REG CANCDMOB
00773 #define DLC2_REG CANCDMOB
00774 #define DLC3_REG CANCDMOB
00775 #define IDE_REG CANCDMOB
00776 #define RPLV_REG CANCDMOB
00777 #define CONMOB0_REG CANCDMOB
00778 #define CONMOB1_REG CANCDMOB
00779
00780
00781 #define SP8_REG SPH
00782 #define SP9_REG SPH
00783 #define SP10_REG SPH
00784 #define SP11_REG SPH
00785 #define SP12_REG SPH
00786 #define SP13_REG SPH
00787 #define SP14_REG SPH
00788 #define SP15_REG SPH
00789
00790
00791 #define SIT0_REG CANSIT2
00792 #define SIT1_REG CANSIT2
00793 #define SIT2_REG CANSIT2
00794 #define SIT3_REG CANSIT2
00795 #define SIT4_REG CANSIT2
00796 #define SIT5_REG CANSIT2
00797 #define SIT6_REG CANSIT2
00798 #define SIT7_REG CANSIT2
00799
00800
00801 #define CGP0_REG CANHPMOB
00802 #define CGP1_REG CANHPMOB
00803 #define CGP2_REG CANHPMOB
00804 #define CGP3_REG CANHPMOB
00805 #define HPMOB0_REG CANHPMOB
00806 #define HPMOB1_REG CANHPMOB
00807 #define HPMOB2_REG CANHPMOB
00808 #define HPMOB3_REG CANHPMOB
00809
00810
00811 #define CS30_REG TCCR3B
00812 #define CS31_REG TCCR3B
00813 #define CS32_REG TCCR3B
00814 #define WGM32_REG TCCR3B
00815 #define WGM33_REG TCCR3B
00816 #define ICES3_REG TCCR3B
00817 #define ICNC3_REG TCCR3B
00818
00819
00820 #define WGM30_REG TCCR3A
00821 #define WGM31_REG TCCR3A
00822 #define COM3C0_REG TCCR3A
00823 #define COM3C1_REG TCCR3A
00824 #define COM3B0_REG TCCR3A
00825 #define COM3B1_REG TCCR3A
00826 #define COM3A0_REG TCCR3A
00827 #define COM3A1_REG TCCR3A
00828
00829
00830 #define PORTF0_REG PORTF
00831 #define PORTF1_REG PORTF
00832 #define PORTF2_REG PORTF
00833 #define PORTF3_REG PORTF
00834 #define PORTF4_REG PORTF
00835 #define PORTF5_REG PORTF
00836 #define PORTF6_REG PORTF
00837 #define PORTF7_REG PORTF
00838
00839
00840 #define OCR1BL0_REG OCR1BL
00841 #define OCR1BL1_REG OCR1BL
00842 #define OCR1BL2_REG OCR1BL
00843 #define OCR1BL3_REG OCR1BL
00844 #define OCR1BL4_REG OCR1BL
00845 #define OCR1BL5_REG OCR1BL
00846 #define OCR1BL6_REG OCR1BL
00847 #define OCR1BL7_REG OCR1BL
00848
00849
00850 #define TCNT3H0_REG TCNT3H
00851 #define TCNT3H1_REG TCNT3H
00852 #define TCNT3H2_REG TCNT3H
00853 #define TCNT3H3_REG TCNT3H
00854 #define TCNT3H4_REG TCNT3H
00855 #define TCNT3H5_REG TCNT3H
00856 #define TCNT3H6_REG TCNT3H
00857 #define TCNT3H7_REG TCNT3H
00858
00859
00860 #define OCR1BH0_REG OCR1BH
00861 #define OCR1BH1_REG OCR1BH
00862 #define OCR1BH2_REG OCR1BH
00863 #define OCR1BH3_REG OCR1BH
00864 #define OCR1BH4_REG OCR1BH
00865 #define OCR1BH5_REG OCR1BH
00866 #define OCR1BH6_REG OCR1BH
00867 #define OCR1BH7_REG OCR1BH
00868
00869
00870 #define TCNT3L0_REG TCNT3L
00871 #define TCNT3L1_REG TCNT3L
00872 #define TCNT3L2_REG TCNT3L
00873 #define TCNT3L3_REG TCNT3L
00874 #define TCNT3L4_REG TCNT3L
00875 #define TCNT3L5_REG TCNT3L
00876 #define TCNT3L6_REG TCNT3L
00877 #define TCNT3L7_REG TCNT3L
00878
00879
00880 #define SP0_REG SPL
00881 #define SP1_REG SPL
00882 #define SP2_REG SPL
00883 #define SP3_REG SPL
00884 #define SP4_REG SPL
00885 #define SP5_REG SPL
00886 #define SP6_REG SPL
00887 #define SP7_REG SPL
00888
00889
00890 #define JTRF_REG MCUSR
00891 #define PORF_REG MCUSR
00892 #define EXTRF_REG MCUSR
00893 #define BORF_REG MCUSR
00894 #define WDRF_REG MCUSR
00895
00896
00897 #define EERE_REG EECR
00898 #define EEWE_REG EECR
00899 #define EEMWE_REG EECR
00900 #define EERIE_REG EECR
00901
00902
00903 #define SE_REG SMCR
00904 #define SM0_REG SMCR
00905 #define SM1_REG SMCR
00906 #define SM2_REG SMCR
00907
00908
00909 #define TWIE_REG TWCR
00910 #define TWEN_REG TWCR
00911 #define TWWC_REG TWCR
00912 #define TWSTO_REG TWCR
00913 #define TWSTA_REG TWCR
00914 #define TWEA_REG TWCR
00915 #define TWINT_REG TWCR
00916
00917
00918 #define CS20_REG TCCR2A
00919 #define CS21_REG TCCR2A
00920 #define CS22_REG TCCR2A
00921 #define WGM21_REG TCCR2A
00922 #define COM2A0_REG TCCR2A
00923 #define COM2A1_REG TCCR2A
00924 #define WGM20_REG TCCR2A
00925 #define FOC2A_REG TCCR2A
00926
00927
00928
00929
00930
00931
00932
00933
00934
00935
00936
00937
00938
00939
00940
00941
00942
00943
00944 #define TWPS0_REG TWSR
00945 #define TWPS1_REG TWSR
00946 #define TWS3_REG TWSR
00947 #define TWS4_REG TWSR
00948 #define TWS5_REG TWSR
00949 #define TWS6_REG TWSR
00950 #define TWS7_REG TWSR
00951
00952
00953 #define INDX0_REG CANPAGE
00954 #define INDX1_REG CANPAGE
00955 #define INDX2_REG CANPAGE
00956 #define AINC_REG CANPAGE
00957 #define MOBNB0_REG CANPAGE
00958 #define MOBNB1_REG CANPAGE
00959 #define MOBNB2_REG CANPAGE
00960 #define MOBNB3_REG CANPAGE
00961
00962
00963 #define JTD_REG MCUCR
00964 #define IVCE_REG MCUCR
00965 #define IVSEL_REG MCUCR
00966 #define PUD_REG MCUCR
00967
00968
00969 #define PINC0_REG PINC
00970 #define PINC1_REG PINC
00971 #define PINC2_REG PINC
00972 #define PINC3_REG PINC
00973 #define PINC4_REG PINC
00974 #define PINC5_REG PINC
00975 #define PINC6_REG PINC
00976 #define PINC7_REG PINC
00977
00978
00979 #define OCR1CL0_REG OCR1CL
00980 #define OCR1CL1_REG OCR1CL
00981 #define OCR1CL2_REG OCR1CL
00982 #define OCR1CL3_REG OCR1CL
00983 #define OCR1CL4_REG OCR1CL
00984 #define OCR1CL5_REG OCR1CL
00985 #define OCR1CL6_REG OCR1CL
00986 #define OCR1CL7_REG OCR1CL
00987
00988
00989 #define OCR1CH0_REG OCR1CH
00990 #define OCR1CH1_REG OCR1CH
00991 #define OCR1CH2_REG OCR1CH
00992 #define OCR1CH3_REG OCR1CH
00993 #define OCR1CH4_REG OCR1CH
00994 #define OCR1CH5_REG OCR1CH
00995 #define OCR1CH6_REG OCR1CH
00996 #define OCR1CH7_REG OCR1CH
00997
00998
00999 #define OCDR0_REG OCDR
01000 #define OCDR1_REG OCDR
01001 #define OCDR2_REG OCDR
01002 #define OCDR3_REG OCDR
01003 #define OCDR4_REG OCDR
01004 #define OCDR5_REG OCDR
01005 #define OCDR6_REG OCDR
01006 #define OCDR7_REG OCDR
01007
01008
01009 #define PINA0_REG PINA
01010 #define PINA1_REG PINA
01011 #define PINA2_REG PINA
01012 #define PINA3_REG PINA
01013 #define PINA4_REG PINA
01014 #define PINA5_REG PINA
01015 #define PINA6_REG PINA
01016 #define PINA7_REG PINA
01017
01018
01019 #define AERR_REG CANSTMOB
01020 #define FERR_REG CANSTMOB
01021 #define CERR_REG CANSTMOB
01022 #define SERR_REG CANSTMOB
01023 #define BERR_REG CANSTMOB
01024 #define RXOK_REG CANSTMOB
01025 #define TXOK_REG CANSTMOB
01026 #define DLCW_REG CANSTMOB
01027
01028
01029 #define TXB81_REG UCSR1B
01030 #define RXB81_REG UCSR1B
01031 #define UCSZ12_REG UCSR1B
01032 #define TXEN1_REG UCSR1B
01033 #define RXEN1_REG UCSR1B
01034 #define UDRIE1_REG UCSR1B
01035 #define TXCIE1_REG UCSR1B
01036 #define RXCIE1_REG UCSR1B
01037
01038
01039 #define UCPOL1_REG UCSR1C
01040 #define UCSZ10_REG UCSR1C
01041 #define UCSZ11_REG UCSR1C
01042 #define USBS1_REG UCSR1C
01043 #define UPM10_REG UCSR1C
01044 #define UPM11_REG UCSR1C
01045 #define UMSEL1_REG UCSR1C
01046
01047
01048 #define MPCM1_REG UCSR1A
01049 #define U2X1_REG UCSR1A
01050 #define UPE1_REG UCSR1A
01051 #define DOR1_REG UCSR1A
01052 #define FE1_REG UCSR1A
01053 #define UDRE1_REG UCSR1A
01054 #define TXC1_REG UCSR1A
01055 #define RXC1_REG UCSR1A
01056
01057
01058 #define DDB0_REG DDRB
01059 #define DDB1_REG DDRB
01060 #define DDB2_REG DDRB
01061 #define DDB3_REG DDRB
01062 #define DDB4_REG DDRB
01063 #define DDB5_REG DDRB
01064 #define DDB6_REG DDRB
01065 #define DDB7_REG DDRB
01066
01067
01068 #define TWD0_REG TWDR
01069 #define TWD1_REG TWDR
01070 #define TWD2_REG TWDR
01071 #define TWD3_REG TWDR
01072 #define TWD4_REG TWDR
01073 #define TWD5_REG TWDR
01074 #define TWD6_REG TWDR
01075 #define TWD7_REG TWDR
01076
01077
01078 #define PORTB0_REG PORTB
01079 #define PORTB1_REG PORTB
01080 #define PORTB2_REG PORTB
01081 #define PORTB3_REG PORTB
01082 #define PORTB4_REG PORTB
01083 #define PORTB5_REG PORTB
01084 #define PORTB6_REG PORTB
01085 #define PORTB7_REG PORTB
01086
01087
01088 #define ADPS0_REG ADCSRA
01089 #define ADPS1_REG ADCSRA
01090 #define ADPS2_REG ADCSRA
01091 #define ADIE_REG ADCSRA
01092 #define ADIF_REG ADCSRA
01093 #define ADATE_REG ADCSRA
01094 #define ADSC_REG ADCSRA
01095 #define ADEN_REG ADCSRA
01096
01097
01098 #define ENMOB0_REG CANEN2
01099 #define ENMOB1_REG CANEN2
01100 #define ENMOB2_REG CANEN2
01101 #define ENMOB3_REG CANEN2
01102 #define ENMOB4_REG CANEN2
01103 #define ENMOB5_REG CANEN2
01104 #define ENMOB6_REG CANEN2
01105 #define ENMOB7_REG CANEN2
01106
01107
01108 #define ENMOB8_REG CANEN1
01109 #define ENMOB9_REG CANEN1
01110 #define ENMOB10_REG CANEN1
01111 #define ENMOB11_REG CANEN1
01112 #define ENMOB12_REG CANEN1
01113 #define ENMOB13_REG CANEN1
01114 #define ENMOB14_REG CANEN1
01115
01116
01117 #define ADTS0_REG ADCSRB
01118 #define ADTS1_REG ADCSRB
01119 #define ADTS2_REG ADCSRB
01120 #define ADHSM_REG ADCSRB
01121 #define ACME_REG ADCSRB
01122
01123
01124 #define WGM10_REG TCCR1A
01125 #define WGM11_REG TCCR1A
01126 #define COM1C0_REG TCCR1A
01127 #define COM1C1_REG TCCR1A
01128 #define COM1B0_REG TCCR1A
01129 #define COM1B1_REG TCCR1A
01130 #define COM1A0_REG TCCR1A
01131 #define COM1A1_REG TCCR1A
01132
01133
01134 #define OCR0A0_REG OCR0A
01135 #define OCR0A1_REG OCR0A
01136 #define OCR0A2_REG OCR0A
01137 #define OCR0A3_REG OCR0A
01138 #define OCR0A4_REG OCR0A
01139 #define OCR0A5_REG OCR0A
01140 #define OCR0A6_REG OCR0A
01141 #define OCR0A7_REG OCR0A
01142
01143
01144 #define ACIS0_REG ACSR
01145 #define ACIS1_REG ACSR
01146 #define ACIC_REG ACSR
01147 #define ACIE_REG ACSR
01148 #define ACI_REG ACSR
01149 #define ACO_REG ACSR
01150 #define ACBG_REG ACSR
01151 #define ACD_REG ACSR
01152
01153
01154 #define MPCM0_REG UCSR0A
01155 #define U2X0_REG UCSR0A
01156 #define UPE0_REG UCSR0A
01157 #define DOR0_REG UCSR0A
01158 #define FE0_REG UCSR0A
01159 #define UDRE0_REG UCSR0A
01160 #define TXC0_REG UCSR0A
01161 #define RXC0_REG UCSR0A
01162
01163
01164 #define FOC1C_REG TCCR1C
01165 #define FOC1B_REG TCCR1C
01166 #define FOC1A_REG TCCR1C
01167
01168
01169 #define ICR3H0_REG ICR3H
01170 #define ICR3H1_REG ICR3H
01171 #define ICR3H2_REG ICR3H
01172 #define ICR3H3_REG ICR3H
01173 #define ICR3H4_REG ICR3H
01174 #define ICR3H5_REG ICR3H
01175 #define ICR3H6_REG ICR3H
01176 #define ICR3H7_REG ICR3H
01177
01178
01179 #define DDE0_REG DDRE
01180 #define DDE1_REG DDRE
01181 #define DDE2_REG DDRE
01182 #define DDE3_REG DDRE
01183 #define DDE4_REG DDRE
01184 #define DDE5_REG DDRE
01185 #define DDE6_REG DDRE
01186 #define DDE7_REG DDRE
01187
01188
01189 #define PORTD0_REG PORTD
01190 #define PORTD1_REG PORTD
01191 #define PORTD2_REG PORTD
01192 #define PORTD3_REG PORTD
01193 #define PORTD4_REG PORTD
01194 #define PORTD5_REG PORTD
01195 #define PORTD6_REG PORTD
01196 #define PORTD7_REG PORTD
01197
01198
01199 #define ICR3L0_REG ICR3L
01200 #define ICR3L1_REG ICR3L
01201 #define ICR3L2_REG ICR3L
01202 #define ICR3L3_REG ICR3L
01203 #define ICR3L4_REG ICR3L
01204 #define ICR3L5_REG ICR3L
01205 #define ICR3L6_REG ICR3L
01206 #define ICR3L7_REG ICR3L
01207
01208
01209 #define PORTE0_REG PORTE
01210 #define PORTE1_REG PORTE
01211 #define PORTE2_REG PORTE
01212 #define PORTE3_REG PORTE
01213 #define PORTE4_REG PORTE
01214 #define PORTE5_REG PORTE
01215 #define PORTE6_REG PORTE
01216 #define PORTE7_REG PORTE
01217
01218
01219 #define SPMEN_REG SPMCSR
01220 #define PGERS_REG SPMCSR
01221 #define PGWRT_REG SPMCSR
01222 #define BLBSET_REG SPMCSR
01223 #define RWWSRE_REG SPMCSR
01224 #define RWWSB_REG SPMCSR
01225 #define SPMIE_REG SPMCSR
01226
01227
01228 #define PRS0_REG CANBT2
01229 #define PRS1_REG CANBT2
01230 #define PRS2_REG CANBT2
01231 #define SJW0_REG CANBT2
01232 #define SJW1_REG CANBT2
01233
01234
01235 #define SMP_REG CANBT3
01236 #define PHS10_REG CANBT3
01237 #define PHS11_REG CANBT3
01238 #define PHS12_REG CANBT3
01239 #define PHS20_REG CANBT3
01240 #define PHS21_REG CANBT3
01241 #define PHS22_REG CANBT3
01242
01243
01244 #define ADCL0_REG ADCL
01245 #define ADCL1_REG ADCL
01246 #define ADCL2_REG ADCL
01247 #define ADCL3_REG ADCL
01248 #define ADCL4_REG ADCL
01249 #define ADCL5_REG ADCL
01250 #define ADCL6_REG ADCL
01251 #define ADCL7_REG ADCL
01252
01253
01254 #define BRP0_REG CANBT1
01255 #define BRP1_REG CANBT1
01256 #define BRP2_REG CANBT1
01257 #define BRP3_REG CANBT1
01258 #define BRP4_REG CANBT1
01259 #define BRP5_REG CANBT1
01260
01261
01262 #define ADCH0_REG ADCH
01263 #define ADCH1_REG ADCH
01264 #define ADCH2_REG ADCH
01265 #define ADCH3_REG ADCH
01266 #define ADCH4_REG ADCH
01267 #define ADCH5_REG ADCH
01268 #define ADCH6_REG ADCH
01269 #define ADCH7_REG ADCH
01270
01271
01272 #define OCR3BL0_REG OCR3BL
01273 #define OCR3BL1_REG OCR3BL
01274 #define OCR3BL2_REG OCR3BL
01275 #define OCR3BL3_REG OCR3BL
01276 #define OCR3BL4_REG OCR3BL
01277 #define OCR3BL5_REG OCR3BL
01278 #define OCR3BL6_REG OCR3BL
01279 #define OCR3BL7_REG OCR3BL
01280
01281
01282 #define OCR3BH0_REG OCR3BH
01283 #define OCR3BH1_REG OCR3BH
01284 #define OCR3BH2_REG OCR3BH
01285 #define OCR3BH3_REG OCR3BH
01286 #define OCR3BH4_REG OCR3BH
01287 #define OCR3BH5_REG OCR3BH
01288 #define OCR3BH6_REG OCR3BH
01289 #define OCR3BH7_REG OCR3BH
01290
01291
01292 #define TOIE2_REG TIMSK2
01293 #define OCIE2A_REG TIMSK2
01294
01295
01296 #define TOIE3_REG TIMSK3
01297 #define OCIE3A_REG TIMSK3
01298 #define OCIE3B_REG TIMSK3
01299 #define OCIE3C_REG TIMSK3
01300 #define ICIE3_REG TIMSK3
01301
01302
01303 #define TOIE0_REG TIMSK0
01304 #define OCIE0A_REG TIMSK0
01305
01306
01307 #define TOIE1_REG TIMSK1
01308 #define OCIE1A_REG TIMSK1
01309 #define OCIE1B_REG TIMSK1
01310 #define OCIE1C_REG TIMSK1
01311 #define ICIE1_REG TIMSK1
01312
01313
01314 #define XMM0_REG XMCRB
01315 #define XMM1_REG XMCRB
01316 #define XMM2_REG XMCRB
01317 #define XMBK_REG XMCRB
01318
01319
01320 #define SRW00_REG XMCRA
01321 #define SRW01_REG XMCRA
01322 #define SRW10_REG XMCRA
01323 #define SRW11_REG XMCRA
01324 #define SRL0_REG XMCRA
01325 #define SRL1_REG XMCRA
01326 #define SRL2_REG XMCRA
01327 #define SRE_REG XMCRA
01328
01329
01330 #define TCNT1L0_REG TCNT1L
01331 #define TCNT1L1_REG TCNT1L
01332 #define TCNT1L2_REG TCNT1L
01333 #define TCNT1L3_REG TCNT1L
01334 #define TCNT1L4_REG TCNT1L
01335 #define TCNT1L5_REG TCNT1L
01336 #define TCNT1L6_REG TCNT1L
01337 #define TCNT1L7_REG TCNT1L
01338
01339
01340 #define PINB0_REG PINB
01341 #define PINB1_REG PINB
01342 #define PINB2_REG PINB
01343 #define PINB3_REG PINB
01344 #define PINB4_REG PINB
01345 #define PINB5_REG PINB
01346 #define PINB6_REG PINB
01347 #define PINB7_REG PINB
01348
01349
01350 #define INTF0_REG EIFR
01351 #define INTF1_REG EIFR
01352 #define INTF2_REG EIFR
01353 #define INTF3_REG EIFR
01354 #define INTF4_REG EIFR
01355 #define INTF5_REG EIFR
01356 #define INTF6_REG EIFR
01357 #define INTF7_REG EIFR
01358
01359
01360 #define PING0_REG PING
01361 #define PING1_REG PING
01362 #define PING2_REG PING
01363 #define PING3_REG PING
01364 #define PING4_REG PING
01365
01366
01367 #define PINF0_REG PINF
01368 #define PINF1_REG PINF
01369 #define PINF2_REG PINF
01370 #define PINF3_REG PINF
01371 #define PINF4_REG PINF
01372 #define PINF5_REG PINF
01373 #define PINF6_REG PINF
01374 #define PINF7_REG PINF
01375
01376
01377 #define PINE0_REG PINE
01378 #define PINE1_REG PINE
01379 #define PINE2_REG PINE
01380 #define PINE3_REG PINE
01381 #define PINE4_REG PINE
01382 #define PINE5_REG PINE
01383 #define PINE6_REG PINE
01384 #define PINE7_REG PINE
01385
01386
01387 #define PIND0_REG PIND
01388 #define PIND1_REG PIND
01389 #define PIND2_REG PIND
01390 #define PIND3_REG PIND
01391 #define PIND4_REG PIND
01392 #define PIND5_REG PIND
01393 #define PIND6_REG PIND
01394 #define PIND7_REG PIND
01395
01396
01397 #define OCR1AH0_REG OCR1AH
01398 #define OCR1AH1_REG OCR1AH
01399 #define OCR1AH2_REG OCR1AH
01400 #define OCR1AH3_REG OCR1AH
01401 #define OCR1AH4_REG OCR1AH
01402 #define OCR1AH5_REG OCR1AH
01403 #define OCR1AH6_REG OCR1AH
01404 #define OCR1AH7_REG OCR1AH
01405
01406
01407 #define OCR1AL0_REG OCR1AL
01408 #define OCR1AL1_REG OCR1AL
01409 #define OCR1AL2_REG OCR1AL
01410 #define OCR1AL3_REG OCR1AL
01411 #define OCR1AL4_REG OCR1AL
01412 #define OCR1AL5_REG OCR1AL
01413 #define OCR1AL6_REG OCR1AL
01414 #define OCR1AL7_REG OCR1AL
01415
01416
01417 #define TOV0_REG TIFR0
01418 #define OCF0A_REG TIFR0
01419
01420
01421 #define AD0_PORT PORTA
01422 #define AD0_BIT 0
01423
01424 #define AD1_PORT PORTA
01425 #define AD1_BIT 1
01426
01427 #define AD2_PORT PORTA
01428 #define AD2_BIT 2
01429
01430 #define AD3_PORT PORTA
01431 #define AD3_BIT 3
01432
01433 #define AD4_PORT PORTA
01434 #define AD4_BIT 4
01435
01436 #define AD5_PORT PORTA
01437 #define AD5_BIT 5
01438
01439 #define AD6_PORT PORTA
01440 #define AD6_BIT 6
01441
01442 #define AD7_PORT PORTA
01443 #define AD7_BIT 7
01444
01445 #define SS_PORT PORTB
01446 #define SS_BIT 0
01447
01448 #define SCK_PORT PORTB
01449 #define SCK_BIT 1
01450
01451 #define MOSI_PORT PORTB
01452 #define MOSI_BIT 2
01453
01454 #define MISO_PORT PORTB
01455 #define MISO_BIT 3
01456
01457 #define OC0_PORT PORTB
01458 #define OC0_BIT 4
01459 #define PWM0_PORT PORTB
01460 #define PWM0_BIT 4
01461
01462 #define OC1A_PORT PORTB
01463 #define OC1A_BIT 5
01464 #define PWM1A_PORT PORTB
01465 #define PWM1A_BIT 5
01466
01467 #define OC1B_PORT PORTB
01468 #define OC1B_BIT 6
01469 #define PWM1B_PORT PORTB
01470 #define PWM1B_BIT 6
01471
01472 #define OC2_PORT PORTB
01473 #define OC2_BIT 7
01474 #define PWM2_PORT PORTB
01475 #define PWM2_BIT 7
01476 #define OC1C_PORT PORTB
01477 #define OC1C_BIT 7
01478
01479 #define A8_PORT PORTC
01480 #define A8_BIT 0
01481
01482 #define A9_PORT PORTC
01483 #define A9_BIT 1
01484
01485 #define A10_PORT PORTC
01486 #define A10_BIT 2
01487
01488 #define A11_PORT PORTC
01489 #define A11_BIT 3
01490
01491 #define A12_PORT PORTC
01492 #define A12_BIT 4
01493
01494 #define A13_PORT PORTC
01495 #define A13_BIT 5
01496
01497 #define A14_PORT PORTC
01498 #define A14_BIT 6
01499
01500 #define A15_PORT PORTC
01501 #define A15_BIT 7
01502
01503 #define SCL_PORT PORTD
01504 #define SCL_BIT 0
01505 #define INT0_PORT PORTD
01506 #define INT0_BIT 0
01507
01508 #define SDA_PORT PORTD
01509 #define SDA_BIT 1
01510 #define INT1_PORT PORTD
01511 #define INT1_BIT 1
01512
01513 #define RXD1_PORT PORTD
01514 #define RXD1_BIT 2
01515 #define INT2_PORT PORTD
01516 #define INT2_BIT 2
01517
01518 #define TXD1_PORT PORTD
01519 #define TXD1_BIT 3
01520 #define INT3_PORT PORTD
01521 #define INT3_BIT 3
01522
01523 #define IC1_PORT PORTD
01524 #define IC1_BIT 4
01525
01526 #define XCK1_PORT PORTD
01527 #define XCK1_BIT 5
01528
01529 #define T1_PORT PORTD
01530 #define T1_BIT 6
01531
01532 #define T2_PORT PORTD
01533 #define T2_BIT 7
01534
01535 #define RXD0_PORT PORTE
01536 #define RXD0_BIT 0
01537 #define PDI_PORT PORTE
01538 #define PDI_BIT 0
01539
01540 #define TXD0_PORT PORTE
01541 #define TXD0_BIT 1
01542 #define PDO_PORT PORTE
01543 #define PDO_BIT 1
01544
01545 #define XCK0_PORT PORTE
01546 #define XCK0_BIT 2
01547 #define AIN0_PORT PORTE
01548 #define AIN0_BIT 2
01549
01550 #define OC3A_PORT PORTE
01551 #define OC3A_BIT 3
01552 #define AIN1_PORT PORTE
01553 #define AIN1_BIT 3
01554
01555 #define OC3B_PORT PORTE
01556 #define OC3B_BIT 4
01557 #define INT4_PORT PORTE
01558 #define INT4_BIT 4
01559
01560 #define OC3C_PORT PORTE
01561 #define OC3C_BIT 5
01562 #define INT5_PORT PORTE
01563 #define INT5_BIT 5
01564
01565 #define T3_PORT PORTE
01566 #define T3_BIT 6
01567 #define INT6_PORT PORTE
01568 #define INT6_BIT 6
01569
01570 #define IC3_PORT PORTE
01571 #define IC3_BIT 7
01572 #define INT7_PORT PORTE
01573 #define INT7_BIT 7
01574
01575 #define ADC0_PORT PORTF
01576 #define ADC0_BIT 0
01577
01578 #define ADC1_PORT PORTF
01579 #define ADC1_BIT 1
01580
01581 #define ADC2_PORT PORTF
01582 #define ADC2_BIT 2
01583
01584 #define ADC3_PORT PORTF
01585 #define ADC3_BIT 3
01586
01587 #define ADC4_PORT PORTF
01588 #define ADC4_BIT 4
01589 #define TCK_PORT PORTF
01590 #define TCK_BIT 4
01591
01592 #define ADC5_PORT PORTF
01593 #define ADC5_BIT 5
01594 #define TMS_PORT PORTF
01595 #define TMS_BIT 5
01596
01597 #define ADC6_PORT PORTF
01598 #define ADC6_BIT 6
01599 #define TD0_PORT PORTF
01600 #define TD0_BIT 6
01601
01602 #define ADC7_PORT PORTF
01603 #define ADC7_BIT 7
01604 #define TDI_PORT PORTF
01605 #define TDI_BIT 7
01606
01607 #define WR_PORT PORTG
01608 #define WR_BIT 0
01609
01610 #define RD_PORT PORTG
01611 #define RD_BIT 1
01612
01613 #define ALE_PORT PORTG
01614 #define ALE_BIT 2
01615
01616 #define TOSC2_PORT PORTG
01617 #define TOSC2_BIT 3
01618
01619 #define TOSC1_PORT PORTG
01620 #define TOSC1_BIT 4
01621
01622